KR20070069913A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20070069913A
KR20070069913A KR1020050132571A KR20050132571A KR20070069913A KR 20070069913 A KR20070069913 A KR 20070069913A KR 1020050132571 A KR1020050132571 A KR 1020050132571A KR 20050132571 A KR20050132571 A KR 20050132571A KR 20070069913 A KR20070069913 A KR 20070069913A
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spacer
film
spacers
semiconductor device
gate electrode
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Korean (ko)
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신기수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method for fabricating a semiconductor device is provided to prevent the etching loss of a first spacer by forming a third spacer on a second spacer and then forming the first spacer on the third spacer. Plural gate electrodes(22) are formed on a semiconductor substrate(21), and first and second material layers for spacers are formed along surfaces of the gate electrodes on the substrate. The second material layer is selectively etched to form a second spacer(24). A third material layer for a spacer is formed along a surface of the gate electrode on the substrate. The third material layer is selectively etched to form a third spacer, and the first material layer is selectively etched to form a first spacer. Silicide is formed on both sides of the gate electrode.

Description

반도체 소자 제조 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 단면도,1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 게이트 전극21 semiconductor substrate 22 gate electrode

23 : 제1스페이서 24 : 제2스페이서23: first spacer 24: second spacer

25 : 제1층간절연막 26 : 제2층간절연막25: first interlayer insulating film 26: second interlayer insulating film

27 : 마스크 28a : 제3스페이서27: mask 28a: third spacer

29 : 코발트살리사이드29: cobalt salicide

본 발명은 반도체 제조 기술에 관한 것으로, 특히 코발트 살리사이드(Co Salicide) 공정을 적용하는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device manufacturing method using a cobalt salicide process.

일반적으로, 주변회로영역(Periphery)에서는 자기 정렬 콘택 마스크를 형성한 후에 산화막 및 질화막 스페이서 식각을 진행하는데, 이 때, 스페이서 질화막의 손실이 발생하여 충분한 스페이서 질화막 너비를 확보하지 못한다. In general, in the peripheral circuit region (Periphery), after forming the self-aligned contact mask, the oxide film and the nitride film spacer are etched. In this case, a loss of the spacer nitride film occurs, so that a sufficient spacer nitride film width cannot be secured.

이어서, 저전압과 고속동작 소자를 구현하기 위해 코발트살리사이드(Co-Salicide) 공정이 진행되는데, 이 때 측면 확산(Lateral Diffusion)이 발생하기 때문에 게이트 펀치 스루(Punch Through) 현상이 발생하는 문제가 있다.Subsequently, a cobalt salicide process is performed to implement a low voltage and high speed operation device. At this time, a side punch occurs and a gate punch through phenomenon occurs. .

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자 제조 방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 셀영역과 주변회로영역이 정의된 반도체 기판(11) 상에 다수의 게이트 전극(12)을 형성한다.As shown in FIG. 1A, a plurality of gate electrodes 12 are formed on a semiconductor substrate 11 in which cell regions and peripheral circuit regions are defined.

이어서, 게이트 전극(12) 측벽에 제1스페이서(13) 및 제2스페이서(14)를 형성한다. 주변회로영역에서는 게이트 전극(12) 측벽에 제2스페이서(14)만 형성하고, 제1스페이서용 절연막(13)은 식각하지 않는다.Subsequently, the first spacer 13 and the second spacer 14 are formed on the sidewalls of the gate electrode 12. In the peripheral circuit region, only the second spacer 14 is formed on the sidewall of the gate electrode 12, and the first spacer insulating layer 13 is not etched.

다음으로, 반도체 기판(11)의 전면에 제1층간절연막(15) 및 제2층간절연막(16)을 차례로 증착한다. 그리고 나서, 제2층간절연막(16) 상에 주변회로영역을 오 픈하는 마스크(17)를 증착한다.Next, the first interlayer insulating film 15 and the second interlayer insulating film 16 are sequentially deposited on the entire surface of the semiconductor substrate 11. Then, a mask 17 is opened on the second interlayer insulating film 16 to open the peripheral circuit region.

도 1b에 도시된 바와 같이, 마스크(17)를 사용하여 제2층간절연막(16) 및 제1층간절연막(15)을 선택적으로 식각하여 주변회로영역에 형성된 게이트 전극(12)의 제2스페이서(14)를 노출시킨다. 이어서, 마스크(17)를 스트립한다.As shown in FIG. 1B, the second spacer of the gate electrode 12 formed in the peripheral circuit region by selectively etching the second interlayer insulating film 16 and the first interlayer insulating film 15 using the mask 17 ( 14). Next, the mask 17 is stripped.

도 1c에 도시된 바와 같이, 주변회로영역에 형성된 게이트 전극(12)의 제1스페이서용 절연막(13)을 식각하여 제1스페이서(13a)를 형성한다.As illustrated in FIG. 1C, the first spacer insulating layer 13 of the gate electrode 12 formed in the peripheral circuit region is etched to form a first spacer 13a.

도 1d에 도시된 바와 같이, 코발트 살리사이드 공정을 진행하여 게이트 전극(12)의 양측 하부에 코발트 살리사이드(18)를 형성한다.As shown in FIG. 1D, the cobalt salicide process is performed to form cobalt salicide 18 on both lower portions of the gate electrode 12.

그러나, 상술한 종래 기술에서는 제1스페이서 식각시 식각 손실이 발생하여, 스페이서 너비가 감소가 발생함으로써, 코발트 살리사이드 공정 후, 게이트 전극 양측면(화살표 표시)으로 확산(Lateral Diffusion)이 발생하여 채널에 침투하는 게이트 펀치(Gate Punch)와 같은 문제가 있다.However, in the above-described conventional technique, etching loss occurs during etching of the first spacer, and the spacer width decreases, so that after the cobalt salicide process, the diffusion (Lateral Diffusion) occurs on both sides (arrows) of the gate electrode, and thus the channel is formed in the channel. There is a problem, such as a penetrating gate punch.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 살리사이드 공정에서 발생하는 측면 확산에 의한 게이트 사이에 발생하는 펀치 스루를 방지하는데 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing punch through occurring between gates due to side diffusion occurring in a salicide process.

상기 목적을 달성하기 위한 특징적인 본 발명의 반도체 소자 제조 방법은 반 도체 기판 상에 다수의 게이트 전극을 형성하는 단계, 상기 반도체 기판 및 게이트 전극을 표면을 따라 스페이서용 제1 및 제2절연막을 차례로 형성하는 단계, 상기 스페이서용 제2절연막을 선택적으로 식각하여 제2스페이서를 형성하는 단계, 상기 반도체 기판 및 상기 제2스페이서가 형성된 게이트 전극의 표면을 따라 스페이서용 제3절연막을 형성하는 단계, 상기 스페이서용 제3절연막을 선택적으로 식각하여 제3스페이서를 형성하는 단계, 상기 스페이서용 제1절연막을 선택적으로 식각하여 제1스페이서를 형성하는 단계, 및 상기 게이트 전극 양측 하부에 실리사이드를 형성하는 단계단계를 포함한다.A semiconductor device fabrication method of the present invention for achieving the above object comprises the steps of forming a plurality of gate electrodes on a semiconductor substrate, the first and second insulating films for spacers in turn along the surface of the semiconductor substrate and the gate electrode Forming a second spacer by selectively etching the second insulating layer for the spacer, forming a third insulating layer for the spacer along a surface of the gate electrode on which the semiconductor substrate and the second spacer are formed; Selectively etching a third insulating layer for spacers to form a third spacer, selectively etching the first insulating layer for spacers to form a first spacer, and forming silicide on both sides of the gate electrode It includes.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 셀영역과 주변회로영역이 정의된 반도체 기판(21) 상에 다수의 게이트 전극(22)을 형성한다.As shown in FIG. 2A, a plurality of gate electrodes 22 are formed on the semiconductor substrate 21 where the cell region and the peripheral circuit region are defined.

이어서, 게이트 전극(22) 측벽에 제1스페이서(23) 및 제2스페이서(24)를 형성한다. 주변회로영역에서는 게이트 전극(22) 측벽에 제2스페이서(24)만 형성하고, 제1스페이서용 물질막(23)은 식각하지 않는다. 한편, 제1스페이서용 물질막(23) 및 제2스페이서(24)는, 산화막 또는 질화막을 사용하여 형성한다.Subsequently, the first spacer 23 and the second spacer 24 are formed on the sidewalls of the gate electrode 22. In the peripheral circuit region, only the second spacer 24 is formed on the sidewall of the gate electrode 22, and the material layer 23 for the first spacer is not etched. In addition, the 1st spacer material film 23 and the 2nd spacer 24 are formed using an oxide film or a nitride film.

다음으로, 반도체 기판(21)의 전면에 제1층간절연막(25) 및 제2층간절연막(26)을 차례로 증착한다. 그리고 나서, 제2층간절연막(26) 상에 주변회로영역을 오픈하는 마스크(27)를 증착한다. 이 때, 마스크(27)는 포토레지스트 패턴이다.Next, the first interlayer insulating film 25 and the second interlayer insulating film 26 are sequentially deposited on the entire surface of the semiconductor substrate 21. Then, a mask 27 for opening the peripheral circuit region is deposited on the second interlayer insulating film 26. At this time, the mask 27 is a photoresist pattern.

이 때, 제1층간절연막(25) 및 제2층간절연막(26)은, BSG(Boro-Silicate-Glass)막, BPSG(Boro-Phospho-Silicate-Glass)막, PSG(Phospho-Silicate-Glass)막, TEOS(Tetra-Ethyl-Ortho-Silicate)막, HDP(High Density Plasma)막, SOG(Spin On Glass)막 또는 APL(Advanced Planarization Layer)막 등을 이용하며, 산화막 계열 이외에 무기 또는 유기 계열의 저유전율막을 이용할 수 있다.In this case, the first interlayer insulating film 25 and the second interlayer insulating film 26 include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, and a PSG (Phospho-Silicate-Glass) film. Film, TEOS (Tetra-Ethyl-Ortho-Silicate) film, HDP (High Density Plasma) film, SOG (Spin On Glass) film or APL (Advanced Planarization Layer) film, etc. A low dielectric constant film can be used.

도 2b에 도시된 바와 같이, 마스크(27)를 사용하여 제2층간절연막(26) 및 제1층간절연막(25)을 선택적으로 식각하여 주변회로영역에 형성된 게이트 전극(22)의 제2스페이서(24)를 노출시킨다. 이어서, 마스크(27)를 스트립한다.As shown in FIG. 2B, the second spacer of the gate electrode 22 formed in the peripheral circuit region by selectively etching the second interlayer insulating layer 26 and the first interlayer insulating layer 25 using the mask 27 ( 24). Next, the mask 27 is stripped.

도 2c에 도시된 바와 같이, 반도체 기판(21) 상의 제1층간절연막(25), 제2층간절연막(26) 및 게이트 전극(22)의 프로파일을 따라 제3스페이서용 물질막(28)을 증착한다. 제3스페이서용 물질막(28)은, 산화막, 질화막, 산화질화막 및 비정질 실리콘막의 그룹에서 선택된 어느 한 물질을 사용할 수 있으며, 50∼100Å의 두께로 형성한다.As shown in FIG. 2C, a third spacer material film 28 is deposited along the profile of the first interlayer insulating film 25, the second interlayer insulating film 26, and the gate electrode 22 on the semiconductor substrate 21. do. As the third spacer material film 28, any material selected from the group consisting of an oxide film, a nitride film, an oxynitride film, and an amorphous silicon film can be used, and is formed to have a thickness of 50 to 100 GPa.

플라즈마 식각을 실시하여 제3스페이서용 물질막(28)을 식각하여 제2스페이서 상에 제3스페이서(28a)를 형성한다. 이 때, 제2층간절연막(26) 상부 및 제1스페이서용 물질막(24) 상에 형성된 제3스페이서용 물질막(28)은 제거되고, 제2층간절연막(25) 및 제1층간절연막(26)의 측벽에는 잔류한다.Plasma etching is performed to etch the third spacer material film 28 to form a third spacer 28a on the second spacer. At this time, the third spacer material film 28 formed on the second interlayer insulating film 26 and on the first spacer material film 24 is removed, and the second interlayer insulating film 25 and the first interlayer insulating film ( It remains on the side wall of 26).

도 2e에 도시된 바와 같이, 제1스페이서용 물질막(24)을 식각하여 게이트 전극(22)의 양측 하부를 오픈한다. 이어서, 코발트 살리사이드 공정을 진행하여 게이트 전극(22) 양측 하부에 코발트 살리사이드(29)를 형성한다.As illustrated in FIG. 2E, the first spacer material layer 24 is etched to open lower portions of both sides of the gate electrode 22. Subsequently, a cobalt salicide process is performed to form cobalt salicide 29 on both sides of the gate electrode 22.

상술한 바와 같이, 제1스페이서를 제2스페이서 식각시 동시에 식각하는 것이 아니라, 제2스페이서 상에 제3스페이서를 형성하고, 제3스페이서 형성 후 제1스페이서를 형성함으로써, 제1스페이서의 식각 손실을 방지할 수 있다. 따라서, 코발트 살리사이드 공정을 진행한 후에도 측면 확산에 의한 거리를 확보할 수 있으므로, 게이트 채널 펀치를 방지할 수 있다As described above, the first spacer is not etched at the same time when the second spacer is etched, but the third spacer is formed on the second spacer, and the first spacer is formed after the third spacer is formed, thereby reducing the etching loss of the first spacer. Can be prevented. Therefore, even after the cobalt salicide process is performed, the distance due to lateral diffusion can be ensured, thereby preventing the gate channel punch.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 저전압 고속 동작용 GDDR 제품에서, 코발트살리사이드(Co-Salicide) 공정을 적용할 때, 주변회로영역의 자기 정렬 영역 콘택 오픈시 발생하는, 질화막 스페이서의 너비 감소를 방지하고, 충분한 스페이서 너비를 확보하기 위해, 자기 정렬 영역 콘택 식각 후에, 산화막 스페이서의 증착 및 식각 공정 후에 질화막 스페이서 식각을 진행함으로써, 후속 코발트살리사이드 공정에서 측면 확산 에 의한 게이트의 펀치 스루를 방지하여, 안정된 고속 동작 트랜지스터의 특성을 확보할 수 있다.The present invention described above is sufficient to prevent the reduction of the width of the nitride film spacer, which occurs when opening the self-aligned region contact of the peripheral circuit region, when applying the cobalt salicide process in the GDDR product for low voltage high speed operation. In order to secure the spacer width, after the self-aligned region contact etching, the nitride spacer etching is performed after the deposition and etching process of the oxide spacer, thereby preventing the punch-through of the gate due to the side diffusion in the subsequent cobalt salicide process, thereby achieving stable high speed operation. The characteristics of the transistor can be secured.

따라서, 저파워 고속 동작 제품 개발에 크게 기여하는 효과가 있다.Therefore, there is an effect that greatly contributes to the development of low-power high-speed operation product.

Claims (14)

반도체 기판 상에 다수의 게이트 전극을 형성하는 단계;Forming a plurality of gate electrodes on the semiconductor substrate; 상기 반도체 기판 및 게이트 전극을 표면을 따라 스페이서용 제1 및 제2물질막을 차례로 형성하는 단계;Sequentially forming first and second material films for spacers along surfaces of the semiconductor substrate and the gate electrode; 상기 스페이서용 제2물질막을 선택적으로 식각하여 제2스페이서를 형성하는 단계;Selectively etching the spacer second material layer to form a second spacer; 상기 반도체 기판 및 상기 제2스페이서가 형성된 게이트 전극의 표면을 따라 스페이서용 제3물질막을 형성하는 단계;Forming a third material film for a spacer along a surface of the gate electrode on which the semiconductor substrate and the second spacer are formed; 상기 스페이서용 제3물질막을 선택적으로 식각하여 제3스페이서를 형성하는 단계;Selectively etching the third material layer for the spacer to form a third spacer; 상기 스페이서용 제1물질막을 선택적으로 식각하여 제1스페이서를 형성하는 단계; 및Selectively etching the first material layer for the spacer to form a first spacer; And 상기 게이트 전극 양측 하부에 실리사이드를 형성하는 단계Forming silicide on both sides of the gate electrode; 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제3물질막은, 산화막으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed of an oxide film. 제2항에 있어서,The method of claim 2, 상기 스페이서용 제3물질막은 50∼100Å으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed in 50 ~ 100∼. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제3물질막은, 비정질 실리콘막으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed of an amorphous silicon film. 제4항에 있어서,The method of claim 4, wherein 상기 스페이서용 제3물질막은 50∼100Å으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed in 50 ~ 100∼. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제3물질막은, 질화막으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed of a nitride film. 제6항에 있어서,The method of claim 6, 상기 스페이서용 제3물질막은 50∼100Å으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed in 50 ~ 100∼. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제3물질막은, 산화질화막으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed of an oxynitride film. 제8항에 있어서,The method of claim 8, 상기 스페이서용 제3물질막은 50∼100Å으로 형성하는 반도체 소자 제조 방법.The third material film for spacers is formed in 50 ~ 100∼. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제1물질막 및 상기 스페이서용 제2물질막은 산화막 또는 질화막을 사용하는 반도체 소자 제조 방법.The first material film for the spacer and the second material film for the spacer use an oxide film or a nitride film. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제2물질막을 선택적으로 식각하여 제2스페이서를 형성하는 단계는,Selectively etching the spacer second material layer to form a second spacer; 플라즈마 식각을 진행하는 반도체 소자 제조 방법.A semiconductor device manufacturing method for performing plasma etching. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제3물질막을 선택적으로 식각하여 제3스페이서를 형성하는 단계는,Selectively etching the third material layer for the spacer to form a third spacer; 플라즈마 식각을 진행하는 반도체 소자 제조 방법.A semiconductor device manufacturing method for performing plasma etching. 제1항에 있어서,The method of claim 1, 상기 스페이서용 제1물질막을 선택적으로 식각하여 제1스페이서를 형성하는 단계는,Selectively etching the first material layer for the spacer to form a first spacer, 플라즈마 식각을 진행하는 반도체 소자 제조 방법.A semiconductor device manufacturing method for performing plasma etching. 제1항에 있어서,The method of claim 1, 상기 실리사이드를 형성하는 단계는,Forming the silicide, 코발트 살리사이드를 형성하는 반도체 소자 제조 방법.A semiconductor device manufacturing method for forming cobalt salicide.
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Publication number Priority date Publication date Assignee Title
US9576953B2 (en) 2014-02-03 2017-02-21 Samsung Electronics Co., Ltd. Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9576953B2 (en) 2014-02-03 2017-02-21 Samsung Electronics Co., Ltd. Layout design system, semiconductor device fabricated by using the system and method for fabricating the semiconductor device

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