KR20100001814A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20100001814A KR20100001814A KR1020080061885A KR20080061885A KR20100001814A KR 20100001814 A KR20100001814 A KR 20100001814A KR 1020080061885 A KR1020080061885 A KR 1020080061885A KR 20080061885 A KR20080061885 A KR 20080061885A KR 20100001814 A KR20100001814 A KR 20100001814A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- film
- exposure
- hard mask
- photoresist
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000000945 filler Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000007654 immersion Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a vertical transistor using double exposure.
Recently, in the case of semiconductor devices such as DRAMs, a technique for increasing the degree of integration by forming more transistors in a limited area is required.
For this purpose, a vertical transistor technology capable of putting a memory cell element in a small area has been proposed.
In the case of a memory device, the vertical transistor provides a surrounding gate structure surrounding the vertical channel.
This surround gate structure selectively isotropically etches the channel region to form at 4F2, making the channel region relatively thinner than the source / drain regions.
In the surround gate structure, the front surface of the channel region may be surrounded by the gate electrode to maximize the control power of the gate.
In addition, the surround gate structure provides excellent operating current characteristics due to the large current flow area as well as the short channel effect.
1 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.
Referring to FIG. 1, in general, vertical transistors are formed so that vertical pillars are regularly arranged in the X-axis direction and the Y-axis direction, and form a surround gate to surround the vertical pillars.
At this time, since the vertical filler is formed at the same time using one exposure process, there is a problem in that the pattern is unevenly formed as shown in (a).
In addition, when the vertical dimension (CD) of the vertical filler is formed smaller than the target line width, as shown in (b), there is a problem that the vertical pillar collapses.
On the other hand, when the line width of the vertical pillar is formed larger than the target line width, as shown in (c), there is a problem that a bridge (vertical) occurs between the vertical pillar.
The present invention has the following object.
First, by forming the vertical filler through the second exposure and development process, the line width of the vertical filler can be formed as much as the target line width, thereby preventing the phenomenon that the pattern collapses or the bridge occurs.
Second, by forming a vertical filler by using a photosensitive film pattern of the line / space form it is possible to form a pattern uniformly.
Method for manufacturing a semiconductor device according to the present invention
Forming a photoresist film on the semiconductor substrate;
Exposing and developing the photoresist film with a first exposure mask including a line / space pattern in a first direction to form a first photoresist pattern;
Exposing and developing the first photoresist pattern with a second exposure mask including a line / space pattern in a second direction to form a second photoresist pattern;
Forming a vertical filler using the second photoresist pattern
Characterized in that it comprises a.
Here, the first direction and the second direction is a direction perpendicular to each other,
The exposure process using the first and second exposure masks is performed using any one selected from ArF equipment, immersion ArF equipment, KrF equipment,
Forming a hard mask film and an anti-reflection film on the semiconductor substrate;
The vertical filler forming step
Etching the anti-reflection film and the hard mask film using the second photoresist pattern as an etch mask to form an anti-reflection film pattern and a hard mask film pattern;
Removing the second photoresist pattern and the anti-reflection film pattern;
Etching the semiconductor substrate using the hard mask layer pattern as an etching mask
Characterized in that it comprises a.
The present invention provides the following effects.
First, by forming the vertical filler through the second exposure and development process, the line width of the vertical filler can be formed as much as the target line width, thereby providing an effect of preventing a pattern from collapsing or generating a bridge.
Second, by forming a vertical filler by using a photosensitive film pattern of the line / space form provides an effect that can be uniformly formed.
Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.
2A to 2F illustrate a method of manufacturing a semiconductor device according to the present invention.
Referring to FIG. 2A, a
2B and 2C, the
Here, the
At this time, the line width of the
Next, the
2D and 2E, the first
Here, the
In this case, the line width of the
The first and second directions preferably cross each other, more preferably perpendicular.
In addition, the first and second exposure process is preferably performed using any one selected from ArF equipment, immersion ArF equipment, KrF equipment.
Next, the second development process is performed to develop the exposed
Next, the
Next, the second photosensitive layer pattern 16d and the anti-reflective layer pattern are removed, and the
That is, the present invention can form the line width of the
In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
1 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.
2A to 2E illustrate a method of manufacturing a semiconductor device according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080061885A KR20100001814A (en) | 2008-06-27 | 2008-06-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020080061885A KR20100001814A (en) | 2008-06-27 | 2008-06-27 | Method for manufacturing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20100001814A true KR20100001814A (en) | 2010-01-06 |
Family
ID=41812077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020080061885A KR20100001814A (en) | 2008-06-27 | 2008-06-27 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20100001814A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8278223B2 (en) | 2010-01-15 | 2012-10-02 | Hynix Semiconductor Inc. | Method for forming hole pattern |
-
2008
- 2008-06-27 KR KR1020080061885A patent/KR20100001814A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8278223B2 (en) | 2010-01-15 | 2012-10-02 | Hynix Semiconductor Inc. | Method for forming hole pattern |
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