KR20100001814A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20100001814A
KR20100001814A KR1020080061885A KR20080061885A KR20100001814A KR 20100001814 A KR20100001814 A KR 20100001814A KR 1020080061885 A KR1020080061885 A KR 1020080061885A KR 20080061885 A KR20080061885 A KR 20080061885A KR 20100001814 A KR20100001814 A KR 20100001814A
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KR
South Korea
Prior art keywords
pattern
film
exposure
hard mask
photoresist
Prior art date
Application number
KR1020080061885A
Other languages
Korean (ko)
Inventor
이병훈
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080061885A priority Critical patent/KR20100001814A/en
Publication of KR20100001814A publication Critical patent/KR20100001814A/en

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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE: A method for manufacturing semiconductor device is provided to uniformly form pattern by forming the vertical type filler into the photosensitive pattern of line and space form. CONSTITUTION: The hard mask layer, and the reflection barrier layer and photosensitive film are formed on the semiconductor substrate(10). The photosensitive film is exposed to the first exposure process using the first exposure mask. The first photoresist pattern is formed. The first photoresist pattern is exposed to the second exposure process using the second exposure mask. The second photosensitive pattern is formed. The reflective barrier pattern and hard mask film pattern are formed by etching the reflection barrier layer and hard mask film. The vertical type filler(22) is formed by etching the semiconductor substrate.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a vertical transistor using double exposure.

Recently, in the case of semiconductor devices such as DRAMs, a technique for increasing the degree of integration by forming more transistors in a limited area is required.

For this purpose, a vertical transistor technology capable of putting a memory cell element in a small area has been proposed.

In the case of a memory device, the vertical transistor provides a surrounding gate structure surrounding the vertical channel.

This surround gate structure selectively isotropically etches the channel region to form at 4F2, making the channel region relatively thinner than the source / drain regions.

In the surround gate structure, the front surface of the channel region may be surrounded by the gate electrode to maximize the control power of the gate.

In addition, the surround gate structure provides excellent operating current characteristics due to the large current flow area as well as the short channel effect.

1 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, in general, vertical transistors are formed so that vertical pillars are regularly arranged in the X-axis direction and the Y-axis direction, and form a surround gate to surround the vertical pillars.

At this time, since the vertical filler is formed at the same time using one exposure process, there is a problem in that the pattern is unevenly formed as shown in (a).

In addition, when the vertical dimension (CD) of the vertical filler is formed smaller than the target line width, as shown in (b), there is a problem that the vertical pillar collapses.

On the other hand, when the line width of the vertical pillar is formed larger than the target line width, as shown in (c), there is a problem that a bridge (vertical) occurs between the vertical pillar.

The present invention has the following object.

First, by forming the vertical filler through the second exposure and development process, the line width of the vertical filler can be formed as much as the target line width, thereby preventing the phenomenon that the pattern collapses or the bridge occurs.

Second, by forming a vertical filler by using a photosensitive film pattern of the line / space form it is possible to form a pattern uniformly.

Method for manufacturing a semiconductor device according to the present invention

Forming a photoresist film on the semiconductor substrate;

Exposing and developing the photoresist film with a first exposure mask including a line / space pattern in a first direction to form a first photoresist pattern;

Exposing and developing the first photoresist pattern with a second exposure mask including a line / space pattern in a second direction to form a second photoresist pattern;

Forming a vertical filler using the second photoresist pattern

Characterized in that it comprises a.

Here, the first direction and the second direction is a direction perpendicular to each other,

The exposure process using the first and second exposure masks is performed using any one selected from ArF equipment, immersion ArF equipment, KrF equipment,

Forming a hard mask film and an anti-reflection film on the semiconductor substrate;

The vertical filler forming step

Etching the anti-reflection film and the hard mask film using the second photoresist pattern as an etch mask to form an anti-reflection film pattern and a hard mask film pattern;

Removing the second photoresist pattern and the anti-reflection film pattern;

Etching the semiconductor substrate using the hard mask layer pattern as an etching mask

Characterized in that it comprises a.

The present invention provides the following effects.

First, by forming the vertical filler through the second exposure and development process, the line width of the vertical filler can be formed as much as the target line width, thereby providing an effect of preventing a pattern from collapsing or generating a bridge.

Second, by forming a vertical filler by using a photosensitive film pattern of the line / space form provides an effect that can be uniformly formed.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A to 2F illustrate a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, a hard mask layer 12, an antireflection film 14, and a photosensitive film 16 are formed on the semiconductor substrate 10.

2B and 2C, the photosensitive film 16 is exposed by a primary exposure process using the first exposure mask 18.

Here, the first exposure mask 18 may include a first line pattern 18a and a first pillar pattern including a vertical pillar region in a first direction on a quartz substrate (not shown), as shown in FIG. 2B (b). The first space pattern 18b between the one line pattern 18a is included.

At this time, the line width of the first line pattern 18a is preferably formed to have the target line width of the vertical filler.

Next, the region 16a exposed by the primary development process is developed to form the first photosensitive film pattern 16b.

2D and 2E, the first photosensitive film pattern 16b is exposed by a secondary exposure process using the second exposure mask 20.

Here, the second exposure mask 20 may include the second line pattern 20a and the second line pattern 20a including the vertical pillar region in the second direction on the quartz substrate (not shown), as shown in FIG. 2D (b). The second space pattern 20b between the two line patterns 20a is included.

In this case, the line width of the second line pattern 20a is preferably formed to have the target line width of the vertical filler.

The first and second directions preferably cross each other, more preferably perpendicular.

In addition, the first and second exposure process is preferably performed using any one selected from ArF equipment, immersion ArF equipment, KrF equipment.

Next, the second development process is performed to develop the exposed region 16c to form a second photoresist pattern (not shown).

Next, the anti-reflection film 14 and the hard mask film 12 are etched using the second photoresist pattern as an etch mask to form an anti-reflection film pattern (not shown) and a hard mask film pattern (not shown).

Next, the second photosensitive layer pattern 16d and the anti-reflective layer pattern are removed, and the semiconductor substrate 10 is etched using the hard mask layer pattern as an etch mask to form the vertical filler 22.

That is, the present invention can form the line width of the vertical filler 22 by the target line width by forming the vertical filler 22 by the exposure and development process over the second step to prevent the pattern collapse or the occurrence of bridges can do. In addition, it can be formed in a line / space form to form a pattern uniformly facilitates mass production of the product.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.

2A to 2E illustrate a method of manufacturing a semiconductor device according to the present invention.

Claims (5)

Forming a photoresist film on the semiconductor substrate; Exposing and developing the photoresist film with a first exposure mask including a line / space pattern in a first direction to form a first photoresist pattern; Exposing and developing the first photoresist pattern with a second exposure mask including a line / space pattern in a second direction to form a second photoresist pattern; And Forming a vertical filler using the second photoresist pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the first direction and the second direction are perpendicular to each other. The method of claim 1, wherein the exposure process using the first and second exposure masks is performed using any one selected from ArF equipment, immersion ArF equipment, and KrF equipment. . The method of claim 1, further comprising forming a hard mask film and an anti-reflection film on the semiconductor substrate. The method of claim 4, wherein the vertical pillar forming step Etching the anti-reflection film and the hard mask film by using the second photoresist pattern as an etch mask to form an anti-reflection film pattern and a hard mask film pattern; Removing the second photoresist pattern and the anti-reflection film pattern; And Etching the semiconductor substrate using the hard mask layer pattern as an etching mask Method of manufacturing a semiconductor device comprising a.
KR1020080061885A 2008-06-27 2008-06-27 Method for manufacturing semiconductor device KR20100001814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080061885A KR20100001814A (en) 2008-06-27 2008-06-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080061885A KR20100001814A (en) 2008-06-27 2008-06-27 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20100001814A true KR20100001814A (en) 2010-01-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8278223B2 (en) 2010-01-15 2012-10-02 Hynix Semiconductor Inc. Method for forming hole pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8278223B2 (en) 2010-01-15 2012-10-02 Hynix Semiconductor Inc. Method for forming hole pattern

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