KR20070058747A - Method for forming isolation film of semiconductor device - Google Patents

Method for forming isolation film of semiconductor device Download PDF

Info

Publication number
KR20070058747A
KR20070058747A KR1020050117395A KR20050117395A KR20070058747A KR 20070058747 A KR20070058747 A KR 20070058747A KR 1020050117395 A KR1020050117395 A KR 1020050117395A KR 20050117395 A KR20050117395 A KR 20050117395A KR 20070058747 A KR20070058747 A KR 20070058747A
Authority
KR
South Korea
Prior art keywords
forming
film
device isolation
region
trench
Prior art date
Application number
KR1020050117395A
Other languages
Korean (ko)
Inventor
김상민
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050117395A priority Critical patent/KR20070058747A/en
Publication of KR20070058747A publication Critical patent/KR20070058747A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)

Abstract

A method for forming an isolation layer in a semiconductor device is provided to improve a DOF(depth of focus) margin of the entire process for forming an isolation mask by forming a dummy pattern in a cell area while an isolation layer is formed in a peripheral area. A nitride layer(202) and a hard mask layer(204) are sequentially formed on a semiconductor substrate(200) divided into a cell area and a peripheral area. A photolithography process is performed by using a first isolation mask for forming a uniform pattern in the cell area so that the hard mask layer, the nitride layer and a part of the semiconductor substrate in a region of the cell area for forming the uniform pattern are etched to form a trench. A photolithography process is performed by using a second isolation mask for simultaneously forming a dummy pattern(208) in the cell area and an isolation layer in the peripheral area so that the hard mask layer, the nitride layer and a part of the semiconductor substrate in a region of the cell area for forming the dummy pattern are etched to form a trench. After a wall oxide layer is formed on the surface of the trench, an insulation layer is formed on the resultant structure to bury the trench.

Description

반도체 소자의 소자분리막 형성 방법{Method for forming Isolation Film of Semiconductor Device}Method for forming Isolation Film of Semiconductor Device

도 1 및 도 2는 종래 반도체 소자의 소자분리막 형성 공정을 나타낸 도면.1 and 2 are views illustrating a device isolation film forming process of a conventional semiconductor device.

도 3 및 도 4는 본 발명의 일실시예에 따른 반도체 소자의 소자분리막 형성 공정을 나타낸 도면.3 and 4 are views illustrating a device isolation film forming process of a semiconductor device according to an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

200 : 반도체 기판 202 : 질화막            200 semiconductor substrate 202 nitride film

204 : 하드마스크막 206 : 제 1 포토레지스트(PR)막            204: hard mask film 206: first photoresist (PR) film

206a : 제 2 포토레지스트막 208 : 더미 패턴(Dummy Pattern)            206a: second photoresist film 208: dummy pattern

본 발명은 반도체 소자의 소자분리막 형성 방법에 관한 것으로서, 특히 주변회로 영역의 소자분리막 형성공정과 동시에 셀 영역의 더미 패턴(Dummy Pattern)을 형성함으로써, 전체적인 소자분리 마스크 공정의 초점깊이(Depth Of Focus ; DOF) 마진(Margin)을 향상할 수 있는 반도체 소자의 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular, by forming a dummy pattern of a cell region at the same time as a device isolation film forming process of a peripheral circuit region, a depth of focus of an overall device isolation mask process (Depth Of Focus). ; DOF) A device isolation film forming method of a semiconductor device capable of improving the margin (Margin).

이하 첨부된 도면을 참조하여 종래 반도체 소자의 소자분리막 형성 공정을 간략하게 설명하기로 한다.Hereinafter, a device isolation film forming process of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1(a) 및 도 2(a)는 종래 반도체 소자의 소자분리막 형성 공정에 사용되는 제 1 소자분리 마스크(ISO Mask) 및 제 2 소자분리 마스크를 도시한 레이아웃(Layout)도 이고, 도 1(b) 및 도 2(b)는 종래 반도체 소자의 소자분리막 형성 공정을 설명하기 위한 반도체 소자의 단면도 이다.1 (a) and 2 (a) are layout views illustrating a first device isolation mask (ISO mask) and a second device isolation mask used in a device isolation film forming process of a conventional semiconductor device. 2B and 2B are cross-sectional views of a semiconductor device for explaining a device isolation film forming process of a conventional semiconductor device.

도 1(b) 및 도 2(b)를 참조하면, 셀 영역과 주변회로 영역으로 구분되어진 반도체기판(100) 상부에 질화막(102) 및 하드마스크막(104)을 형성하고, 제 1 포토레지스트(PR)막(106)을 도포한 후, 주변회로 영역은 차단한 채 셀 영역의 하드마스크막(104) 및 질화막(102)의 일부를 순차적으로 식각하여 소자분리막을 형성하기 위해 도 1(a)와 같은 제 1 소자분리 마스크로 사진 및 식각공정을 실시한다.Referring to FIGS. 1B and 2B, a nitride film 102 and a hard mask film 104 are formed on a semiconductor substrate 100 divided into a cell region and a peripheral circuit region, and a first photoresist is formed. After applying the (PR) film 106, the hard mask film 104 and the portion of the nitride film 102 of the cell region are sequentially etched while the peripheral circuit region is blocked to form an isolation layer. A photolithography and an etching process are performed using the first device isolation mask as in FIG.

사진 및 식각공정으로 셀 영역의 일부를 식각한 후, 제 1 포토레지스트막(106)을 제거하면, 라인 스페이스가 1:1 이 되는 균일 패턴 영역과 라인 스페이스가 균일하지 않게 되는 더미 패턴(108) 영역이 형성되게 된다.After the part of the cell region is etched by the photolithography and etching process, the first photoresist layer 106 is removed, and the uniform pattern region where the line space becomes 1: 1 and the dummy pattern 108 where the line space becomes uneven The area will be formed.

더미 패턴(108)은 반도체 디바이스에 기여하는 패턴을 아니나, 더미 패턴(108)을 잘 유지시켜 주어야만 균일 패턴이 그대로 유지되기 때문에 소자분리막 형성공정시, 더미 패턴을 손상시키지 않는 기술이 필요하다.The dummy pattern 108 is not a pattern that contributes to the semiconductor device. However, since the uniform pattern is maintained only when the dummy pattern 108 is well maintained, a technique that does not damage the dummy pattern is required in the device isolation film forming process.

즉, 종래에는 균일패턴과 더미패턴(108)을 포함한 셀 영역만의 트랜치 형성공정을 실시한 후, 주변회로 영역만의 트랜치 형성공정을 실시하였다.That is, in the related art, after the trench forming step of only the cell region including the uniform pattern and the dummy pattern 108 is performed, the trench forming step of only the peripheral circuit region is performed.

그러나, 도 1(a)와 같은 제 1 소자분리 마스크로 제 1 공정을 실시한 후, 전 체구조상부에 제 2 포토레지스트막(106a)을 형성하여 도 2(a)와 같은 제 2 소자분리 마스크로 제 2 공정을 실시하면, 사진식각공정 중 한방향으로 특정조명을 쬐어주는 노광공정의 특성상 균일 패턴이 아닌 더미 패턴(108)은 초점깊이(Depth Of Focus ; DOF) 마진(Margin)이 매우 취약해 지는 문제점이 있다.However, after the first process is performed with the first device isolation mask as shown in FIG. 1A, a second photoresist film 106a is formed over the entire structure to form a second device isolation mask as shown in FIG. When the second process is performed, the dummy pattern 108, which is not a uniform pattern, has a very weak margin of focus due to the characteristics of the exposure process that exposes specific light in one direction of the photolithography process. There is a problem losing.

실제로, 셀 영역의 균일 패턴 라인에서는 초점 0.2㎛ 까지 패턴이 형성되나, 셀 영역의 더미 패턴 라인의 경우에는 초점 0.1㎛ 에서 패턴의 마진이 떨어지기 시작하면서 초점 0.2㎛에서는 디포커스(Defocus) 되어 패턴이 형성되지 않는다.In practice, the pattern is formed up to 0.2 µm in focus in the uniform pattern line of the cell region, but in the case of dummy pattern lines in the cell region, the margin of the pattern begins to fall at the focus of 0.1 µm, and the pattern is defocused at 0.2 µm in focus. It is not formed.

본 발명의 목적은 주변회로 영역(Peri. Area)의 소자분리막 형성공정과 동시에 셀 영역(Cell Area)의 더미 패턴(Dummy Pattern)을 형성함으로써, 전체적인 소자분리 마스크 공정의 초점깊이(Depth Of Focus ; DOF) 마진(Margin)을 향상할 수 있는 반도체 소자의 소자분리막 형성 방법을 제공함에 있다.An object of the present invention is to form a dummy pattern of the cell area at the same time as the device isolation film forming process of the peripheral circuit area (Peri. Area), the depth of the overall device isolation mask process (Depth Of Focus; It is an object of the present invention to provide a method for forming a device isolation film of a semiconductor device capable of improving margins.

본 발명의 일 실시예에 따른 반도체 소자의 소자분리막 형성 방법은, 셀 영역과 주변회로 영역으로 구분되어진 반도체기판 상부에 질화막, 하드마스크막을 순차적으로 형성하는 단계; 상기 셀 영역의 균일 패턴을 형성하기 위한 제 1 소자분리 마스크로 사진 및 식각공정을 실시하여 상기 셀 영역의 균일 패턴이 형성될 영역의 하드마스크막, 질화막 및 반도체 기판의 일부를 식각하여 트랜치를 형성하는 단계; 상기 셀 영역의 더미 패턴과 주변회로 영역의 소자분리막을 동시에 형성하기 위한 제 2 소자분리 마스크로 사진 및 식각공정을 실시하여 상기 셀 영역의 더미 패턴이 형성될 영역과 주변회로 영역의 하드마스크막, 질화막 및 반도체 기판의 일부를 식각하여 트랜치를 형성하는 단계; 및 상기 트랜치가 매립되도록 전체구조상부에 절연막을 형성하는 단계를 포함한다.A method of forming a device isolation film of a semiconductor device according to an embodiment of the present invention includes: sequentially forming a nitride film and a hard mask film on a semiconductor substrate divided into a cell region and a peripheral circuit region; Photo-etching is performed with a first device isolation mask to form a uniform pattern of the cell region to form a trench by etching a hard mask film, a nitride film, and a portion of the semiconductor substrate in the region where the uniform pattern of the cell region is to be formed. Doing; Performing a photo-etching process with a second device isolation mask for simultaneously forming the dummy pattern of the cell region and the device isolation film of the peripheral circuit region, and a hard mask film of the region where the dummy pattern of the cell region is to be formed and the peripheral circuit region; Etching a portion of the nitride film and the semiconductor substrate to form a trench; And forming an insulating film on the entire structure to fill the trench.

상기 제 2 소자분리 마스크 형성시, 상기 더미 패턴 간의 간격을 조절할 수 있다.The gap between the dummy patterns may be adjusted when the second device isolation mask is formed.

상기 절연막 형성 전에 상기 트랜치 표면에 월(Wall) 산화막을 형성하는 단계를 더 포함한다.And forming a wall oxide film on the trench surface before forming the insulating film.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3(a) 및 도 4(a)는 본 발명의 반도체 소자의 소자분리막 형성 공정에 사용되는 제 1 소자분리 마스크(ISO Mask) 및 제 2 소자분리 마스크를 도시한 레이아웃(Layout)도 이고, 도 3(b) 및 도 4(b)는 본 발명의 일 실시예에 따른 반도체 소자의 소자분리막 형성 공정을 설명하기 위한 반도체 소자의 단면도 이다.3 (a) and 4 (a) are layout diagrams showing a first device isolation mask (ISO Mask) and a second device isolation mask used in the device isolation film forming process of the semiconductor device of the present invention. 3 (b) and 4 (b) are cross-sectional views of a semiconductor device for explaining a process of forming a device isolation film of a semiconductor device according to an embodiment of the present invention.

도 3(b)를 참조하면, 셀 영역과 주변회로 영역으로 구분되어진 반도체기판(200) 상부에 질화막(202) 및 하드마스크막(204)을 순차적으로 형성한다.Referring to FIG. 3B, a nitride film 202 and a hard mask film 204 are sequentially formed on the semiconductor substrate 200 divided into a cell region and a peripheral circuit region.

여기서, 상기 반도체기판(200)과 질화막(202) 사이에는 산화막을 포함한 다른 계면이 형성될 수 있으나, 본 발명의 취지상 생략한다.In this case, another interface including an oxide film may be formed between the semiconductor substrate 200 and the nitride film 202, but is omitted for the purpose of the present invention.

하드마스크막(204) 상부에 제 1 포토레지스트(PR)막(206)을 도포한 후, 셀 영역 중 균일 패턴 형성 영역의 하드마스크막(204), 질화막(202) 및 반도체기판(200)의 일부를 식각하여 트랜치를 형성하기 위해 도 3(a)와 같은 제 1 소자분리 마스크로 사진 및 식각공정을 실시한다.After the first photoresist (PR) film 206 is applied on the hard mask film 204, the hard mask film 204, the nitride film 202, and the semiconductor substrate 200 of the uniform pattern formation region of the cell region are formed. In order to form a trench by etching a portion, a photolithography and an etching process are performed using a first device isolation mask as shown in FIG.

제 1 소자분리 마스크로 사진식각공정을 실시하면, 라인 스페이스(Line Space)가 1:1 이 되는 균일 패턴만이 형성된다.When the photolithography process is performed using the first device isolation mask, only a uniform pattern having a line space of 1: 1 is formed.

다음, 제 1 포토레지스트막(206)을 제거한 후, 클리닝 공정을 실시한다.Next, after the first photoresist film 206 is removed, a cleaning process is performed.

도 4(b)를 참조하면, 전체구조상부에 제 2 포토레지스트막(206a)을 도포한 후, 셀 영역의 균일 패턴 영역은 차단한 채, 주변회로 영역 및 셀 영역의 더미 패턴(208) 영역의 하드마스크막(204), 질화막(202) 및 반도체기판(200)의 일부를 식각하여 트랜치를 형성하기 위해 도 4(a)와 같은 제 2 소자분리 마스크로 사진 및 식각공정을 실시한다.Referring to FIG. 4B, after applying the second photoresist film 206a over the entire structure, the peripheral pattern region and the dummy pattern region 208 of the cell region are blocked while the uniform pattern region of the cell region is blocked. A photomask and an etching process are performed using a second device isolation mask as shown in FIG. 4A to form a trench by etching portions of the hard mask film 204, the nitride film 202, and the semiconductor substrate 200.

여기서, 상기 제 2 소자분리 마스크 형성시, 상기 더미 패턴(208) 간의 간격을 조절하여 초점(Focus)을 최적화 시킨다.Here, when forming the second device isolation mask, the focus is optimized by adjusting the gap between the dummy patterns 208.

제 2 소자분리 마스크로 사진식각공정을 실시한 후, 제 2 포토레지스트막(206a)을 제거하면, 주변회로 영역(Peri. Area)의 소자분리막 형성공정과 동시에 셀 영역(Cell Area)의 더미 패턴(Dummy Pattern)(208)이 형성되어, 전체적인 소자분리 마스크 공정의 초점깊이(Depth Of Focus ; DOF) 마진(Margin)을 향상할 수 있다.After the photolithography process is performed using the second device isolation mask and the second photoresist film 206a is removed, the dummy pattern of the cell area may be formed at the same time as the device isolation film forming process of the peripheral circuit area Peri. A dummy pattern 208 may be formed to improve the margin of focus of the entire device isolation mask process.

다음, 트랜치 표면에 월(Wall) 산화막을 형성한 후, 트랜치가 매립되도록 절연막을 형성하여 소자분리막을 형성한다.Next, after forming a wall oxide film on the trench surface, an insulating film is formed to fill the trench to form an isolation layer.

본 발명은 도면에 도시된 실시 예를 참고로 설명되었으나, 이는 예시적인 것에 불과하며, 본 기술분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시 예가 가능하다는 점을 이해할 것이다.Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible.

따라서, 본 발명의 진정한 기술적 보호 범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

본 발명은 주변회로 영역(Peri. Area)의 소자분리막 형성공정과 동시에 셀 영역(Cell Area)의 더미 패턴(Dummy Pattern)을 형성함으로써, 전체적인 소자분리 마스크 공정의 초점깊이(Depth Of Focus ; DOF) 마진(Margin)을 향상할 수 있다.The present invention forms a dummy pattern of the cell area at the same time as the device isolation film forming process of the peripheral circuit area (Peri. Area), thereby increasing the depth of focus of the entire device isolation mask process (Depth Of Focus; DOF). You can improve your margins.

Claims (3)

셀 영역과 주변회로 영역으로 구분되어진 반도체기판 상부에 질화막, 하드마스크막을 순차적으로 형성하는 단계;Sequentially forming a nitride film and a hard mask film on the semiconductor substrate divided into a cell region and a peripheral circuit region; 상기 셀 영역의 균일 패턴을 형성하기 위한 제 1 소자분리 마스크로 사진 및 식각공정을 실시하여 상기 셀 영역의 균일 패턴이 형성될 영역의 하드마스크막, 질화막 및 반도체 기판의 일부를 식각하여 트랜치를 형성하는 단계;Photo-etching is performed with a first device isolation mask to form a uniform pattern of the cell region to form a trench by etching a hard mask film, a nitride film, and a portion of the semiconductor substrate in the region where the uniform pattern of the cell region is to be formed. Doing; 상기 셀 영역의 더미 패턴과 주변회로 영역의 소자분리막을 동시에 형성하기 위한 제 2 소자분리 마스크로 사진 및 식각공정을 실시하여 상기 셀 영역의 더미 패턴이 형성될 영역과 주변회로 영역의 하드마스크막, 질화막 및 반도체 기판의 일부를 식각하여 트랜치를 형성하는 단계; 및Performing a photo-etching process with a second device isolation mask for simultaneously forming the dummy pattern of the cell region and the device isolation film of the peripheral circuit region, and a hard mask film of the region where the dummy pattern of the cell region is to be formed and the peripheral circuit region; Etching a portion of the nitride film and the semiconductor substrate to form a trench; And 상기 트랜치가 매립되도록 전체구조상부에 절연막을 형성하는 단계;Forming an insulating film on an entire structure to fill the trench; 를 포함하는 반도체 소자의 소자분리막 형성 방법.Device isolation film forming method of a semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 제 2 소자분리 마스크 형성시, 상기 더미 패턴 간의 간격을 조절할 수 있는 반도체 소자의 소자분리막 형성 방법.The method of forming a device isolation film of a semiconductor device, wherein the gap between the dummy patterns may be adjusted when the second device isolation mask is formed. 제 1항에 있어서,The method of claim 1, 상기 절연막 형성 전에 상기 트랜치 표면에 월(Wall) 산화막을 형성하는 단 계를 더 포함하는 반도체 소자의 소자분리막 형성 방법.And forming a wall oxide film on the surface of the trench before forming the insulating film.
KR1020050117395A 2005-12-05 2005-12-05 Method for forming isolation film of semiconductor device KR20070058747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050117395A KR20070058747A (en) 2005-12-05 2005-12-05 Method for forming isolation film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050117395A KR20070058747A (en) 2005-12-05 2005-12-05 Method for forming isolation film of semiconductor device

Publications (1)

Publication Number Publication Date
KR20070058747A true KR20070058747A (en) 2007-06-11

Family

ID=38355342

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050117395A KR20070058747A (en) 2005-12-05 2005-12-05 Method for forming isolation film of semiconductor device

Country Status (1)

Country Link
KR (1) KR20070058747A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100983509B1 (en) * 2008-07-24 2010-09-27 주식회사 하이닉스반도체 Method for fabricating semiconductor device
CN111627808A (en) * 2019-02-28 2020-09-04 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100983509B1 (en) * 2008-07-24 2010-09-27 주식회사 하이닉스반도체 Method for fabricating semiconductor device
CN111627808A (en) * 2019-02-28 2020-09-04 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof
CN111627808B (en) * 2019-02-28 2023-10-20 中芯国际集成电路制造(北京)有限公司 Semiconductor structure and forming method thereof

Similar Documents

Publication Publication Date Title
JP2007013074A (en) Method for manufacturing semiconductor device
KR100822581B1 (en) Method of manufacturing a flash memory device
JP2007149768A (en) Method of manufacturing semiconductor device
JP2007027681A (en) Method for manufacturing semiconductor device
KR20070058747A (en) Method for forming isolation film of semiconductor device
JP2008091824A (en) Manufacturing method for semiconductor device
KR100807074B1 (en) Method for fabrication a semiconductor device
JP2007180475A (en) Method of manufacturing semiconductor device utilizing amorphous carbon
KR20060076498A (en) Method of forming an isolation layer in a semiconductor device
KR100796515B1 (en) Method for forming semiconductor device
KR20050007984A (en) Method for forming a trench in semiconductor device
KR100489350B1 (en) Method for fabricating gate electrode of semiconductor device
KR100905181B1 (en) Method for manufacturing semiconductor device
KR20030092569A (en) Method for manufacturing a semiconductor device
KR100835420B1 (en) Method for fabricating semiconductor device
KR20070069692A (en) Method for forming fine pattern of semiconductor device
KR20080022973A (en) Method for manufacturing semiconductor device
KR100887064B1 (en) Overlay vernier and method for forming the same
KR100905193B1 (en) Method for manufacturing semiconductor device
KR100905164B1 (en) Method for manufacturing of semiconductor device
JP2005033224A (en) Method of manufacturing thin film semiconductor device and method of forming resist pattern thereof
KR20060133796A (en) Formation method of sti
KR20070069691A (en) Method for manufacturing semiconductor device
KR20100001814A (en) Method for manufacturing semiconductor device
KR20070023170A (en) Method for forming trench of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination