JP2005033224A - Method of manufacturing thin film semiconductor device and method of forming resist pattern thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the simplification of a process and to improve the accuracy of alignment by avoiding pitch aligning caused by a plurality of masks. <P>SOLUTION: First, etching is performed on a ground silicon layer 13 formed on the surface of a glass substrate 11 with a penetration pattern 2 forming the thinnest film as an opening pattern to form an alignment pattern 4, by using a resist layer 14a having a plurality of different film thickness areas corresponding to a plurality of different patterns formed with half tone masks each having a half tone area in a photo mask. Next, the ground silicon layer 13a is exposed in a main pattern area 5 by removing the entire surface of the resist layer 14a by means of ashing, and ions are injected in the entire surface of the resist 14a. Consequently, only the main pattern area 5 in the ground silicon layer 13a is doped. A process following the etching is not limited to doping. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a thin film semiconductor device and a method for forming a resist pattern thereof, and more particularly, to a method for manufacturing a thin film semiconductor device capable of realizing simplification of the process and improving alignment accuracy and a method for forming a resist pattern thereof.

  Conventionally, in this type of thin film semiconductor device manufacturing method and its resist pattern forming method, it is not possible to align the next step with a step in which a pattern does not remain on the substrate after removal of the photoresist, such as ion doping. Therefore, in this case, the alignment pattern formed in another process is commonly used in the next process.

  For example, as shown in FIG. 6A, when an exposure mask 120 having an alignment pattern region 122 and an ion doping region 123 as a light transmission region with respect to the light shielding region 121 is used on the surface of the resist layer 14. Is assumed.

  As a result of exposure and development processing in this state, as shown in FIG. 6B, the resist layer 14 is removed in the portions exposed in the alignment pattern region 122 and the ion doping region 123 other than the light shielding region 121, and the resist layer 14 is removed. Layer 14 (0) is generated. That is, in the resist layer 14 (0), the alignment pattern portion 2 and the ion doping portion 3 that form spaces up to the base silicon layer 13 corresponding to the alignment pattern region 122 and the ion doping region 123, respectively.

  When ion doping is performed using the resist layer 14 (0) in this state as a mask, not only the ion doping portion 3 but also the underlying silicon layer 13 of the alignment pattern portion 2 is doped, so that the exposed alignment is performed. The pattern portion is also made of the same material as the ion doping portion. Therefore, when the resist layer 14 is removed for the next step, both cannot be optically identified, and the alignment mark cannot be identified.

  Therefore, for example, as shown in FIG. 6C, an etching process using an etching mask 220 having only the alignment pattern region 222 separately prepared without using the resist layer 14 (0) having a plurality of patterns as a mask. There is a need to do. In this way, the alignment pattern 4 is formed on the underlying silicon layer 13 by etching. As a result, as shown in FIG. 6D, the alignment pattern 4 can be distinguished from other regions. Therefore, in the next step, the alignment layer 4 is used for alignment using the resist layer 14 (0) as a mask. Can do.

  Further, in another step of performing ion doping first, a mask is prepared only for forming the alignment mark, and a step of forming a photoresist layer using this mask is added, so that the same state as in FIG. Can be formed. That is, since the process moves to the next ion doping process after the alignment mark is formed, a method of forming a photoresist layer in each of the two processes is employed.

  In the conventional thin film semiconductor device manufacturing method and the resist pattern forming method described above, when there is a processing step such as ion doping at the beginning, an etching mask is prepared to generate an alignment mark, or the alignment mark is formed in the next step. Not only is an extra process required, such as preparing a mask for alignment with the main process, but also indirect alignment with the next process, resulting in poor alignment accuracy. There was a point.

  It is an object of the present invention to provide a method for manufacturing a thin film semiconductor device and a method for forming a resist pattern thereof that can solve such problems, realize process simplification and improve alignment accuracy.

  In the method of manufacturing a thin film semiconductor device according to the present invention, as a resist pattern to be used, a plurality of different film thickness regions corresponding to a plurality of different patterns are generated in the resist layer using a mask having a halftone or gray tone region. It is characterized by that. For example, the mask has a transmission mask region, a halftone exposure region, and a light-shielding mask region, and each region forms a plurality of layer thickness patterns on the resist layer. That is, an alignment mark can be formed on the underlying silicon layer by first etching the region corresponding to the alignment pattern in the resist pattern generated in this way.

  A specific method for manufacturing a thin film semiconductor device includes a step of forming a base silicon layer on a substrate surface and a step of forming a resist pattern having a plurality of different film thickness regions on the surface of the base silicon layer. ing. Next, if the underlying layer is not exposed, a step of removing the thinnest resist film thickness region, which is the alignment pattern portion, by ashing so as to expose the underlying layer, and etching using the resist pattern generated thereby as a mask And forming an alignment pattern on the underlying silicon layer. Further, the method includes a step of removing the thinnest thin film region of the resist by ashing so as to expose the base of the next pattern portion, and a step of forming other than the alignment pattern using the generated resist pattern as a mask. . In this way, the thinnest portion of the resist thin film is removed stepwise by ashing from a resist pattern having a plurality of different film thickness regions.

  Processes other than forming the alignment pattern on the underlying silicon layer can be processed by etching or processes other than etching using a resist pattern other than the alignment pattern as a mask. Further, one of processes other than etching is a process of ion implantation using a resist pattern as a mask.

  In addition, an insulating transparent substrate can be used as a substrate for a liquid crystal display, and an alignment pattern can be formed as an opening pattern as a resist pattern formed on the surface of the underlying silicon layer. This process eliminates the ashing process for generating the alignment pattern.

  By such a method, a resist pattern corresponding to the alignment pattern can be formed into a pattern having the thinnest film thickness or an opening pattern by exposure and development. Therefore, if necessary, the alignment pattern can be formed into an opening pattern by first ashing, so that the alignment pattern can be etched. As a result, the resist pattern portion having the next thinnest film thickness is removed by the next ashing, for example, ion doping is possible. That is, only one photomask may be used to form a resist pattern for the two steps of alignment mark formation and ion doping.

  As described above, according to the present invention, a thin film semiconductor device in which an alignment pattern is formed by etching using the thinnest resist layer portion generated using a halftone mask having a halftone region as a photomask. A manufacturing method is obtained. By this method, a plurality of photoresist production steps can be combined into one, so that the process can be simplified and alignment by a plurality of photoresists can be avoided and alignment accuracy can be improved.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a manufacturing process diagram by a cross-sectional view of a thin film semiconductor device as one embodiment of the present invention. 2 is a view showing a detailed form of the manufacturing process in FIG. 1C, and FIG. 3 is a view showing a form of the substrate plane of the thin film semiconductor device to which the present invention is applied. As shown in FIG. 3, an alignment pattern 31 is provided on the upper surface of the substrate 30 for positioning the upper surface of the substrate 30 with one corner of the transistor formation region 32 interposed therebetween.

  In the method of manufacturing the thin film semiconductor device shown in FIG. 1, first, as shown in FIG. 1A, for example, an insulating film 12 made of silicon dioxide, for example, is formed on the surface of a transparent insulating glass substrate 11 as a base protective film. As approximately 3000 angstroms. Next, as shown in FIG. 1B, amorphous silicon (hereinafter referred to as a-Si) of about 600 angstroms is formed on the surface of the insulating film 12 by LP-CVD or PE-CVD as the underlying silicon layer 13. It is formed. The a-Si formed by PE-CVD is dehydrogenated to 1% or less after being formed as the underlying silicon layer 13.

  Here, with reference to FIG. 2, the production | generation method of the resist layer 14a shown by FIG.1 (c) is demonstrated.

  First, as shown in FIG. 2A, a resist layer 14 of approximately 2 μm is applied on the upper surface of the underlying silicon layer 13 shown in FIG.

  Next, as shown in FIG. 2B, the halftone mask 20 is used for exposure processing. That is, the halftone mask 20 has a light shielding mask portion 21 where the thickness of the resist layer 14 is maintained, a transmission mask portion 22 where the resist layer 14 is not left, and a predetermined thickness such as an intermediate thickness. And a semi-transmissive (hereinafter halftone) mask portion 23 in which the layer 14 is left.

  In the example shown in FIG. 2, the transmission mask portion 22 is used for forming the alignment pattern 31 in FIG. The halftone mask portion 23 is used for ion doping of the transistor region 32 in FIG.

  After the exposure and development, as shown in FIG. 2 (c), the resist layer 14 in an excessive exposure portion is removed, so that a resist layer 14a having a three-layer resist layer thickness is formed. . That is, the light-shielding pattern portion 1 that leaves the thickness of the resist layer 14, the transmission pattern portion 2 that does not leave the resist layer 14, and the halftone pattern portion 3 that leaves the resist layer 14 in a predetermined thickness.

  The thickness of the resist layer 14a of the halftone pattern portion 3 by halftone exposure is preferably 3000 angstroms or more in the case of dry etching and 1000 angstroms or more in the case of wet etching, although it varies depending on the process conditions.

  Returning again to FIG. FIG.1 (c) is the same form as FIG.2 (c) produced | generated by the process mentioned above.

  Subsequently, as shown in FIG. 1D, the underlying silicon layer 13 exposed only in the transmission pattern portion 2 of the resist layer 14a is dry-etched using the resist layer 14a as a mask. As a result, the base silicon layer 13 is formed on the base silicon layer 13 a having the alignment pattern 4.

  Next, as shown in FIG. 1E, the underlying silicon layer 13a is formed in the main pattern region 5 in which the resist layer 14a of the halftone pattern portion 3 is removed by reducing the film thickness of the resist layer 14a as a whole by ashing. For example, ion implantation or ion doping of boron for controlling the threshold value of an Nch transistor is performed on the exposed portion. Finally, by removing the resist 14b, the formation of the alignment mark 4 for the next process and the main pattern area 5 serving as a boron selective introduction area can be performed in one mask process.

  In the above description, dry etching and channel region formation of an Nch transistor have been described. Needless to say, wet etching can be applied instead of dry etching, but a channel formation region of a Pch transistor instead of an Nch transistor. The present invention can also be applied to the case where selective impurity introduction is performed. Further, the present invention is applicable not only to transistors but also to selective impurity introduction processes for all devices that require impurity introduction. Further, the halftone mask portion is formed in the halftone pattern portion and can be applied not only to the doping process but also to the second etching process. Further, although the underlying silicon layer is a-Si (amorphous silicon), it can also be applied to polycrystalline silicon.

  Next, simultaneous formation of island regions other than pattern formation will be described with reference to FIG.

  In the above-described embodiment, the present invention is applied to the alignment pattern formation process for the next process and the selective impurity introduction process. However, the alignment pattern formation is performed not only for the simple pattern formation but also for example, simultaneously with the formation of the island region 6. You can also. That is, as shown in the drawing, in addition to the alignment pattern 4, a pattern for the island region 8 can be formed at the same time. Therefore, one photoresist is sufficient for each of the three formation purposes for the alignment mark, the island, and the doping. Is possible.

  Next, an embodiment different from FIG. 1 will be described with reference to FIG.

  On the glass substrate 11 shown in the figure, approximately 1000 angstroms of silicon dioxide is formed as an oxide film 15 on the surface of the underlying silicon layer 13 shown in FIG. 1B by LP-CVD or PE-CVD. By forming the oxide film 15 on the base silicon layer 13, it is possible to prevent the base silicon layer 13 from being contaminated from the resist layer 14.

  In the above description, the resist layer is formed in three layers, but it is also possible to form four or more layers by forming the halftone region of the photomask in a plurality of stages.

It is a figure which shows a manufacturing process by sectional drawing of one Embodiment by this invention with a thin film semiconductor device. It is a figure which shows one detailed form of the manufacturing process in FIG.1 (c). It is a figure which shows one form of the board | substrate plane of the thin film semiconductor device to which this Embodiment is applied. FIG. 2 is a diagram showing an embodiment for simultaneous formation of island regions instead of pattern formation, different from FIG. 1. It is a figure which shows one form for the contamination prevention with respect to a base silicone layer separately from FIG. It is a figure which shows a manufacturing process with sectional drawing of a thin film semiconductor device of an example of the past.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light-shielding pattern part 2 Transmission pattern part 3 Halftone pattern part 4, 31 Alignment pattern 5 Main pattern area | region 6 Island area | region 11 Glass substrate 12 Insulating film 13 Underlayer silicon layer 14 Resist layer 20 Halftone mask 21 Light-shielding mask part 22 Transmission mask part 23 Translucent mask part (halftone mask part)
30 Substrate 32 Transistor formation region

Claims (8)

  Forming a base silicon layer on the substrate surface, forming a plurality of different film thickness regions corresponding to different patterns on the surface of the base silicon layer as resist patterns, and exposing the base At least one step of removing the thinnest thickness region of the resist pattern by ashing, forming an alignment pattern in the underlying silicon layer by etching a first opening pattern using the resist pattern as a mask, and And a step of forming other than the alignment pattern using a resist pattern regenerated by ashing as a mask.   2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the step other than forming an alignment pattern on the underlying silicon layer is a step of processing other than etching using the resist pattern as a mask.   2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the process other than forming an alignment pattern on the underlying silicon layer is a process of ion implantation using the resist pattern as a mask.   2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the process other than forming the alignment pattern on the underlying silicon layer is a process of etching using the resist pattern as a mask.   5. The method for manufacturing a thin film semiconductor device according to claim 1, wherein an insulating transparent substrate is used as the substrate.   5. The method of manufacturing a thin film semiconductor device according to claim 1, wherein an alignment pattern is formed as an opening pattern as the resist pattern formed on the surface of the base silicon layer.   A method for forming a resist pattern on the surface of a base silicon layer formed on a substrate surface, the step of applying a photoresist to form a resist layer, and a photomask for patterning the resist layer And forming the alignment pattern portion, the main pattern portion for the next process following alignment pattern formation, and the transparent mask region, the halftone exposure region, and the light shielding mask region as portions other than these, and the formed resist Forming a plurality of film thickness regions by exposing the layer using the photomask and developing the layer. 8. The resist pattern forming method according to claim 7, wherein the film thickness region generated by the transmission mask region is formed in an opening pattern.

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