JP2007005700A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of suppressing the propagation of a potential fluctuation as a noise between wells, and being inexpensively manufactured. <P>SOLUTION: The method for manufacturing the semiconductor device includes a process for forming an n-type deep well 1e by injecting n-type impurity ion with a first mask film formed on a p-type semiconductor substrate 1 as a mask; a process for forming a p-type well 1b positioned on the deep well 1e by introducing a p-type impurity to the semiconductor substrate 1 with the first mask film as the mask; a process for removing the first mask film; and a process for forming an n-type well 1d surrounding the circumference of the p-type well 1b by forming a second mask film on the semiconductor substrate 1, so as to introduce an n-type impurity with the second mask film as the mask. A second opening pattern is positioned in the whole edge periphery of a region, where an element is formed in the p-type well 1b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device and a semiconductor device that can suppress propagation of potential fluctuations as noise between wells and have low manufacturing costs.

  Each drawing in FIG. 8 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. This method is a method of forming an N-type well and a P-type well on a P-type silicon substrate 101, respectively. The silicon substrate 101 is provided with a digital area 110 where a digital circuit (for example, a logic circuit) is formed and an analog area 111 where an analog circuit is formed.

  First, as shown in FIG. 8A, a photoresist film 121 is applied on the silicon substrate 101. Next, the photoresist film 121 is exposed using a first glass mask (not shown) and then developed. As a result, a first opening pattern is formed in the photoresist film 121. Next, N-type impurity ions are implanted into the silicon substrate 101 with high energy using the photoresist film 121 as a mask. As a result, a deep N-type well 101e is formed in the silicon substrate 101 located in the analog region 111.

  Thereafter, as shown in FIG. 8B, the photoresist film 121 is removed. Next, a photoresist film 122 is applied on the silicon substrate 101. Next, the photoresist film 122 is exposed using a second glass mask (not shown) and then developed. As a result, a second opening pattern is formed in the photoresist film 122. Next, using the photoresist film 122 as a mask, N-type impurity ions are implanted into the silicon substrate 101 with low energy. As a result, an N-type well 101 c is formed in the silicon substrate 101 located in the digital region 110, and an N-type well 101 d is formed in the silicon substrate 101 located in the analog region 111. The N-type well 101d is located on a part of the deep N-type well 101e. Note that an N-type well 101 f is also formed at the edge of the analog region 111. For this reason, the bottom of the analog region 111 is covered with the deep N-type well 101e, and the side surfaces are surrounded by the N-type wells 101d and 101f.

  Thereafter, as shown in FIG. 8C, the photoresist film 122 is removed. Next, a photoresist film 123 is applied on the silicon substrate 101. Next, the photoresist film 122 is exposed using a third glass mask (not shown) and then developed. As a result, a third opening pattern is formed in the photoresist film 123. Next, P-type impurity ions are implanted into the silicon substrate 101 using the photoresist film 123 as a mask. As a result, a P-type well 101a is formed in the silicon substrate 101 located in the digital region 110, and a P-type well 101b is formed in the silicon substrate 101 located in the analog region 111.

  Thereafter, the photoresist film 123 is removed, and an analog circuit and a digital circuit are formed. When the digital circuit operates, potential fluctuation occurs in the P-type well 101a and the N-type well 101c. Since the silicon substrate 101 is P-type, the potential variation of the P-type well 101a propagates as noise to the analog region 111 through the silicon substrate 101, and varies the potential of the P-type well 101b located in the analog region 111. there is a possibility. When the potential of the P-type well 101b varies, the characteristics of the analog circuit are affected.

  However, in the analog region 111, the bottom and the periphery thereof are covered with the deep N-type well 101e, and the side surfaces are surrounded by the N-type wells 101d and 101f. For this reason, the noise is blocked by the deep N-type well 101e and the N-type wells 101d and 101f, and the potential of the P-type well 101b is suppressed from being affected by the noise.

  Although the analog circuit and the digital circuit operate at different potentials, since the deep N-type well 101e is formed only in the analog region 111, the N-type well 101c located in the digital region 110 and the N-well located in the analog region 111 The type well 101d is prevented from being short-circuited through the deep N type well 101e.

  In the prior art described above, it is necessary to form the resist film and pattern it three times. Moreover, since each pattern is different, three glass masks were required. In order to reduce the manufacturing cost of the semiconductor device, it is effective to reduce the number of times the resist film is patterned and reduce the number of glass masks.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to suppress the propagation of potential fluctuation as noise between wells, reduce the number of times of resist film patterning, and reduce the glass mask. It is an object to provide a method of manufacturing a semiconductor device and a semiconductor device capable of reducing the number of the semiconductor devices.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first mask film having a first opening pattern on a first conductivity type semiconductor substrate,
Forming a second conductivity type deep well in the semiconductor substrate by implanting second conductivity type impurity ions into the semiconductor substrate using the first mask film as a mask;
Forming a first conductivity type well located on the deep well in the semiconductor substrate by introducing a first conductivity type impurity into the semiconductor substrate using the first mask film as a mask;
Removing the first mask film;
Forming a second mask film having a second opening pattern on the semiconductor substrate;
Forming a second conductivity type well in the semiconductor substrate by introducing a second conductivity type impurity into the semiconductor substrate using the second mask film as a mask;
Removing the second mask film;
Comprising
The second opening pattern is located at least around the entire edge of the first conductivity type well,
In the step of forming the second conductivity type well, a second conductivity type impurity is introduced to the entire periphery of the edge of the first conductivity type well, and the entire periphery of the edge has a higher resistance than the semiconductor substrate.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a first mask film having a first opening pattern on a semiconductor substrate of a first conductivity type,
Forming a second conductivity type deep well in the semiconductor substrate by implanting second conductivity type impurity ions into the semiconductor substrate using the first mask film as a mask;
Forming a first conductivity type well located on the deep well in the semiconductor substrate by introducing a first conductivity type impurity into the semiconductor substrate using the first mask film as a mask;
Removing the first mask film;
Forming a second mask film having a second opening pattern on the semiconductor substrate;
Forming a second conductivity type well in the semiconductor substrate by introducing a second conductivity type impurity into the semiconductor substrate using the second mask film as a mask;
Removing the second mask film;
Comprising
The second opening pattern is located at least around the entire periphery of the region where the element is formed on the first conductivity type well,
In the step of forming the second conductivity type well, a second conductivity type impurity is introduced to the entire periphery of the region where the element is formed in the first conductivity type well, and the entire periphery of the well is connected to the semiconductor substrate. Compared to high resistance.

  According to these semiconductor device manufacturing methods, the second conductivity type deep well is formed at the bottom of the first conductivity type well and the periphery thereof. Further, the entire circumference of the edge of the first conductivity type well or the entire circumference of the edge of the region of the first conductivity type well where the element is formed is increased in resistance. For this reason, even when noise originating from other wells propagates through the semiconductor substrate of the first conductivity type, the noise is blocked by the deep well and the high resistance portion. Therefore, it is possible to prevent the potential fluctuation from propagating as noise between the wells.

  Further, two mask films (for example, photoresist films) are used. Therefore, the number of mask films is reduced as compared with the prior art, and the number of manufacturing steps and the number of glass masks for forming the mask film are reduced. In addition, the number of mask film formations is reduced. Therefore, the manufacturing cost of the semiconductor device can be reduced.

In the step of forming the second conductivity type well, it is preferable that the edge having the increased resistance is of the second conductivity type.
The first conductivity type is, for example, P type, and the second conductivity type is, for example, N type.

  The first conductivity type well may be located in an analog region where an analog circuit is formed. In this case, the semiconductor substrate includes the analog region and a digital region where a digital circuit is formed. In the step of forming the first conductivity type well, the semiconductor substrate located in the digital region also has the first conductivity type. Wells may be formed. Even if noise propagates from the first conductivity type well located in the digital region, the above-described action suppresses this noise from propagating to the first conductivity type well located in the analog region.

A semiconductor device according to the present invention includes a first conductivity type well formed in a first conductivity type semiconductor substrate,
A high resistance region formed on the semiconductor substrate and surrounding a side surface of the first conductivity type well and having a higher resistance than the semiconductor substrate;
A second conductivity type deep well located under the first conductivity type well and the high resistance region;
It comprises.

Another semiconductor device according to the present invention includes a first conductivity type well formed in a first conductivity type semiconductor substrate,
A high resistance region formed on the semiconductor substrate and surrounding a side surface of a region of the first conductivity type well where a semiconductor element is formed;
A second conductivity type deep well located under the first conductivity type well and the high resistance region;
It comprises.

  A first conductivity type impurity and a second conductivity type impurity may be introduced into the high resistance region, respectively. The high resistance region is preferably of a second conductivity type. The width of the high resistance region is preferably 2 μm or more.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A, FIG. 2, FIG. 3A, FIG. 4A, FIG. 5 and FIG. 6A illustrate a method of manufacturing a semiconductor device according to the first embodiment of the present invention. It is sectional drawing for this, and has shown the part corresponded to the AA cross section of FIG.1 (B), FIG.3 (B), and FIG.4 (B). FIG. 1B and FIG. 3B are plan views for explaining the exposure pattern of the glass mask used in the present embodiment. FIG. 4B is a plan view of the semiconductor device in the state of FIG. FIGS. 6B and 6C are an AA cross-sectional view and a BB cross-sectional view of FIG. 6A, respectively.

  In this method, an N-type well and a P-type well are formed on a P-type silicon substrate 1. The silicon substrate 1 is provided with a digital area 10 where a digital circuit (for example, a logic circuit) is formed and an analog area 11 where an analog circuit is formed.

  First, as shown in FIG. 1A, a positive photoresist film 50 is applied on the silicon substrate 1. Next, the photoresist film 50 is exposed using a glass mask 60.

  FIG. 1B is a plan view for explaining a light shielding pattern of the glass mask 60. The light shielding film of the glass mask 60 has an opening pattern 60 a located above the analog region 11 and a plurality of opening patterns 60 b located above the digital region 10. The shape of the opening pattern 60a is a shape obtained by removing the light shielding film located in the analog region 11 except for the region where the N-type well is formed and the periphery thereof. Each of the plurality of opening patterns 60b has a slit shape and is disposed substantially parallel to each other.

  Next, as shown in FIG. 2, the photoresist film 50 is developed. Thereby, an opening pattern corresponding to the opening pattern of the glass mask 60 is formed in the photoresist film 50. Next, N-type impurity ions are implanted into the silicon substrate 1 with high energy using the photoresist film 50 as a mask. As a result, a deep N-type well 1e is formed in the silicon substrate 1. The deep N-type well 1e is formed in both the digital region 10 and the analog region 11.

  Next, using the photoresist film 50 as a mask, P-type impurity ions are implanted into the silicon substrate 1 with low energy. As a result, a P-type well 1 a is formed in the silicon substrate 1 located in the digital region 10, and a P-type well 1 b is formed in the silicon substrate 1 located in the analog region 11. Each of the P-type wells 1a and 1b is located on the deep N-type well 1e. In the digital region 10, a plurality of combinations of the P-type well 1a and the deep N-type well 1e are formed in parallel with each other in a slit shape. In the analog region 11, the P-type well 1b and the deep N-type well 1e are formed except for the region where the N-type well is formed and its periphery.

  Thereafter, as shown in FIG. 3A, the photoresist film 50 is removed. Next, a positive type photoresist film 51 is applied on the silicon substrate 1, and the photoresist film 51 is exposed using a glass mask 61.

  FIG. 3B is a plan view for explaining a light shielding pattern of the glass mask 61. The light shielding film of the glass mask 61 has opening patterns 61 a and 61 c located in the analog region 11 and a plurality of slit-like opening patterns 61 b located in the digital region 10.

As shown in FIGS. 3A and 3B, the opening pattern 61a is formed above the region where the N-type well is formed and at a position overlapping with the periphery thereof, and the entire periphery of the opening pattern 61a is the same as the P-type well 1b. overlapping. The width of the portion overlapping the P-type well 1b is, for example, not less than 2 μm and not more than 3 μm. The opening pattern 61c is formed at a position overlapping the edge of the region where the semiconductor element is formed in the P-type well 1b. The width of the opening pattern 61c is, for example, not less than 2 μm and not more than 3 μm. The region where the semiconductor element is formed in the P-type well 1b is surrounded by the opening patterns 61a and 61c.
The opening pattern 61b is arranged so as to alternate with the P-type well 1a.

Next, as shown in FIG. 4A, the photoresist film 51 is developed. Thereby, an opening pattern corresponding to the opening pattern of the glass mask 61 is formed in the photoresist film 51. Next, using the photoresist film 51 as a mask, N-type impurity ions are implanted into the silicon substrate 1 with low energy.
As a result, an N-type well 1 c is formed in the silicon substrate 1 located in the digital region 10, and an N-type well 1 d is formed in the silicon substrate located in the analog region 11.

  Also, as shown in FIGS. 4A and 4B, N-type impurity ions are implanted into the entire periphery of the region where the semiconductor element is formed in the P-type well 1b. A high resistance region 1f having a high resistance is formed. The width of the high resistance region 1f is, for example, not less than 2 μm and not more than 3 μm. In the high resistance region 1f, it is preferable to be N-type. In FIG. 4B, the photoresist film 51 is not shown for explanation.

  Thus, in the region where the semiconductor element is formed in the P-type well 1b, the bottom is covered with the deep N-type well 1e, and the side surface is surrounded by the high-resistance region 1f. The bottom of the high resistance region 1f is also covered with the deep N type well 1e.

  Thereafter, the photoresist film 51 is removed as shown in FIG. Next, a thermal oxide film (not shown) and a silicon nitride film (not shown) are formed on the silicon substrate 1, and an opening pattern is formed in the silicon nitride film. Next, the silicon substrate 1 is thermally oxidized using this silicon nitride film as a mask. Thereby, an element isolation film 2 is formed on the silicon substrate 1. The element isolation film 2 is located at least on the high resistance region 1f, and isolates the P-type wells 1a and 1b and the N-type wells 1c and 1d from other regions. Thereafter, the silicon nitride film and the thermal oxide film are removed.

  Next, as shown in each drawing of FIG. 6, the silicon substrate 1 is thermally oxidized. Thus, gate insulating films 3a, 3b, 3c, 3d are formed on the silicon substrate 1 located in the P-type wells 1a, 1b and the N-type wells 1c, 1d, respectively. The gate insulating films 3b and 3d may be formed in a separate process from the gate insulating films 3a and 3c, respectively. In this way, the thickness of each of the gate insulating films 3b and 3d can be made different (for example, thicker) from the thickness of the gate insulating films 3a and 3c.

  Next, a polysilicon film is formed on the entire surface including the respective gate insulating films, and this polysilicon film is patterned. Thereby, gate electrodes 4a, 4b, 4c, and 4d are formed on the gate insulating films 3a, 3b, 3c, and 3d, respectively.

  Next, a photoresist film (not shown) is applied on the entire surface including the P-type wells 1a and 1b and the N-type wells 1c and 1d, and the photoresist film is exposed and developed. As a result, the photoresist film located on the P-type wells 1a and 1b is removed. Next, N-type impurities are introduced using this photoresist film as a mask. Thereby, N-type low-concentration impurity regions 6a and 6b are formed in the P-type wells 1a and 1b, respectively. Thereafter, the photoresist film is removed.

  Next, a photoresist film (not shown) is applied on the entire surface including the P-type wells 1a and 1b and the N-type wells 1c and 1d, and the photoresist film is exposed and developed. Thereby, the photoresist film located on the N-type wells 1c and 1d is removed. Next, P-type impurities are introduced using this photoresist film as a mask. Thereby, P-type low concentration impurity regions 6c and 6d are formed in the N-type wells 1c and 1d, respectively. Thereafter, the photoresist film is removed.

  Next, a silicon oxide film is formed on the entire surface including the gate electrodes 4a, 4b, 4c, and 4d, and the silicon oxide film is etched back. As a result, the side walls of the gate electrodes 4 a, 4 b, 4 c, 4 d are covered with the side walls 5.

  Next, a photoresist film (not shown) is applied on the entire surface including the P-type wells 1a and 1b and the N-type wells 1c and 1d, and the photoresist film is exposed and developed. As a result, the photoresist film located on the P-type wells 1a and 1b is removed. Next, N-type impurities are introduced using this photoresist film as a mask. As a result, N-type impurity regions 7a and 7b serving as a source and a drain are formed in the P-type wells 1a and 1b, respectively. Thereafter, the photoresist film is removed.

Next, a photoresist film (not shown) is applied on the entire surface including the P-type wells 1a and 1b and the N-type wells 1c and 1d, and the photoresist film is exposed and developed. As a result, the photoresist film located on the N-type wells 1c and 1d is removed. Next, P-type impurities are introduced using this photoresist film as a mask. As a result, P-type low-concentration impurity regions 7c and 7d serving as a source and a drain are formed in the N-type wells 1c and 1d, respectively. Thereafter, the photoresist film is removed.
In this way, transistors are formed in the P-type wells 1a and 1b and the N-type wells 1c and 1d, respectively.

  As described above, according to the first embodiment, in the P-type well 1b of the analog region 11, the region where the semiconductor element is formed is covered with the deep N-type well 1e at the bottom and surrounded by the high-resistance region 1f at the side. It is. The bottom of the high resistance region 1f is also covered with the deep N type well 1e. For this reason, even if the transistor operates and the potential of the P-type well 1a in the digital region 10 fluctuates, even if the potential fluctuation propagates through the P-type silicon substrate 1 as noise, the noise is generated by the deep N-type well 1e and the high resistance. It is blocked by region 1f and does not propagate to P-type well 1b. Accordingly, the potential of the P-type well 1b is stabilized.

  In addition, since the above-described structure is formed by the two photoresist films 50 and 51, the formation and patterning of the photoresist film are fewer than the conventional one, and the number of glass masks is also smaller than the conventional one. This lowers the manufacturing cost of the semiconductor device.

  FIG. 7 is a plan view for explaining a semiconductor device according to the second embodiment of the present invention. This embodiment has the same configuration as the well of the semiconductor device formed by the first embodiment except for the shape of the high resistance region 1f.

In the present embodiment, the high resistance region 1f is formed on the boundary between the P-type well 1b and the N-type well 1d and on the entire periphery of the edge of the P-type well 1b. The semiconductor device having such a structure can be manufactured by the same method as that of the first embodiment by changing the light shielding pattern of the glass mask 61.
In the present embodiment, transistors may be formed in the P-type wells 1a and 1b and the N-type wells 1c and 1d by the same process as that in the first embodiment.
Also according to the present embodiment, the same operations and effects as those of the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the case where the photoresist films 50 and 51 are negative, the light shielding films of the glass masks 60 and 61 have the opened portion and the remaining portion reversed.

(A) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment, (B) is a top view of the glass mask 60. FIG. Sectional drawing for demonstrating the next process of FIG. 1 (A). (A) is sectional drawing for demonstrating the next process of FIG. 2, (B) is a top view of the glass mask 61. FIG. (A) is sectional drawing for demonstrating the next process of FIG. 3 (A), (B) is a top view of the semiconductor device in the state of (A). Sectional drawing for demonstrating the next process of FIG. 4 (A). (A) is sectional drawing for demonstrating the next process of FIG. 5, (B) is AA sectional drawing of (A), (C) is BB sectional drawing of (A). The top view for demonstrating the semiconductor device which concerns on 2nd Embodiment. (A) is sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device, (B) is sectional drawing for demonstrating the next process of (A), (C) is the next process of (B). Sectional drawing for demonstrating.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101 ... Silicon substrate, 1a, 1b, 101a, 101b ... P type well, 1c, 1d, 101c, 101d, 101f ... N type well, 1e, 101e ... Deep N type well, 1f ... High resistance region, 2 ... Element isolation film, 3a, 3b, 3c, 3d ... gate insulating film, 4a, 4b, 4c, 4d ... gate electrode, 5 ... sidewall, 6a, 6b ... N-type low concentration impurity region, 6c, 6d ... P-type low Concentration impurity region, 7a, 7b ... P-type impurity region, 7c, 7d ... P-type impurity region, 10,110 ... digital region, 11,111 ... analog region, 50,51,121,122,123 ... photoresist film, 60, 61 ... Glass mask, 60a, 60b, 61a, 61b, 61c ... Opening pattern

Claims (12)

Forming a first mask film having a first opening pattern on a first conductivity type semiconductor substrate;
Forming a second conductivity type deep well in the semiconductor substrate by implanting second conductivity type impurity ions into the semiconductor substrate using the first mask film as a mask;
Forming a first conductivity type well located on the deep well in the semiconductor substrate by introducing a first conductivity type impurity into the semiconductor substrate using the first mask film as a mask;
Removing the first mask film;
Forming a second mask film having a second opening pattern on the semiconductor substrate;
Forming a second conductivity type well in the semiconductor substrate by introducing a second conductivity type impurity into the semiconductor substrate using the second mask film as a mask;
Removing the second mask film;
Comprising
The second opening pattern is located at least around the entire edge of the first conductivity type well,
In the step of forming the second conductivity type well, a second conductivity type impurity is introduced into the entire periphery of the first conductivity type well, and the entire periphery of the edge increases the resistance of the semiconductor substrate. Manufacturing method. Forming a first mask film having a first opening pattern on a first conductivity type semiconductor substrate;
Forming a second conductivity type deep well in the semiconductor substrate by implanting second conductivity type impurity ions into the semiconductor substrate using the first mask film as a mask;
Forming a first conductivity type well located on the deep well in the semiconductor substrate by introducing a first conductivity type impurity into the semiconductor substrate using the first mask film as a mask;
Removing the first mask film;
Forming a second mask film having a second opening pattern on the semiconductor substrate;
Forming a second conductivity type well in the semiconductor substrate by introducing a second conductivity type impurity into the semiconductor substrate using the second mask film as a mask;
Removing the second mask film;
Comprising
The second opening pattern is located at least around the entire periphery of the region where the element is formed on the first conductivity type well,
In the step of forming the second conductivity type well, a second conductivity type impurity is introduced to the entire periphery of the region where the element is formed in the first conductivity type well, and the entire periphery of the well is introduced into the semiconductor substrate. In contrast, a method for manufacturing a semiconductor device with high resistance.   3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of forming the second conductivity type well, the edge having the increased resistance is changed to a second conductivity type.   The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type well is located in an analog region where an analog circuit is formed. 6. The semiconductor substrate has the analog region and a digital region where a digital circuit is formed,
6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the step of forming the first conductivity type well, the first conductivity type well is also formed in the semiconductor substrate located in the digital region. A first conductivity type well formed in a first conductivity type semiconductor substrate;
A high resistance region formed on the semiconductor substrate and surrounding a side surface of the first conductivity type well and having a higher resistance than the semiconductor substrate;
A second conductivity type deep well located under the first conductivity type well and the high resistance region;
A semiconductor device comprising: A first conductivity type well formed in a first conductivity type semiconductor substrate;
A high resistance region formed on the semiconductor substrate and surrounding a side surface of a region of the first conductivity type well where a semiconductor element is formed;
A second conductivity type deep well located under the first conductivity type well and the high resistance region;
A semiconductor device comprising:   9. The semiconductor device according to claim 7, wherein a first conductivity type impurity and a second conductivity type impurity are respectively introduced into the high resistance region.   The semiconductor device according to claim 7, wherein the high resistance region is a second conductivity type.   The semiconductor device according to claim 7, wherein a width of the high resistance region is 2 μm or more. The first conductivity type well is located in an analog region where an analog circuit is formed;
The semiconductor device according to claim 7, further comprising a second conductivity type well located in a digital region where a digital circuit is formed.

Images