KR20110083978A - Method of forming fine pattern of semiconductor device - Google Patents

Method of forming fine pattern of semiconductor device Download PDF

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Publication number
KR20110083978A
KR20110083978A KR1020100003984A KR20100003984A KR20110083978A KR 20110083978 A KR20110083978 A KR 20110083978A KR 1020100003984 A KR1020100003984 A KR 1020100003984A KR 20100003984 A KR20100003984 A KR 20100003984A KR 20110083978 A KR20110083978 A KR 20110083978A
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KR
South Korea
Prior art keywords
hard mask
layer
forming
patterns
material layer
Prior art date
Application number
KR1020100003984A
Other languages
Korean (ko)
Inventor
이성은
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100003984A priority Critical patent/KR20110083978A/en
Publication of KR20110083978A publication Critical patent/KR20110083978A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

The present invention discloses a method of forming a fine pattern of a semiconductor device capable of forming a fine pattern while reducing the number of masks by using hard mask layers having different etching selectivity. In the method of forming a fine pattern of a semiconductor device of the present invention, forming the first to third hard mask layers sequentially on a semiconductor substrate, patterning the third hard mask layer to form a third hard mask in a cell region on the semiconductor substrate. Forming patterns, forming spacers on both sidewalls of the third hard mask patterns, and patterning the second hard mask layer to form second hard mask patterns in the cell region and a peripheral circuit region on the semiconductor substrate, respectively. And forming a first hard mask pattern in the cell region and the peripheral circuit region by patterning a first hard mask layer using the second hard mask patterns.

Description

Method of forming fine pattern of semiconductor device

The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly to a method of forming a fine pattern of a semiconductor device using a hard mask layer having different etching selectivity.

In the conventional method of forming a fine pattern, a partition pattern is formed using a cell mask, a spacer is formed on sidewalls of the partition pattern, an active mask pattern of a cell region is formed with a cutting mask, and a peripheral circuit region open mask is used. The active mask pattern of the peripheral circuit region was formed, and a shallow trench etching process was performed using the active pattern.

However, the conventional method for forming the active trench region by forming the shallow trench isolation layer has to use three masks, which causes a complicated process.

The present invention provides a method of forming a fine pattern of a semiconductor device capable of forming a fine pattern while reducing the number of masks.

In the method of forming a fine pattern of a semiconductor device according to an embodiment of the present invention, the step of sequentially forming the first to third hard mask layer on the semiconductor substrate, by patterning the third hard mask layer cell area on the semiconductor substrate Forming a third hard mask pattern on the substrate, forming spacers on both sidewalls of the third hard mask patterns, and patterning the second hard mask layer to form second hard mask patterns on the cell region and the peripheral circuit region. Forming each of the first hard mask layers by using the second hard mask patterns to form first hard mask patterns in the cell region and the peripheral circuit region.

The second hard mask layer may include first and second hard mask material layers having different etching selectivity. The first hard mask material layer may include a polysilicon film, and the second hard mask material layer may include a nitride film. Alternatively, the first hard mask material layer may include a nitride film, and the second hard mask material layer may include a polysilicon film.

The spacer may include a nitride film. The forming of the second hard mask patterns using the spacer may include patterning the second hard mask material layer patterns of the second hard mask layer using the spacer as an etch mask to form second hard mask material layer patterns. Forming a fourth hard mask layer on the first hard mask material layer including the second hard mask material layer patterns; patterning the fourth hard mask layer to form a fourth Forming hard mask patterns in the cell region and the peripheral circuit region, respectively, and patterning the second hard mask material layer using the fourth hard mask patterns to form a second hard mask material layer pattern. can do.

The fourth hard mask layer may include a multifunctional hard mask layer. An anti-reflection film may be further formed on the fourth hard mask layer.

After forming the first and third hard mask layers, anti-reflection films may be further formed on the first and third hard mask layers.

According to the method of forming a fine pattern of a semiconductor device of the present invention as described above, by using a hard mask layer having a different etching selectivity, by forming a hard mask pattern of the cell region and the peripheral circuit region to reduce the number of masks than conventional In addition to simplifying the process, it can be formed to use fine patterns below the limit resolution.

1A to 1H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

1A to 1H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a semiconductor substrate 100 is provided. The semiconductor substrate 100 may include a silicon substrate. The semiconductor substrate 100 may include a cell region 101 in which memory cells are arranged and a peripheral circuit region 105 in which peripheral circuits are arranged.

A first hard mask layer, a second hard mask layer, and a third hard mask layer are sequentially stacked on the semiconductor substrate 100. Since the first hard mask layer acts as a substantial hard mask during the subsequent etching process, the anti-reflective layer during the exposure process, for example, the first hard mask material layer 110 and the exposure layer to provide a sufficient etching margin. The first anti-reflection film 120 may be included. The first hard mask material layer 110 may include an amorphous carbon layer (ACL) having excellent hard mask properties, and the second anti-reflection film 120 may include a silicon oxynitride layer (SiON). .

The second hard mask layer includes third and fourth hard mask material layers 130 and 140 having a two-layer structure. The third and fourth hard mask material layers 130 and 140 may have different etching selectivity. For example, the third hard mask material layer 130 may include a polysilicon layer, and the fourth hard mask material layer 140 may include a nitride layer. Alternatively, the third hard mask material layer 130 may include a nitride film, and the fourth hard mask material layer 140 may include a polysilicon film.

Like the first hard mask layer, the third hard mask layer may include a fourth hard mask material layer 150 and a second anti-reflection film 160. The fourth hard mask material layer 150 may include an amorphous carbon film, and the second anti-reflection film 160 may include a silicon oxynitride film.

The photosensitive film 170 is formed on the second anti-reflection film 160. The photoresist film 170 is patterned using a cell mask (not shown) to leave the photoresist film 170 in the cell region 101.

Referring to FIG. 1B, the second anti-reflection film 160 and the fourth hard mask material layer 150 of the third hard mask layer are patterned using the photosensitive film 170 as a mask to form fourth hard mask patterns 155. ) Is formed in the cell region 101. The fourth hard mask patterns 155 may be formed to have a partition shape arranged one per pitch of two active regions to be formed in a subsequent process.

Referring to FIG. 1C, an insulating layer 180 for spacers is formed on the third hard mask material layer 140 including the fourth hard mask patterns 155. The spacer insulating layer 180 may include a nitride layer.

Referring to FIG. 1D, spacers 185 are formed on both sides of the fourth hard mask patterns 155 by etching back the spacer insulating layer 180. Subsequently, the fourth hard mask patterns 155 are removed.

Referring to FIG. 1E, the third hard mask material layer 140 of the second hard mask layer is etched using the spacers 185 as an etching mask. Accordingly, third hard mask patterns 145 are arranged on the second hard mask material layer 130 of the cell region 101. Subsequently, the spacers 185 are removed. The spacers 185 may be removed through a cleaning process.

Referring to FIG. 1F, a multifunction hardmask (MFHM) layer 190 is formed on the second hardmask material layer 130 on which the third hardmask patterns 145 are formed. The multifunctional hard mask layer 190 is a film having excellent flow characteristics, and may be formed by a coating method. The multifunctional hard mask layer 190 may be a film that simultaneously serves as an etching barrier and an anti-reflection film, and may include, for example, a film containing silicon in a BARC (Bottom Anti Coating Layer) film.

An anti-reflection film 200, such as a silicon oxynitride layer (SiON), may be formed on the multifunctional hard mask layer 190. Alternatively, a coating film such as a spin on carbon (SOC) layer may be further formed on the multifunctional hard mask layer 190. In addition, a hard mask layer may be further formed on the multifunctional hard mask layer 190.

A photosensitive film (not shown) is formed on the multifunctional hard mask layer 190. The photoresist may include an ArF photoresist. The photoresist is patterned using a cutting mask (not shown) to form a photoresist pattern 171 for cutting and a photoresist pattern 175 for a peripheral circuit in the peripheral circuit region 105 on the cell region 101.

Referring to FIG. 1G, the multifunctional hard mask layer 190 is etched using the photoresist patterns 171 and 175 to form a multifunctional hard mask pattern (not shown). The second hard mask layer 130 is etched using the multifunctional hard mask pattern. Accordingly, second hard mask patterns 131 and 135 are formed in the cell region 101 and the peripheral circuit region 105, respectively. In this case, some of the third hard mask patterns 145 may be removed from the cell region 101, and the remaining multifunctional hard mask pattern may be removed using an O 2 plasma.

Referring to FIG. 1H, the first hard mask layer 110 and the first anti-reflection film 120 are patterned using the second hard mask patterns 131 and 135 as an etch mask to form the cell region 101. ) And the first hard mask patterns 111 and 115 are formed in the peripheral circuit region 105, respectively.

Subsequently, although not shown in the drawing, the semiconductor substrate 100 is etched by a predetermined depth using the first hard mask patterns 111 and 115 to form a trench, and the cell region 101 and the peripheral circuit are formed. An isolation layer defining an active region may be formed in the trench of the region 105.

In the embodiment of the present invention, a hard mask pattern of a cell region and a peripheral circuit region is formed using a hard mask layer having different etching selectivity, and an active region is formed using the same. The same can be applied to a method for forming a fine pattern such as an insulating film or a conductive film.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, various modifications by those skilled in the art within the spirit and scope of the present invention And changes are possible.

100: semiconductor substrate 110, 130, 140, 150, 200: hard mask layer
111, 115, 131, 135, 145, 155: hard mask pattern
120, 160: antireflection film 170, 171: photoresist pattern
180: nitride film for spacer 185: spacer
190: Multifunctional Hard Mask Layer

Claims (9)

Sequentially forming the first to third hard mask layers on the semiconductor substrate;
Patterning the third hard mask layer to form third hard mask patterns in a cell region on the semiconductor substrate;
Forming spacers on both sidewalls of the third hard mask patterns;
Patterning the second hard mask layer to form second hard mask patterns in the cell region and a peripheral circuit region on the semiconductor substrate, respectively; And
And forming first hard mask patterns in the cell region and the peripheral circuit region by patterning a first hard mask layer using the second hard mask patterns. The method of claim 1, wherein the second hard mask layer comprises first and second hard mask material layers having different etching selectivity. 3. The method of claim 2, wherein the first hard mask material layer comprises a polysilicon layer and the second hard mask material layer comprises a nitride layer. 3. The method of claim 2, wherein the first hard mask material layer comprises a nitride film and the second hard mask material layer comprises a polysilicon film. The method of claim 1, wherein the spacer comprises a nitride film. The method of claim 2, wherein the forming of the second hard mask patterns using the spacer is performed.
Patterning the second hardmask material layer of the second hardmask layer using the spacer as an etch mask to form second hardmask material layer patterns in the cell region;
Forming a fourth hard mask layer on the first hard mask material layer including the second hard mask material layer patterns;
Patterning the fourth hard mask layer to form fourth hard mask patterns in the cell region and the peripheral circuit region, respectively; And
And patterning the second hard mask material layer using the fourth hard mask patterns to form a second hard mask material layer pattern. The method of claim 6, wherein the fourth hard mask layer comprises a multifunctional hard mask layer. The method of claim 6, further comprising forming an anti-reflection film on the fourth hard mask layer after forming the fourth hard mask layer. The method of claim 1, further comprising forming anti-reflection films on the first and third hard mask layers after forming the first and third hard mask layers. .
KR1020100003984A 2010-01-15 2010-01-15 Method of forming fine pattern of semiconductor device KR20110083978A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211089B2 (en) 2016-09-22 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR20200110598A (en) * 2019-03-15 2020-09-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Ultra narrow trench patterning using plasma etching

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211089B2 (en) 2016-09-22 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR20200110598A (en) * 2019-03-15 2020-09-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Ultra narrow trench patterning using plasma etching
US11348800B2 (en) 2019-03-15 2022-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra narrow trench patterning with dry plasma etching
US11894237B2 (en) 2019-03-15 2024-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra narrow trench patterning with dry plasma etching

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