KR20130022677A - Method for fabricating array of fine patterns in semiconductor device - Google Patents

Method for fabricating array of fine patterns in semiconductor device Download PDF

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Publication number
KR20130022677A
KR20130022677A KR1020110085451A KR20110085451A KR20130022677A KR 20130022677 A KR20130022677 A KR 20130022677A KR 1020110085451 A KR1020110085451 A KR 1020110085451A KR 20110085451 A KR20110085451 A KR 20110085451A KR 20130022677 A KR20130022677 A KR 20130022677A
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South Korea
Prior art keywords
patterns
cell line
line patterns
dummy
cell
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KR1020110085451A
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Korean (ko)
Inventor
최진영
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에스케이하이닉스 주식회사
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Priority to KR1020110085451A priority Critical patent/KR20130022677A/en
Publication of KR20130022677A publication Critical patent/KR20130022677A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

PURPOSE: A method for arranging fine patterns of a semiconductor device is provided to effectively suppress a pattern bridge defect in an exposure process by improving a mask layout of a photomask. CONSTITUTION: A first photomask with a first cell line pattern(111) and a first dummy line pattern(113) is formed. The first cell line pattern is arranged in an X axis direction. The first dummy line pattern is arranged in a Y axis direction. A second photomask with a second cell line pattern(131) and a second dummy line pattern(133) is formed. The second cell line pattern is arranged in the Y axis direction. The second dummy line pattern is arranged in the X axis direction. A resist layer is firstly exposed by using the first photomask. The resist layer is secondly exposed by using the second photomask. A first mask layout(110) is extracted as a layout including the first cell line patterns and the first dummy line patterns. A second mask layout(130) is extracted as a layout including the second cell line patterns and the second dummy line patterns. [Reference numerals] (AA) Cell area; (BB) Dummy area

Description

Method for fabricating array of fine patterns in semiconductor device

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly to a method of forming an array of fine patterns using double exposure techniques.

As the design rule of a semiconductor device is reduced, the size of patterns constituting the device is rapidly reduced. As the pattern required to form a DRAM memory device or a phase change random access memory is miniaturized, a micropattern is implemented on a wafer at a size smaller than a resolution that can be implemented in a lithography process. Pattern-forming techniques using double patterning or double exposure techniques have been tried. The double patterning technique includes two exposures and two development processes, but a large burden on the process cost requires development of a double exposure technique including two exposures and one development process. It is becoming.

Unlike the lithography-lithography-etching (LLE) or lithography-freezing-lithography-etching (LFLE) process, the double exposure technique uses a single photoresist. Since it requires a coating process (PR), it has the advantage of improving the CD uniformity of the pattern, but it may represent a weak point that is difficult to secure the process margin.

For example, an array of pillar patterns may be formed in a cell region, and a larger rectangular cell block may be formed as dummy patterns outside the pillar patterns. In this case, in the double exposure technique, the pillar patterns are patterned by a combination of the primary exposure and the secondary exposure, and the arrangement of the dummy patterns is patterned with the cell block located outside the cell. However, since the size of the dummy patterns, which are the cell blocks, is relatively large compared to the cell patterns, which are pillar patterns, more exposure light amount must be provided to the dummy patterns in order to separate the dummy patterns from each other. However, since the exposure light amount is set at a lower level in accordance with the level of separating the cell patterns, the amount of exposure light is insufficient to separate the dummy patterns, thereby causing a pattern defect. Defects in which a pattern bridge or a profile is poor in dummy patterns, which are cell blocks, may be caused. This pattern defect is due to difficulty in providing an appropriate amount of exposure light required for each region, which is a process margin in a double exposure technique in which a pattern is realized by a combination of exposure light provided in the first and second exposures. This may mean weakness.

According to the present invention, when a resist layer is applied on a semiconductor substrate and double exposure is performed using two photomasks on the resist layer to form an array of fine patterns, a pattern bridge defect which may be caused during the exposure process may be photosensitive. By improving the mask layout of the mask to provide a method that can be suppressed during the exposure process.

According to an aspect of the invention, the first cell line patterns arranged in the X-axis direction, and the first dummy line pattern arranged in the Y-axis direction to extend in the X-axis direction on the side portions of the first cell line patterns Forming a first photomask including photomasks; A second cell line pattern arranged in the Y-axis direction and a second dummy line pattern arranged in the X-axis direction so as to extend in the Y-axis direction on the side portions of the second cell line patterns; Forming a photomask; First exposing the resist layer using the first photomask; Second exposure of the resist layer using the second photomask; And developing the first and second exposed resist layers to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and forming the first cell line patterns and the first cell. Forming the resist layer portions in which the dummy line patterns cross and the resist layer portions in which the second cell line patterns and the first dummy line patterns intersect in dummy patterns. It presents a way to form an array of them.

The first exposure step is performed by employing X-axis dipole illumination, and the second exposure step provides a method of forming an array of fine patterns of a semiconductor device, which is performed by employing Y-axis dipole illumination.

Another aspect of the present invention includes first cell line patterns arranged mutually, and first dummy line patterns mutually arranged to extend perpendicular to the first cell line patterns at the sides of the first cell line patterns. Forming a first photomask; Second cell line patterns arranged to extend perpendicular to the first cell line patterns, and a second cell line arranged to extend in a direction in which the first cell line patterns extend on a side of the second cell line patterns Forming a second photomask including dummy line patterns; Double exposure of a resist layer using the first and second photomasks; And developing the double-exposed resist layer to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and the first cell line patterns and the second dummy line pattern. Forming dummy patterns of the resist layer portions in which the resist layers and the second cell line patterns and the first dummy line patterns cross each other in dummy patterns. How to do it.

Another aspect of the present invention includes first cell line patterns arranged mutually, and first dummy line patterns mutually arranged to extend perpendicular to the first cell line patterns at the sides of the first cell line patterns. Forming a first photomask; Second cell line patterns arranged to extend perpendicular to the first cell line patterns, and a second cell line arranged to extend in a direction in which the first cell line patterns extend on a side of the second cell line patterns Forming a second photomask including dummy line patterns; Double exposure of the resist layer on the object layer to be etched using the first and second photomasks; The double-exposed resist layer is developed to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and the first cell line patterns and the second dummy line patterns Forming dummy portions of the resist layer portions crossing the resist layer portions and the second cell line patterns and the first dummy line patterns; And selectively etching an exposed portion of the etch target layer using the cell patterns and the dummy patterns as an etch mask to form cell pillar patterns and dummy pillar patterns. A method of forming an array of fine patterns of a device is presented.

The cell pillar patterns and the dummy pillar patterns provide a method of forming an array of fine patterns of a semiconductor device formed as a lower electrode of a diode of a phase change memory device.

According to an embodiment of the present invention, the present invention is a pattern that can be caused in the exposure process when applying a resist layer on a semiconductor substrate and double exposure using two photomasks on the resist layer to form an array of fine patterns Bridge bridge defects can be effectively suppressed during the exposure process by improving the mask layout of the photomask.

1 is a layout diagram showing an arrangement of fine patterns of a semiconductor device according to an embodiment of the present invention.
2 to 4 illustrate layouts of photomasks used in a method of forming an array of fine patterns of a semiconductor device according to an exemplary embodiment of the inventive concept.
5 and 6 are diagrams illustrating modified illumination systems used in a method of forming an array of fine patterns of a semiconductor device according to an exemplary embodiment of the present invention.
7 to 10 are views illustrating a method of forming an array of fine patterns of a semiconductor device according to an embodiment of the present invention.
FIG. 11 is a measurement photograph provided to explain an effect of a method of forming an array of fine patterns of a semiconductor device according to an exemplary embodiment of the present inventive concept.
12 and 13 illustrate examples of applying a method of forming an array of fine patterns of a semiconductor device to fabrication of a phase change memory device according to an embodiment of the present invention.

In an embodiment of the present invention, an array of pillar patterns is formed in a cell region, and together with a dummy pattern, a larger rectangular cell block is formed around the pillar patterns. When forming the photomasks, the size of the dummy patterns, which are the cell blocks, is relatively large compared to the cell patterns, which are the pillar patterns, so that more exposure light amount is provided to the dummy patterns so that the dummy patterns are separated from each other. Improve mask layout. The improved mask layout can further increase the amount of exposure light for separation of the dummy patterns without increasing the amount of exposure light provided to the cell patterns, causing the dummy patterns to be caused by the lack of the amount of exposure light to the dummy patterns. It is possible to effectively compensate and suppress a defect in which a pattern bridge or profile becomes poor.

Referring to FIG. 1, pillar patterns are arranged in cell patterns 11 in a cell region in which memory cells of a DRAM device or a phase change memory device are disposed. Dummy patterns 13 may be disposed outside the array of the (11). The cell patterns 11 may be patterned to implement circuit patterns constituting a DRAM memory cell or may be patterned with lower electrodes of a diode constituting a phase change memory cell. A target layout in which dummy patterns 13 are arranged outside a matrix array of cell patterns 11 is designed.

Although the cell pattern 11 is a pillar pattern, the cell pattern 11 may be set as a hard mask pattern or a pattern for an active region in addition to the pillar pattern. When designing the target layout of the pattern to be formed, the dummy patterns 13 are arranged in order to induce an effect in which the pattern arrangement regularity is continued on the outside of the cell patterns 11. When the neighboring cell pattern 11 is exposed or transferred or etched, the dummy pattern 13 provides a surrounding environment similar to the surrounding environment of the other cell pattern 11 inside, so that the dummy pattern 13 is adjacent to the dummy pattern 13. It serves to guide the cell pattern 11 to be patterned by exposure transfer or etching as designed to a more accurate shape. The dummy pattern 13 may be designed in a pattern having a larger critical dimension (CD) than the cell hole pattern 11 or may have a rectangular shape compared to the cell pattern 11 in a circular pattern. .

Referring to FIG. 2, photomask layouts for forming a photomask to be used in an exposure process using the target layout of FIG. 1 in which the cell patterns 11 and the dummy patterns 13 are disposed outside are formed. 110, 130). The first cell line patterns 111 and the second cell line patterns 131 are arranged in the intersecting lines so that the intersecting portions are set in the cell patterns 11. The second dummy line patterns 133 are arranged such that portions intersecting portions extending to the dummy regions of the first cell line patterns 111 are set as the dummy patterns 13. The first dummy line patterns 113 are arranged such that portions intersecting with portions extending to the dummy regions of the second cell line patterns 113 are also set as the outer dummy patterns 13. As illustrated in the first region 201, the first dummy line patterns 113 may be disposed in a short line pattern compared to the rectangular patterns spaced apart from each other or the second cell line patterns 131 extending in the X-axis direction. have.

Since there is a space between the first dummy line patterns 113, the exposure light may be projected to the space part during the exposure process, so that the portion where the first dummy line patterns 113 on the wafer are to be positioned, that is, In this case, a larger amount of exposure light may be transmitted and incident to a portion where the dummy patterns 13 of FIG. 1 are to be positioned. Accordingly, it is possible to ensure the amount of exposure light effective for the dummy patterns 13 on the wafer to be separated from each other without increasing the total amount of exposure light so that the gap between the dummy patterns 13 in FIG. 1 is not separated due to lack of the exposure light amount. The pattern bridge phenomenon can be effectively suppressed and prevented. In addition, the width of the gap between the patterned dummy patterns 13 may be increased by enlarging the line width of the spaced spaces between the first dummy line patterns 113, so that the gaps between the dummy patterns 13 may be increased. When depositing a filling insulating layer, it is possible to effectively suppress the occurrence of gap fill defects such as voids by improving the gap fill characteristic.

Similarly, the second dummy line patterns 133 are arranged in a short line pattern as compared to the rectangular patterns spaced apart from each other or the first cell line patterns 111 extending in the Y-axis direction as shown in the second region 201. Can be. The first and second dummy line patterns 113 and 133 are designed to have a larger line width in the rectangular shape so that the dummy pattern 13 positioned in the dummy area of the rectangular or rectangular corner portion of the cell area is guided to the rectangle. Can be deployed.

As shown in FIG. 2, after designing a mask layout to implement the target layout of FIG. 1, each of the first mask layout 110 and the second mask layout 130 is extracted. The first mask layout 110 is extracted as the layout including the first cell line patterns 111 and the first dummy line pattern 113, and the second mask layout 130 is the second cell line pattern 131. And a second dummy line pattern 133 may be extracted.

3 and 4, each of the extracted first and second mask layouts 110 and 130 is implemented as a mask pattern, for example, a light shielding pattern or a phase inversion pattern, on each of the transparent substrates 115 and 135. do. Since the implemented mask patterns follow the first and second mask layouts 110 and 130, the mask patterns are denoted by the same reference numerals. As shown in FIG. 3 by a photomask manufacturing process, a mask pattern of the first cell line patterns 111 and the first dummy line pattern 113 is implemented on the transparent substrate 115. ) Is provided. In addition, as shown in FIG. 4, a second photomask 103 having a mask pattern of the second cell line patterns 131 and the second dummy line pattern 133 is implemented on the transparent substrate 135.

The double exposure process using the first and second photomasks 101 and 103 manufactured as described above is performed. In this case, the exposure process may be performed by using modified illuminations, for example, dipole modified illuminations, which may implement a resolution improvement in exposing and transferring the line-shaped patterns. For example, in the case of the first photomask 101, since the first cell line patterns 111 extend in the Y-axis direction, as illustrated in FIG. 5, an X-axis dipole (image axis) is advantageous and resolution is improved. 310, that is, X-axis dipole 310 illumination in which openings 311 through which light is transmitted may be used. In the case of the second photomask 103, since the second cell line patterns 131 extend in the X-axis direction, as illustrated in FIG. 6, the Y-axis dipole 310 is advantageous in image forming and the resolution is improved. That is, the Y-axis dipole 310 may be used in which the openings 331 through which light is transmitted in the Y-axis direction are positioned.

Referring to FIG. 7, a conductive layer or an insulating layer, which is an etching target layer 430, is formed on a semiconductor substrate or wafer 410, and a resist layer 450 is formed on the etching target layer 430. When the exposure process is performed using an ArF lithography apparatus, the resist layer 450 may be formed by coating a resist for ArF exposure.

Referring to FIG. 8, the resist layer 450 is first exposed using a first photomask (101 of FIG. 3). The first cell line patterns 111 of FIG. 3 are transferred by the first exposure, so that the first unexposed resist first region 451, the first exposed second region 452, and the first dummy line pattern 113 are exposed. ) Are transferred to form the first unexposed third region 453 and the first exposed fourth region 454 in the resist layer 450.

Referring to FIG. 9, the first exposed resist layer 450 is second exposed using a second photomask 103 (in FIG. 4). The second cell line patterns 131 of FIG. 4 are transferred by the second exposure, so that the second unexposed resist fifth region 455 and the second exposed sixth region 456 and the second dummy line pattern 133 are transferred. ) Are transferred so that the seventh non-exposed seventh region 457 and the second exposed eighth region 458 are inductively formed in the resist layer 450.

In this case, portions of the resist layer 450 that intersect the first and second cell line patterns 111 and 113 of FIGS. 3 and 4, that is, the first region 451 and the fifth region 455 overlap each other. The portion exists as an unexposed region in both the first and second exposures and is patterned into cell patterns (11 in FIG. 1) after development, and the remaining second regions 452 and sixth regions 456 are all exposed. It is present as a region and will be removed in subsequent development. In addition, portions of the resist layer 450 where the first cell line patterns 111 and the second dummy line pattern 133 intersect, that is, a portion where the first region 451 and the seventh region 457 overlap with each other, are also included. It exists as an unexposed area in both the first and second exposures and is patterned into dummy patterns (13 in FIG. 1) after development. The remaining second region 452 and the eighth region 458 are both exposed regions and are removed in subsequent development. Similarly, portions of the resist layer 450 where the second cell line patterns 131 and the first dummy line pattern 113 intersect, that is, the third region 453 and the fifth region 455 are formed. The overlapping portions also exist as unexposed regions in both the first and second exposures and are patterned into dummy patterns (13 in FIG. 1) after development. The remaining fourth region 454 and the sixth region 456 are both exposed regions and are removed in subsequent development.

The resist layer 450 patterned by the first and second post-exposure development processes is a second resist pattern 461 and an array of dummy patterns, which are an array of pillar patterns or an array of cell patterns, as shown in FIG. 10. Patterned into resist patterns 463.

The shape of the actual resist patterns 461 and 463 formed by the first and second exposure using the first and second photomasks (101 in FIG. 3 and 103 in FIG. 4) according to an exemplary embodiment of the present invention are measured. The resulting photographs are shown in FIG. The photographs shown in FIG. 11 show that defects such as pattern bridges are effectively suppressed between dummy patterns even under a set exposure energy condition, for example, the best energy condition. It is shown that the pattern bridge is effectively suppressed even when exposed to light and -mj when exposed to low exposure energy. This proves that the margin of exposure energy can be secured at least 2mj margin under the exposure conditions, thereby improving the process margin of the exposure process.

12 and 13 showing a cross section along the AA ′ cutting line of FIG. 10, a method of forming an array of fine patterns according to an embodiment of the present invention is provided in which the arrangement of the lower electrodes of the diode of the phase change memory device is shown. Can be applied to implement For example, by using the resist patterns 461 and 463 formed as shown in FIG. 10 as an etch mask, the exposed portions of the etch target layer 430 may be selectively etched to form the cell electrodes 431 as cell patterns. And dummy electrodes 433 as dummy patterns. Subsequently, as shown in FIG. 13, after forming the insulating layer 470 filling the cell electrode 431 and the dummy electrode 433, the phase transition layer is formed on each of the cell electrode 431 and the dummy electrode 433. The diodes of the memory cells of the phase change memory device may be formed by patterning the 510 and the upper electrodes 530.

In the method of forming a fine pattern according to the embodiment of the present invention, as described above, a process of forming a lower electrode of a phase-transfer memory element or forming a trench for a field region for setting an active state of the memory element is performed. It can be applied to form repeating patterns of fine size, such as the process of forming a hard mask to be used to.

11: cell pattern, 13: dummy pattern,
101: first photomask, 103: second photomask,
111: first cell line pattern, 113: first dummy line pattern,
131: second cell line pattern, 133: first dummy line pattern.

Claims (5)

A first photomask including first cell line patterns arranged in an X-axis direction and first dummy line patterns arranged in a Y-axis direction to extend in the X-axis direction at sides of the first cell line patterns; forming a photomask;
A second cell line pattern arranged in the Y-axis direction and a second dummy line pattern arranged in the X-axis direction so as to extend in the Y-axis direction on the side portions of the second cell line patterns; Forming a photomask;
First exposing the resist layer using the first photomask;
Second exposure of the resist layer using the second photomask; And
Developing the first and second exposed resist layers to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and forming the first cell line patterns and the second Forming dummy patterns of the resist layer portions in which the dummy line patterns cross and the resist layer portions in which the second cell line patterns and the first dummy line patterns intersect, into dummy patterns. How to form an array.
The method of claim 1,
The first exposure step
Is done by employing X-axis dipole lighting,
The second exposure step
A method of forming an array of fine patterns of a semiconductor device that is performed by employing Y-axis dipole illumination.
A first photomask including mutually arranged first cell line patterns and first dummy line patterns arranged on a side of the first cell line patterns to extend perpendicular to the first cell line patterns Forming a;
Second cell line patterns arranged to extend perpendicular to the first cell line patterns, and a second cell line arranged to extend in a direction in which the first cell line patterns extend on a side of the second cell line patterns Forming a second photomask including dummy line patterns;
Double exposure of a resist layer using the first and second photomasks; And
The double-exposed resist layer is developed to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and the first cell line patterns and the second dummy line patterns Forming an array of fine patterns of the semiconductor device, the method including forming dummy patterns of the resist layer portions that cross and the second cell line patterns and the first dummy line patterns. Way.
A first photomask including mutually arranged first cell line patterns and first dummy line patterns arranged on a side of the first cell line patterns to extend perpendicular to the first cell line patterns Forming a;
Second cell line patterns arranged to extend perpendicular to the first cell line patterns, and a second cell line arranged to extend in a direction in which the first cell line patterns extend on a side of the second cell line patterns Forming a second photomask including dummy line patterns;
Double exposure of the resist layer on the object layer to be etched using the first and second photomasks;
The double-exposed resist layer is developed to form portions of the resist layer where the first and second cell line patterns intersect into cell patterns, and the first cell line patterns and the second dummy line patterns Forming dummy portions of the resist layer portions crossing the resist layer portions and the second cell line patterns and the first dummy line patterns; And
Selectively etching the exposed portion of the etch target layer using the cell patterns and the dummy patterns as an etch mask to form cell pillar patterns and dummy pillar patterns To form an array of fine patterns.
5. The method of claim 4,
And the cell pillar patterns and the dummy pillar patterns are formed as a lower electrode of a diode of a phase change memory device.
KR1020110085451A 2011-08-26 2011-08-26 Method for fabricating array of fine patterns in semiconductor device KR20130022677A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319741B2 (en) 2016-12-14 2019-06-11 Samsung Electronics Co., Ltd. Semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319741B2 (en) 2016-12-14 2019-06-11 Samsung Electronics Co., Ltd. Semiconductor devices

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