KR20090044586A - Overlay vernier and method of forming the same - Google Patents

Overlay vernier and method of forming the same Download PDF

Info

Publication number
KR20090044586A
KR20090044586A KR1020070110726A KR20070110726A KR20090044586A KR 20090044586 A KR20090044586 A KR 20090044586A KR 1020070110726 A KR1020070110726 A KR 1020070110726A KR 20070110726 A KR20070110726 A KR 20070110726A KR 20090044586 A KR20090044586 A KR 20090044586A
Authority
KR
South Korea
Prior art keywords
vernier
overlay
pattern
layer
forming
Prior art date
Application number
KR1020070110726A
Other languages
Korean (ko)
Inventor
구선영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070110726A priority Critical patent/KR20090044586A/en
Publication of KR20090044586A publication Critical patent/KR20090044586A/en

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/682—Mask-wafer alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

The present invention relates to an overlay vernier and a method of forming the same. More particularly, the present invention relates to a band-shaped first parent vernier, a band-shaped second parent vernier formed inside the first mother vernier, and a second mother vernier. It relates to an overlay vernier and a method for forming the same comprising a box-shaped ruler vernier. The overlay vernier of the present invention and the method of forming the same do not need to separately form a vernier which is added only for the purpose of overlay control in double patterning in another region of the scribing lane, and also in one mask only when double patterning is applied. The advantage is that the overlap control can be performed evenly without bias.

Overlay Vernier, Mod Vernier, Purple Vernier, Double Patterning

Description

Overlay Vernier and Method of Forming the Same}

The present invention relates to an overlay vernier and a method of forming the same, and more particularly, an overlay vernier and a method of forming the overlay vernier which can be effectively applied to the overlay reading of a double patterned layer and another layer formed thereon during double patterning. It is about.

As semiconductor devices become highly integrated, the pitch between patterns in the mask decreases. However, due to the limitation of the resolution, there is a limit of the pitch that can be realized to a minimum, and in order to overcome the limitation of the resolution, a multiple exposure method has been studied.

1A and 1B are plan views illustrating an exposure mask for a conventional overlay vernier according to the prior art, and illustrate an exposure mask for forming an overlay vernier in the form of a box in box. FIG. 1A is a plan view illustrating a parent vernier exposure mask 100, and the parent vernier exposure mask 100 is formed to include a first light blocking pattern 110 having a rectangular shape having a line width of a predetermined thickness. FIG. 1B is a plan view illustrating the exposure mask 150 for the child vernier, and the exposure mask 150 for the child vernier is formed in a box shape inside the first light shielding pattern 110 provided in the exposure mask 100 for the parent vernier. It is formed to include the second light blocking pattern 160.

2A and 2B are cross-sectional views illustrating a general overlay vernier forming method of a semiconductor device using an exposure mask according to the prior art.

Referring to FIG. 2A, an etched layer 210 and a first mask layer (not shown) are formed on the semiconductor substrate 200, and the parent vernier exposure mask (100 in FIG. 1A) illustrated in FIG. 1A is used. The first mask layer (not shown) is patterned by a photolithography process to form a first mask layer pattern (not shown). Next, the etched layer 210 is etched using the first mask layer pattern (not shown) as a mask to form a trench 215 defining a parent vernier.

Referring to FIG. 2B, after the intermediate layer 220 is formed on the entire semiconductor substrate 200 including the trench 215, a photoresist film (not shown) is formed on the intermediate layer 220, and FIG. An exposure and development process is performed using the illustrated exposure mask for the child vernier (150 in FIG. 1B) to form a second mask layer pattern 230 defining the child vernier.

Meanwhile, in the process of applying the conventional double patterning, a separate overlay vernier for double patterning was required regardless of the total integration to measure the overlap between the exposure mask for the parent vernier and the exposure mask for the child vernier. . Therefore, since more than one vernier is additionally required for each layer to which double patterning is applied, the specific gravity of the vernier region occupying in the scrape lane becomes large. In addition, in order to overlay reading between the layer on which the double patterning is formed and the other layer, an overlay vernier with another layer is separately added at the position of the exposure mask for the parent vernier or the exposure mask for the child vernier during the double patterning, in which case the parent vernier Since the vernier for the other layer is formed only on one of the exposure mask for the self or the vernier exposure mask, the overlay reading with the other layer is also performed with only one of these masks. As a result, the mask process that proceeds to the double patterning does not overlap with other layers uniformly, and the overlapping is better because only one of the masks on which the vernier is formed is exposed among the parent vernier exposure mask or the self vernier exposure mask. In this case, it may not be a problem if only one step is applied, but may act as an overlay problem as the accumulation is accumulated step by step. That is, as the highly integrated device is developed, the size of the pattern is reduced, and accordingly, overlay control is required as several nm, and thus, there is a problem that it is difficult to control the overlay which becomes weak by the conventional double patterning overlay reading method. .

The present invention has been made to improve the problems of the conventional overlay vernier and the formation method as described above, not only separately forming the overlay vernier formed in the double patterning application in different areas of the scribing lane, but also in different layers It is an object of the present invention to provide an overlay vernier and a method of forming the same, which can perform overlap control evenly without biasing only one mask even when overlapping with the formed vernier.

In order to achieve the above object, the present invention

Strip-shaped first parent vernier;

A band-shaped second mother vernier formed inside the first mother vernier; And

It provides an overlay vernier including a box-shaped ruler vernier is formed inside the second vernier.

In the above, preferably an intermediate layer is formed between the first mother vernier and the second mother vernier and the second mother vernier and the child vernier.

In addition, the present invention

Forming an etched layer and a first mask layer on the semiconductor substrate, and then patterning the first mask layer to form a band-shaped first vernier pattern;

After forming a second mask layer on the first parent vernier pattern, patterning the second mask layer to form a band-shaped second vernier pattern formed inside the first parent vernier pattern; And

Forming a third mask layer on the second mother vernier pattern, patterning the third mask layer to form a box-shaped ruler vernier pattern formed inside the second mother vernier pattern to form an overlay vernier Provide a method.

The etching target layer may be any one selected from an amorphous carbon layer, a silicon oxynitride layer, and a combination thereof. The first mask layer and the second mask layer may be hard masks provided on the conductive wiring. The layer is preferably a photosensitive film, but is not necessarily limited thereto.

According to one embodiment of the present invention, the first parent vernier pattern and the second parent vernier pattern formed when applying double patterning are not formed in separate regions of the scribing lane, but the vernier of another layer formed thereon. It is formed in the area where the pattern is located. That is, after forming the first parent vernier pattern of double patterning at the vernier position where the layer to which the double patterning is applied is to be formed when applying the single patterning, and forming the second parent vernier pattern therein, the second mother A ruler vernier pattern is formed inside the vernier pattern to overlap the layer formed thereon. This eliminates the need for conventional vernier regions that were formed separately in the scribe lanes for the purpose of controlling the overlay of double patterning. In addition, the first and the second and second parent vernier patterns are located at the same position as the first and second parent vernier patterns, instead of only one mask formed when the double patterning is applied. Since two parent vernier patterns and child vernier patterns can be read at the same time, even when double patterning is applied, overlay control can be performed evenly without biasing only one mask.

Meanwhile, according to another embodiment of the present invention, the vernier formed for double patterning may be the first parent vernier and the child vernier, and the vernier for the other layer formed thereon may be the second parent vernier. That is, the technical feature of the present invention is that the three vernier as described above are formed together in the same area of the subscription lane.

The overlay vernier of the present invention and the method for forming the same do not respectively form overlay verniers formed when applying double patterning to different regions of the scribing lanes, but overlap the vernier regions that should be formed when the layer is applied with single patterning. This eliminates the need to add a vernier to the scribing lane, which is added only for overlay control during double patterning, and evenly controls overlap evenly without applying bias to only one mask when double patterning is applied. The advantage is that it can be applied not only to DRAM, but also to all processes and technologies that apply dual patterning in the future.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3D illustrate one embodiment of a method of forming an overlay vernier of the present invention. After performing exposure and development processes using a first mask for exposing the first vernier (Figures 3a and 300) in a predetermined region of the scribing lane where double patterning is performed, a band-shaped first vernier pattern is formed, and then the first vernier The stripe-shaped second vernier pattern is formed by performing exposure and development processes using the second parent vernier exposure masks (FIGS. 3B and 310) inside the pattern. In this case, an intermediate layer is formed between the first parent vernier pattern and the second parent vernier pattern. Thereafter, a box-shaped ruler vernier pattern formed on the layer on which the double patterning is formed is formed inside the second parent vernier pattern by an exposure and development process using an exposure mask (FIGS. 3C and 320) for the ruler. In this case, an intermediate layer (not shown) is formed between the second mother vernier pattern and the child vernier pattern. The overlapped form of the finally formed overlay vernier is shown in FIG. 3D. In the exposure process, the exposure light source is preferably performed using any one selected from I-Line, KrF, ArF, ArFi, or EUV, and the exposure illumination system is conventional, annular, quadropole. It is preferable to perform using any one selected from Quadrupole, Dipole, and a combination thereof, but is not necessarily limited thereto.

4A to 4D illustrate another embodiment of a method of forming an overlay vernier of the present invention. After the exposure and development processes using the first mask of the first vernier exposure mask (FIGS. 4A and 400) are performed on a predetermined region of the scribing lane where the double patterning is performed, a band-shaped first vernier pattern is formed, and then the first vernier A box-shaped ruler vernier pattern is formed on the inside of the pattern by using the exposure masks for ruler vernier (FIGS. 4B and 410). In this case, an intermediate layer is formed between the first mother vernier pattern and the child vernier pattern. Subsequently, a strip-shaped second vernier pattern formed on the layer on which the double patterning is formed is formed on the outside of the first vernier pattern by an exposure and development process using exposure masks for FIGS. 4C and 420. In this case, an intermediate layer is formed between the first parent vernier pattern and the second parent vernier pattern. The overlapped form of the finally formed overlay vernier is shown in FIG. 4D. In the exposure process, the exposure light source is preferably performed using any one selected from I-Line, KrF, ArF, ArFi, or EUV, and the exposure illumination system is conventional, annular, quadropole, dipole, and a combination thereof. It is preferable to perform using any one selected from, but is not necessarily limited thereto.

1A and 1B are plan views illustrating an exposure mask for an overlay vernier according to the prior art.

2A and 2B are cross-sectional views illustrating an overlay vernier forming method showing an exposure mask according to the prior art.

3A and 3D are plan views illustrating an example of an exposure mask for overlay vernier according to the present invention.

4A and 4D are plan views showing another example of an exposure mask for overlay vernier according to the present invention.

<Description of the symbols for the main parts of the drawings>

100,300,400: exposure mask for the first mother vernier,

310,420: exposure mask for the second parent vernier,

150,320,410: Exposure mask for ruler vernier,

110: first shading pattern, 160: second shading pattern

200: semiconductor substrate, 210: etched layer

215: trench, 220: middle layer

Claims (6)

Strip-shaped first parent vernier; A band-shaped second mother vernier formed inside the first mother vernier; And An overlay vernier comprising a box-shaped ruler vernier formed inside the second vernier. The method according to claim 1, Overlay vernier, characterized in that the intermediate layer is formed between the first mother vernier and the second mother vernier and the second mother vernier and the child vernier. Forming an etched layer and a first mask layer on the semiconductor substrate, and then patterning the first mask layer to form a band-shaped first vernier pattern; After forming a second mask layer on the first parent vernier pattern, patterning the second mask layer to form a band-shaped second vernier pattern formed inside the first parent vernier pattern; And Forming a third mask layer on the second mother vernier pattern, patterning the third mask layer to form a box-shaped ruler vernier pattern formed inside the second mother vernier pattern to form an overlay vernier Way. The method according to claim 3, The etched layer may be any one selected from an amorphous carbon layer, a silicon oxynitride film, and a combination thereof. The method according to claim 3, The first mask layer and the second mask layer is a method of forming an overlay vernier, characterized in that the hard mask provided on the upper side of the conductive wiring. The method according to claim 3, And the third mask layer is a photosensitive film.
KR1020070110726A 2007-10-31 2007-10-31 Overlay vernier and method of forming the same KR20090044586A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070110726A KR20090044586A (en) 2007-10-31 2007-10-31 Overlay vernier and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070110726A KR20090044586A (en) 2007-10-31 2007-10-31 Overlay vernier and method of forming the same

Publications (1)

Publication Number Publication Date
KR20090044586A true KR20090044586A (en) 2009-05-07

Family

ID=40855128

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070110726A KR20090044586A (en) 2007-10-31 2007-10-31 Overlay vernier and method of forming the same

Country Status (1)

Country Link
KR (1) KR20090044586A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8906584B2 (en) 2012-08-31 2014-12-09 SK Hynix Inc. Photomask and method for forming pattern of semiconductor device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8906584B2 (en) 2012-08-31 2014-12-09 SK Hynix Inc. Photomask and method for forming pattern of semiconductor device using the same

Similar Documents

Publication Publication Date Title
US7776750B2 (en) Semiconductor device and method for forming a pattern in the same with double exposure technology
KR100843870B1 (en) Method for manufacturing fine pattern of a semiconductor device
KR20190013409A (en) Multiple-mask multiple-exposure lithography and masks
JP2007081403A (en) Method of forming fine pattern in semiconductor element
US20080014684A1 (en) Two-print-two-etch method for enhancement of CD control using ghost poly
KR101154007B1 (en) Method for fabricating fine pattern
US20040248016A1 (en) Method of designing a reticle and forming a semiconductor device therewith
KR20120126442A (en) Method for forming pattern of Semiconductor Device
US8003301B2 (en) Manufacturing method for semiconductor device
JP2001235850A (en) Method for designing photomask pattern, method for forming resist pattern and method for manufacturing semiconductor device
US7939225B2 (en) Mask for controlling line end shortening and corner rounding arising from proximity effects
US7945869B2 (en) Mask and method for patterning a semiconductor wafer
US20140220482A1 (en) Method for forming patterns
US20120135341A1 (en) Method for double patterning lithography and photomask layout
KR101051177B1 (en) Pattern Forming Method of Semiconductor Device Using Double Exposure
US8778604B2 (en) Mask set for double exposure process and method of using the mask set
KR101616744B1 (en) Photomask, method of exposing a substrate to light, method of forming a pattern, and method of manufacturing a semiconductor device
KR20090044586A (en) Overlay vernier and method of forming the same
KR101159689B1 (en) Method for forming overlay vernier in semiconductor device
US20070281218A1 (en) Dummy Phase Shapes To Reduce Sensitivity Of Critical Gates To Regions Of High Pattern Density
KR100801738B1 (en) Photo mask and the method for fabricating the same
US6767672B2 (en) Method for forming a phase-shifting mask for semiconductor device manufacture
KR101096191B1 (en) Method for forming contact hole
WO2009125529A1 (en) Method of generating mask pattern and method of forming pattern
KR100915064B1 (en) Overlay vernier and method for forming the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination