KR101095041B1 - Method for forming the fine pattern of semiconductor devices - Google Patents

Abstract

The present invention relates to a method of forming a fine pattern of a semiconductor device, and sequentially forming a first insulating film and a second insulating film on an upper surface of a semiconductor substrate on which an etched layer is formed, and forming a trench-shaped first photoresist film pattern. A spacer is formed on the photoresist pattern sidewalls, the first photoresist pattern is removed, a second insulation film pattern is formed using the spacer as a mask, a second photoresist film pattern is formed on the second insulation film pattern, and then the second photoresist film is formed. A first insulating film pattern is formed by using the pattern, the spacer, and the second insulating film pattern as a mask, a structure on the first insulating film pattern is removed, and a third photoresist film pattern is formed on the first insulating film pattern. 3 is provided by providing a configuration including a step of etching the first insulating film pattern of the dummy pattern region using the photosensitive film pattern as a mask It is possible to essentially improve the lithography process margins without information, in the section where the pitch (Pitch) a technique for changing to form a photosensitive pattern vertical.

Fine Pattern, Uniformity, Depth of Focus

Description

METHOD FOR FORMING THE FINE PATTERN OF SEMICONDUCTOR DEVICES

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a technique for improving the uniformity and depth of focus of a pattern at a boundary region of a cell portion.

The most important elements in forming a semiconductor device include a deposition process and an etch process, and among these, as the degree of integration of semiconductor devices increases, the importance of the etching process increases.

In particular, the patterning process in the etching process may be a process directly affecting the increase in the integration degree of the semiconductor device, and the yield and reliability of the semiconductor device may vary depending on the patterning process. This will be described below with an example.

For example, a process of forming a plurality of metal wires included in a semiconductor device will be described. An insulating film for electrically isolating metal wires is formed on a semiconductor substrate. In order to pattern the insulating film, a hard mask pattern is formed on the insulating film, and the hard mask pattern may be formed by performing an etching process according to the photoresist pattern. In particular, the photoresist pattern is formed by performing an exposure and development process, and the width of the pattern is mainly determined by the exposure process performed at this time.

The resolution R of the exposure process may be a major factor in determining the width of the pattern, and the resolution R may be expressed by Equation 1 below.

Referring to Equation 1, 'R' is the resolution, and 'Ki' is a coherence factor, and generally has a value of 0.5 to 0.8. 'λ' is the wavelength of the light source used in the exposure process, and 'NA' represents the lens numerical aperture of the exposure equipment.

Among these, since the process capability variable Ki is very difficult to be arbitrarily adjusted in the manufacturing process, it is preferable to adjust the resolution by lowering the wavelength? Of the light source or increasing the lens numerical aperture NA.

On the other hand, in order to change the light source or lens numerical aperture as described above, the replacement of the exposure equipment must be made, but this requires expensive equipment and manufacturing cost.

In recent years, fine patterns of semiconductor devices have been formed using hard masks and organic antireflection films.

 1A to 1C are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.

Referring to FIG. 1A, an etched layer 10 is formed on a semiconductor substrate (not shown), and a first hard mask layer 12, a second hard mask layer 14, an anti-reflection film 16, and a photoresist film are formed on the etched layer 10. The pattern 18 is formed. Here, the first and second hard mask layers 12 and 14 are formed of a nitride film, an oxide film, or a nitride oxide film.

At this time, the photoresist pattern 18 is formed by an exposure and development process using an exposure mask for coating a photoresist on the anti-reflection film 16 and forming a fine pattern.

The antireflection film 16 is formed of an organic film.

Referring to FIG. 1B, the antireflection film 16 is etched using the photoresist pattern 18 as a mask to expose the second hard mask layer 14.

Subsequently, the second hard mask layer 14 pattern is formed by etching the second hard mask layer 14 using the remaining photoresist pattern 18 and the anti-reflection film 16 as a mask.

At this time, the material existing on the upper portion of the etching material acts as a mask and is simultaneously etched during the etching of the lower layer, and the anti-etching film (on the second hard mask layer 14 pattern of FIG. 16) and the photosensitive film pattern 18 remain. Of course, the etching process is performed by a wet or dry method using the difference in the etching selectivity between the layers. Here, the remaining portion of the anti-reflection film 16 and the photoresist pattern 18 is removed using the difference in etching selectivity with other structures.

Referring to FIG. 1C, a pattern of the first hard mask layer 12 exposing the etched layer 10 by etching the exposed first hard mask layer 12 using the second hard mask layer 14 pattern as a mask. To form.

At this time, the second hard mask layer 14 pattern is removed during the etching process of the first hard mask layer 12, but the remaining part is removed using the difference in etching selectivity with other structures.

Although not shown, a fine pattern is formed by etching the etched layer 10 using the first hard mask layer 12 pattern as a mask in a subsequent process.

At this time, the first hard mask layer 12 pattern is removed in the same manner as removing the second hard mask layer 14 pattern.

As described above, the method for forming a fine pattern of a semiconductor device according to the prior art has the following problems.

1. In order to form the hard mask layer, the number of layers of the hard mask layer must be accompanied by the CVD forming process.

2. Use anti-reflection film to increase the resolution of fine pattern.

3. Increased cost of using the above structure

4. Developing process of lithography to pattern the photoresist to the limit line width.

5. Contamination increases due to particle generation following 1-4 process.

Recently, in order to solve this problem and to form a fine pattern according to the high integration of the semiconductor device, SPT (Spacer Patterning Technology) process is used.

In the SPT process, since the pitch of the pattern is too small to be directly patterned by the exposure machine, one partition patterning per two pitches is used to form two line patterns in one line by forming spacers using the same. Technology.

However, in the dark tone mask of FIG. 2A, the most edge line pattern having a pitch change is most vulnerable to process margin. In particular, the edge pattern of the clear tone mask shown in FIG. 2B is impossible to define a CD largely because the CD target is the same as a cell, and an area without the pattern is opened to flare. Very vulnerable to flare noise. If the flare noise is affected, CD uniformity is degraded by affecting not only the most edge pattern but also the CD of the inner line pattern.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a fine pattern of a semiconductor device, which can improve the uniformity and depth of focus of a pattern at a boundary region of a cell part.

Method for forming a fine pattern of a semiconductor device according to the present invention,

Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate on which the etched layer is formed;

Forming a trench-shaped first photoresist pattern;

Forming a spacer on sidewalls of the first photoresist pattern;

Removing the first photoresist pattern;

Forming a second insulating film pattern using the spacer as a mask;

Forming a second photoresist pattern on the second insulation pattern;

Forming a first insulating film pattern using the second photosensitive film pattern, the spacer and the second insulating film pattern as a mask;

Removing the structure above the first insulating layer pattern;

Forming a third photoresist pattern on the first insulation pattern;

Etching the first insulating film pattern in the dummy pattern region using the third photoresist pattern as a mask;

The first insulating film is formed of a TEOS oxide film,

The second insulating film is formed of SiON,

The spacer is formed of ULTO,

The second photoresist pattern is formed at a boundary between an actual pattern region and a dummy pattern region, the second photoresist pattern is formed using a pad mask,

The third photoresist pattern may be performed using a cutting mask for patterning a region where a spacer is formed into an active region,

And patterning the etched layer using the first insulating film pattern as a mask.

A method of forming a fine pattern of a semiconductor device according to the present invention is as follows.

1. It can fundamentally improve the lithography process margin in select transistor regions.

2. Real cell pattern insertion eliminates flare noise.

3. It is possible to form a vertical photoresist pattern in a section where pitch is changed.

4. Dark tone mask, clear tone mask, negative photoresist and positive photoresist can be applied.

5. No further process is required for existing processes.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, the polysilicon layer 11 is formed on the semiconductor substrate.

Next, a first insulating layer 13, for example, a TEOS oxide layer, is formed on the polysilicon layer 11 as an etched layer.

A second insulating film 15, for example, a silicon oxynitride film, is formed on the first insulating film 13.

Next, a first photoresist layer pattern 17 having a trench shape is formed on the second insulation layer 15.

In this case, the first photoresist pattern 17 is formed according to a cell layout diagram for forming a spacer.

Referring to FIG. 3B, spacers 19 are formed on sidewalls of the first photoresist pattern 17.

In this case, the spacer 19 is formed by forming an ultra low temperature oxide on the entire surface and anisotropically etching it.

Referring to FIG. 3C, the first photoresist layer pattern 17 is removed to form a hard mask layer as a spacer 19 on the second insulating layer 15.

Referring to FIG. 3D, the second photosensitive film pattern 21 is formed on the entire surface by a lithography process using a pad mask.

In this case, the second photoresist layer pattern 21 is formed between the actual pattern region 100 and the dummy pattern region 200 in the form of a pad for forming the selective transistor region 300.

Here, the optional transistor region 300 is a pattern formed at the boundary between the actual pattern and the dummy pattern.

Referring to FIG. 3E, the first insulating film 13 is etched using the second photoresist film pattern 21 and the spacer 19 as a mask to form the first insulating film 13 pattern.

Next, the second photosensitive film pattern 21 and the spacer 19 are removed. In this case, the polysilicon layer 11 is exposed under the first insulating layer 13 pattern.

Referring to FIG. 3F, a third photosensitive film pattern 23 is formed on the entire surface.

In this case, the third photoresist layer pattern 23 is formed in a pattern form that exposes the dummy pattern region 200.

Referring to FIG. 3G, the first insulating layer 13 pattern exposed to the dummy pattern region 200 is removed using the third photoresist pattern 23 as a mask.

Then, the third photosensitive film pattern is removed.

Although not shown, the patterning process is completed by using the first insulating film 13 pattern remaining in the actual pattern region 100 and the optional transistor region 300 as a hard mask layer in a subsequent process.

According to another embodiment of the present invention, the insulating film structure used as the hard mask layer may include an antireflection film, a silicon oxynitride film (SiON), an oxide film, a nitride film, an amorphous carbon layer (ACL), a polysilicon layer, and a teos (TEOS), spin on carbon (SOC), and one of these laminated structures.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are as follows It should be regarded as belonging to the claims.

1A to 1C are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art.

2A and 2B are photographs showing problems of the prior art.

3A to 3G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to an embodiment of the present invention.

Claims (7)

Sequentially forming a first insulating film and a second insulating film on the semiconductor substrate on which the etched layer is formed; Forming a trench-shaped first photoresist pattern on the second insulating layer; Forming a spacer on sidewalls of the first photoresist pattern; Removing the first photoresist pattern; Forming a second insulating film pattern using the spacer as a mask; Forming a second photoresist pattern on the second insulation pattern; Forming a first insulating film pattern using the second photosensitive film pattern, the spacer and the second insulating film pattern as a mask; Removing the structure above the first insulating layer pattern; Forming a third photoresist pattern on the first insulation pattern; And etching the first insulating film pattern in the dummy pattern region using the third photoresist pattern as a mask. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, And the first insulating film is formed of a TEOS oxide film. Claim 3 was abandoned when the setup registration fee was paid. And the second insulating film is formed of SiON. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The spacer is a fine pattern forming method of a semiconductor device, characterized in that formed by ULTO. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the second photoresist pattern is formed at the boundary between the actual pattern region and the dummy pattern region. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, The second photosensitive film pattern is a fine pattern forming method of a semiconductor device, characterized in that formed using a pad mask. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, And patterning the etched layer using the first insulating film pattern as a mask.

Images