KR20120129084A - Method for Manufacturing Semiconductor Device - Google Patents

Method for Manufacturing Semiconductor Device Download PDF

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Publication number
KR20120129084A
KR20120129084A KR1020110047131A KR20110047131A KR20120129084A KR 20120129084 A KR20120129084 A KR 20120129084A KR 1020110047131 A KR1020110047131 A KR 1020110047131A KR 20110047131 A KR20110047131 A KR 20110047131A KR 20120129084 A KR20120129084 A KR 20120129084A
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KR
South Korea
Prior art keywords
etching
contact hole
mask
exposed
forming
Prior art date
Application number
KR1020110047131A
Other languages
Korean (ko)
Inventor
이동진
Original Assignee
에스케이하이닉스 주식회사
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110047131A priority Critical patent/KR20120129084A/en
Publication of KR20120129084A publication Critical patent/KR20120129084A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

According to the present invention, after forming a plurality of contact holes by primary etching with a contact hole forming mask, secondary etching is performed on the lower part of the exposed contact hole using a blocking layer, and the second etching is performed by expanding the blocking layer. By partially blocking the hole and terminating the lower portion of the contact hole exposed from the blocking layer so as to be connected to a desired semiconductor device, when forming a plurality of contact holes having different etching depths, the contact is made to have a desired depth without using a plurality of masks. The present invention provides a method for fabricating a semiconductor device that can reduce the number of mask fabrication costs and reduce the number of exposures and processing steps by forming holes.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simplifying a process when connecting a contact hole and a semiconductor device.

As the recent development of semiconductor device manufacturing technology and the application field of memory devices have been expanded, there is an urgent need to develop a technology for manufacturing a large-capacity memory device in which integration degree is improved and electrical characteristics are not degraded. Accordingly, various studies have been conducted to improve photo-lithography processes or to obtain stable process conditions by overcoming limitations such as cell structures, wiring forming materials, and insulating film forming materials. Among these, the photolithography process is an essential technology applied to the contact forming process or the pattern forming process for connecting the various layers constituting the device to each other, and the improvement of the photolithography process technology determines the success or failure of the highly integrated semiconductor device. Becomes

The photolithography process uses a principle of changing a property by causing a chemical reaction when a specific chemical (photo resist) receives light.However, by using a mask of a desired pattern, a photoresist is selectively injected to the light to mask the pattern of the mask. It is a process of forming in the same pattern as. The photolithography process is a coating process for applying a photoresist corresponding to a film of a general photograph, an exposure process for selectively scanning light using a mask, and a photoresist for removing a portion of the lighted portion using a developer to form a pattern. It consists of a developing process.

The photolithography process currently commercialized uses exposure equipment using short wavelength light sources such as KrF and ArF, and the resolution of the pattern obtained from such short wavelength light sources is limited to about 0.1 μm. Thus, it is very difficult to fabricate highly integrated semiconductor devices of smaller sized patterns.

In particular, a resist flow process using heat has been performed to reduce the size of a contact hole pattern, which is one of fine patterns included in a semiconductor device, using a conventional technology. However, in the resist flow process, even if the same energy is delivered to the front surface of the photoresist at a temperature higher than the glass transition temperature, the upper part of the pattern spreads more than the lower part because the photoresist flows relatively higher than the upper and middle parts of the photoresist. There is a problem that overflow occurs.

As described above, the technology for reducing the size of the contact hole pattern is not yet complete. In addition, the development of the technology of the exposure equipment has also reached a limit point, the situation of technology development is delayed. In the case where fine patterns of non-uniform size are formed on the semiconductor substrate, the measurement accuracy of the critical dimension (CD) is reduced, thereby not only obtaining sufficient etching margin for performing a stable subsequent etching process, but also yielding final semiconductor device yield. This decreasing phenomenon occurs.

In the above-described method of manufacturing a semiconductor device, as the design rules of the DRAM device become smaller, defects in the contact hole or contact plug area, which are reduced in forming the contact hole or contact plug, are continuously generated. When forming contact plugs or wirings connected to the gates and gates of the peripheral circuit area, a plurality of masks are used according to the height or depth to be etched, and each contact plug or Because of the connection between the wiring and the lower layer (embedded gate, vertical gate and gate of the peripheral circuit region, etc.), there are many problems in terms of manufacturing process steps and cost.

In order to solve the above-mentioned conventional problems, the present invention forms a plurality of contact holes by primary etching with a contact hole forming mask, and then secondly etches the lower part of the exposed contact hole using a blocking layer. By extending the blocking layer to partially block the secondly etched contact hole and by terminating the lower portion of the contact hole exposed from the blocking layer so as to be connected to a desired semiconductor device, a plurality of contact holes having different etching depths are formed. The present invention provides a method of manufacturing a semiconductor device capable of reducing the cost of manufacturing a plurality of masks and reducing the number of exposures and processing steps by forming contact holes to a desired depth without using two masks.

The present invention provides a method of forming an insulating film on a semiconductor substrate including a cell region and a peripheral circuit region, forming first, second and third contact holes by first etching the insulating film, and forming the third contact hole. Second etching the insulating layer using a light shielding mask to etch deeper the lower portions of the exposed first and second contact holes, and to adjust the size of the mask to shield the second and third contact holes. And deeply etching a lower portion of the first contact hole exposed by the etch mask with the scaled mask.

Preferably, when the first, second and third contact holes are formed, the contact hole forming mask may be one immersion mask.

Preferably, the mask for shielding the third contact hole is an I-line mask.

Preferably, the method of controlling the size of the mask is characterized in that using a relax process, a reflow process or a sapphire process.

Preferably, when forming the first, second and third contact holes by first etching the insulating film, etching the insulating film until the gate electrode layer of the gate pattern of the peripheral circuit region is exposed. It features.

Preferably, when etching the lower portions of the exposed first and second contact holes deeper, etching the lower portions of the first and second contact holes until the vertical gate of the cell region is exposed. It features.

Preferably, when etching the lower portion of the first contact hole deeper, etching the lower portion of the first contact hole until the buried bit line of the cell region is exposed.

According to the present invention, after forming a plurality of contact holes by primary etching with a contact hole forming mask, secondary etching is performed on the lower part of the exposed contact hole using a blocking layer, and the second etching is performed by expanding the blocking layer. By partially blocking the hole and terminating the lower portion of the contact hole exposed from the blocking layer so as to be connected to a desired semiconductor device, when forming a plurality of contact holes having different etching depths, the contact is made to have a desired depth without using a plurality of masks. The formation of holes has the advantage of reducing the cost of manufacturing a plurality of masks and reducing the number of exposures and process steps.

1A to 1C illustrate a method of manufacturing a semiconductor device in accordance with the present invention.
2 and 3 are masks showing a method of manufacturing a semiconductor device according to the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween. Also, the same reference numerals throughout the specification represent the same components.

1A to 1C are diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, an isolation layer 120 defining an active region 110 is formed on a semiconductor substrate having a cell region 1000a and a peripheral circuit region 1000b.

Next, buried bitlines 130 and vertical gates 140 are formed in the active region 110 and the device isolation layer 120. Here, since the manufacturing process for forming the buried bit line 130 and the vertical gate 140 is formed by a general process, it is omitted here. Thereafter, the gate pattern 150 is formed on the active region 110 of the peripheral circuit region 1000b. The gate pattern 150 is preferably a general planar gate pattern formed in the peripheral circuit region 1000b.

Next, an insulating layer 160 is formed on the active region 110 and the device isolation layer 120. In this case, the insulating layer 160 may be formed in a stacked structure of a BPSG (Borophospho Silicate Glass) film and a TEOS (Tetraethly Orthosilicate) film.

Next, a plurality of contact holes 170, 180, and 190 are formed by first etching the insulating layer 160 using the contact hole forming mask.

For example, as illustrated in FIG. 1A, the gates of the first contact hole A, the second contact hole B, and the peripheral circuit region 1000b of the cell region 1000a are formed using a contact hole forming mask. A plurality of contact holes are defined including a third contact hole C connected to the pattern 150. That is, when the insulating layer 160 using the contact hole forming mask is first etched to form a plurality of contact holes, the first etching is performed until the gate electrode layer of the gate pattern 150 of the peripheral circuit region 1000b is exposed. It is preferable. Here, the contact hole forming mask is to form a plurality of contact holes using one mask, it is preferable to use an immersion mask.

Referring to FIG. 1B, the lower portions of the exposed first contact hole A and the second contact hole B are second-etched using a blocking layer blocking the third contact hole C (FIG. In this case, it is preferable to use an I-line mask as the blocking layer. Here, it is preferable to perform secondary etching on the lower portion of the second contact hole B until the buried gate 140 is exposed using the secondary etching process.

Referring to FIG. 1C, the blocking layer 200 is used again, but the blocking layer 200 extends to block the second contact hole B, and then the lower portion of the first contact hole A is exposed. 3rd etching (see 200 'of FIG. 3)

Here, it is preferable to etch the lower portion of the first contact hole A using the tertiary etching process until the buried bit line 130 is exposed.

In this case, the process of expanding 200 ′ so that the blocking layer 200 may block the second contact hole B may be a relaxation process, a reflow process, or a sapphire film (Shrink Assist Film for Enhanced Resolution, Safier). It is preferable to use a process and the like.

The Relax process is applied to a relax (RELACS) material (not shown) 1000 ~ 2000Å, and performs a baking process that is heated for about 60 to 100 seconds at a temperature of 110 ~ 190 ℃. When the baking process is performed, a crosslinking reaction occurs between the photoresist pattern and the RELACS layer to form a crosslinking layer (not shown). Then, the DI rinse process washes away impurities and chemicals on the surface of the pattern, so that the RELACS material is water-soluble, so that the RELACS layer without crosslinking reaction is removed, thereby reducing the trench line width between the photoresist patterns. It is a method for implementing a micro process in which a photoresist pattern having a trench line width is formed.

The reflow process is a method of implementing a micro process by reducing the space between the photoresist and the photoresist by flowing the photoresist using a heat process after applying the photoresist.

As described above, according to the present invention, after forming a plurality of contact holes by first etching with a contact hole forming mask, the lower part of the exposed contact hole is secondly etched using a blocking layer, and the blocking film is expanded. By partially blocking the secondly etched contact hole and terminating the lower portion of the contact hole exposed from the blocking layer so as to be connected to a desired semiconductor device, a plurality of masks are not used when forming a plurality of contact holes having different etching depths. By forming a contact hole to a desired depth without the advantage of reducing the number of mask manufacturing costs, the number of exposures and the process step can be reduced.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (7)

Forming an insulating film on a semiconductor substrate having a cell region and a peripheral circuit region;
First etching the insulating film to form first, second and third contact holes;
Second etching the insulating layer using a mask for blocking the third contact hole to etch deeper the lower portions of the exposed first and second contact holes;
Adjusting the size of the mask to shield the second contact hole and the third contact hole; And
Etching deeper the lower portion of the first contact hole exposed by the sized mask as an etch mask
And forming a second insulating film on the semiconductor substrate. The method according to claim 1,
The method for manufacturing a semiconductor device according to claim 1, wherein the contact hole forming mask is an immersion mask when the first, second and third contact holes are formed. The method according to claim 1,
The mask for shielding the third contact hole is an I-line mask manufacturing method of a semiconductor device. The method according to claim 1,
The method of adjusting the size of the mask is a manufacturing method of a semiconductor device, characterized in that using a relax process, a reflow process or a sapphire process. The method according to claim 1,
Etching the insulating film to form first, second and third contact holes by first etching the insulating film until the gate electrode layer of the gate pattern of the peripheral circuit region is exposed. Method of manufacturing the device. The method according to claim 1,
Etching the lower portions of the exposed first and second contact holes deeper, etching the lower portions of the first and second contact holes until the vertical gate of the cell region is exposed. Method of manufacturing the device. The method of claim 1,
Etching the bottom of the first contact hole more deeply, etching the bottom of the first contact hole until the buried bit line of the cell region is exposed.
KR1020110047131A 2011-05-19 2011-05-19 Method for Manufacturing Semiconductor Device KR20120129084A (en)

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KR1020110047131A KR20120129084A (en) 2011-05-19 2011-05-19 Method for Manufacturing Semiconductor Device

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KR1020110047131A KR20120129084A (en) 2011-05-19 2011-05-19 Method for Manufacturing Semiconductor Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688687B2 (en) 2020-07-29 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor devices having landing pad patterns and methods of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688687B2 (en) 2020-07-29 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor devices having landing pad patterns and methods of manufacturing the same

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