KR20090106294A - vertical structured group 3 nitride-based light emitting diode and its fabrication methods - Google Patents

Abstract

PURPOSE: A group III nitride based semiconductor light emitting diode having a vertical structure and a manufacturing method thereof are provided to separate a light emitting structure for a light emitting diode from a growth substrate without thermal and mechanical damage. CONSTITUTION: A group III nitride based semiconductor light emitting diode having a vertical structure includes an n-type ohmic contact electrode structure(406), a light emitting structure(402), a p-type ohmic contact electrode layer, a first device passivation layer, a reflective ohmic contact electrode layer, a conductive wafer bonding layer, a second device passivation layer, a heat sink supporting bar(403), a p-type ohmic contact electrode structure, and a die bonding layer. The light emitting structure comprises an n-type nitride based clad layer, a nitride based active layer, and a p-type nitride based clad layer. The p-type ohmic contact electrode layer and the first device passivation layer include a current blocking region formed in a bottom surface of the light emitting structure. The reflective ohmic contact electrode layer is formed in a bottom surface of the p-type ohmic contact electrode layer and the first device passivation layer. The conductive wafer bonding layer is formed in a bottom surface of the reflective ohmic contact electrode layer. The second device passivation layer surrounds the light emitting structure, the p-type ohmic contact electrode layer, the first device passivation layer, the reflective ohmic contact electrode layer, and the conductive wafer bonding layer. The heat sink supporting bar is formed in a bottom surface of the conductive wafer bonding layer, and has a laminate structure. The p-type ohmic contact electrode structure and the die bonding layer are formed in a bottom surface of the heat sink supporting bar of the laminate structure.

Description

Vertical structured group 3 nitride-based semiconductor light emitting diode device and method of manufacturing the same {vertical structured group 3 nitride-based light emitting diode and its fabrication methods}

According to an embodiment of the present invention, an n-type ohmic contact electrode structure and a p-type ohmic contact electrode structure are positioned to face up and down around a light emitting structure composed of a group III nitride semiconductor, and the heat sink support of the light emitting structure and the laminate structure is at least 300 ° C. Provided are a next-generation vertical group III-nitride semiconductor light emitting diode device manufactured using a conductive wafer bonding layer bonded at the above temperature, and a method of manufacturing the same.

Light emitting devices such as light emitting diodes (LEDs) and laser diodes (LDs) are solid-state semiconductor devices that generate light by flowing a current in a forward direction to a p-n coupling. In particular, light emitting diode devices using solid semiconductors have high efficiency for converting electrical energy into light energy, have a long lifespan of more than 5 to 10 years, and can greatly reduce power consumption and maintenance costs. It is attracting attention in the field.

In general, group III-nitride semiconductor light emitting diode devices grow on top of a transparent sapphire growth substrate, but the sapphire growth substrate is hard, electrically insulating, and does not have excellent thermal conductivity. There is a limit in reducing the manufacturing cost by reducing the size, or improve the characteristics of the unit chip, such as light extraction efficiency, or electrostatic discharge (hereinafter referred to as "ESD"). In other words, since the sapphire growth substrate is an electrical insulator, there is a big limitation in the structure of the group III-nitride semiconductor light emitting diode device. As shown in FIG. 1, the structure of a conventional group III-nitride semiconductor light emitting diode device formed on an upper surface of a sapphire growth substrate will be described in detail.

1 is a cross-sectional view of a conventional group III-nitride semiconductor light emitting diode device. The light emitting structure for the group III nitride semiconductor light emitting diode device is grown on the sapphire growth substrate 10. The conventional group III nitride semiconductor light emitting diode device is grown on the growth substrate 10 and the growth substrate 10. Light emitting structures 20, 30, and 40 for group III-nitride semiconductor light emitting diode elements formed in the substrate.

The light emitting structures 20, 30, and 40 for the group III-nitride semiconductor light emitting diode devices are sequentially formed on the growth substrate 10 and the n-type nitride cladding layer 20 and the multi-quantum well. A nitride active layer 30 and a p-type nitride cladding layer 40. The light emitting structure for the light emitting diode device may be grown using a process such as MOCVD. In this case, before the n-type nitride cladding layer 20 is grown, a buffer layer (not shown) made of AlN or GaN may be formed to relieve stress caused by lattice matching with the growth substrate 10 and a difference in coefficient of thermal expansion. It may be.

In addition, the p-type nitride cladding layer 40 and the nitride-based active layer 30 corresponding to a predetermined region are dry-etched to expose a part of the upper surface of the n-type nitride cladding layer 20 to the atmosphere, and the exposed n-type. The p-type ohmic contact electrode and the pad 60 and the n-type ohmic contact electrode and the pad 70 for applying a predetermined voltage to the upper surface of the nitride cladding layer 20 and the upper surface of the p-type nitride cladding layer 40 are respectively provided. Form. In general, in order to increase the current injection area while not adversely affecting the brightness, the p-type ohmic contact electrode, the pad 60 and the n-type cladding layer 40 and the n-type nitride cladding layer 20 are disposed on the upper surface. Prior to forming the type ohmic contact electrode and the pad 70, a transparent current spreading layer may be formed. In FIG. 1, a transparent current spreading layer 50 positioned between the p-type nitride cladding layer 40, the p-type electrode, and the pad 60 is illustrated.

As described above, the conventional group III-nitride semiconductor light emitting diode device uses the sapphire growth substrate 10 which is an electrical insulator, so that the two ohmic contact electrodes and the pads 60 and 70 can be formed side by side in the horizontal direction. none. Therefore, when an external voltage is applied, a current flow from the n-type ohmic contact electrode and the pad 70 to the p-type ohmic contact electrode and the pad 60 through the nitride based active layer 30 is inevitably formed along the horizontal direction. . Due to this narrow current flow, the group III-nitride-based semiconductor light emitting diode device has a forward voltage, which reduces the current injection efficiency (called "current crowding phenomenon"), thereby causing electrostatic discharge. ) The problem is that the effect is weak.

In addition, in the conventional group III-nitride semiconductor light emitting diode device, a large amount of heat is generated due to an increase in current density, while low heat conductivity of the sapphire growth substrate 10 may cause heat emission to the outside. Therefore, as the current density increases, mechanical stress is generated between the sapphire growth substrate 10 and the light emitting structure for the light emitting diode device, thereby affecting the electrical and optical characteristics of the device.

Furthermore, in the conventional group III-nitride semiconductor light emitting diode device, in order to form the n-type ohmic contact electrode and the pad 70, the nitride system is larger than the area of the n-type ohmic contact electrode and the pad 70 to be formed. Since some areas of the active layer 30 need to be removed, there is a problem that the light emitting area is reduced, thereby reducing the light emitting efficiency according to the device size versus the luminance.

Group III nitride semiconductor light emitting diode devices that overcome the problems of the group III nitride semiconductor light emitting diode devices formed on the upper surface of the electrically insulating sapphire growth substrate 10 and have high energy conversion efficiency and high luminance emission characteristics. In order to implement the method, when driving a light emitting device, a large amount of electric energy must be applied from outside or a large unit chip must be manufactured. Currently, the implementation of a light emitting diode device having high energy conversion efficiency and high luminance light emitting characteristics is performed by applying a large current (that is, a large capacity) to the light emitting diode device, which is a relatively easy method, It is difficult to solve the heat dissipation problem.

Recently, as a new alternative, Germany's OSRAM has grown a laser lift-off of a vertical group III-nitride semiconductor light emitting diode device product called thinGaN LED by removing the growth substrate. The company has developed the substrate removal technology, and several other advanced companies are focusing on the development of similar type group III-nitride semiconductor light emitting diode devices.

The vertical structure group III-nitride semiconductor light emitting diode device having high energy conversion efficiency and high brightness through the removal of the transparent growth substrate may be manufactured if only the removal of the sapphire growth substrate 10 is performed reliably. You can innovate significantly. In addition, in the case of manufacturing a group III nitride semiconductor light emitting diode device formed on the upper surface of the sapphire growth substrate 10, the light emitting area is about 50% of the unit chip area, whereas the vertical structure light emitting diode from which the sapphire growth substrate 10 is removed In the case of the device, since the light emitting area reaches about 90% of the unit chip area, it is much more advantageous than the light emitting diode device having a horizontal structure including the sapphire growth substrate 10 from an economical and technical point of view. However, the horizontal light emitting diode device including the sapphire growth substrate 10 and the vertical light emitting diode device using the sapphire growth substrate 10 removal method still apply a large current to a device having a constant unit chip emission area. The conversion efficiency ('externally applied electrical energy versus emitted light energy') is not good.

Therefore, in order to implement group III-nitride-based light emitting diode devices having high energy conversion efficiency and high luminance characteristics, it is much more advantageous in terms of technology and economics to use a large area low current injection method.

Currently, a light emitting diode device including the sapphire growth substrate 10 has a current crowding phenomenon due to the electrical conductivity of a low p-type nitride based cladding layer, so that technical limitations are fundamental in manufacturing a large area light emitting diode device. There is this. In addition, the vertical structure light emitting diode device using the sapphire growth substrate 10 removal method is also manufactured by the large-area vertical structure light emitting device due to the limitation of the laser beam size used in manufacturing the light emitting device, and high brightness characteristics through low power injection. It is not easy to secure a light source with. In general, since the conventional laser lift-off method can irradiate a laser beam of a uniform and strong energy source having an area of one square centimeters, damage and cracks of the solid semiconductor thin film before irradiating the laser beam ( In order to minimize crack propagation, isolation processing should be performed by using a trench to the sapphire growth substrate 10 by dry etching. The islanding process is a technique for preventing the occurrence of microcracks in the group III nitride-based semiconductor thin film and propagation to the generation and propagation of crack. However, since the light emitting structure area of the light emitting diode device isolated to a predetermined light emitting area transferred to the electroconductive support by the laser lift-off method is limited to the shape and size of the laser beam used, the vertical light emitting diode device You can not freely increase the size of.

In addition to the islanding process through the trench, in order to realize a vertical light emitting diode device including a group III nitride semiconductor as a next-generation light source, damage to the semiconductor thin film layer generated when the laser lift-off method is introduced must be minimized. A support having excellent adhesion to the upper surface of the light emitting structure for a light emitting diode device for the purpose of preventing cracking, propagation, and breaking due to latent stress existing between the group 10 and the group III-nitride semiconductor thin film layer. ) To form. In addition to mitigating potential stress during the laser lift-off process, the support also has excellent thermal and electrical conductivity, thereby releasing a large amount of heat generated during driving of the finally manufactured vertical LED device. It should be able to act as a heat-sink and as an electrode and pad for current injection.

As described above, electroplating and wafer bonding are mainly used as a method for forming a support for manufacturing a vertical light emitting diode device through a laser lift-off method.

Using the support formed by the electroplating has the advantage that it is relatively easy to manufacture a vertical structure light emitting diode device, but there is a lot of room that can cause serious problems in the overall device reliability of the finally produced vertical structure light emitting diode device There is a limitation in improving device performance (see FIG. 2). On the other hand, the support formed by the wafer bonding is advantageous in that there is much potential for securing stable device reliability and improving device performance. The process of forming a support by such wafer bonding must successfully perform wafer bonding between dissimilar materials having different thermal expansion coefficients. However, due to thermal stress after wafer bonding between dissimilar materials, various serious problems such as fine cracks or cracks in the growth substrate or the semiconductor thin film layer, and moreover, debonding are emerging (see FIG. 3). Accordingly, the fabrication of vertical light emitting diode devices using wafer bonding currently uses a conductive wafer bonding layer (eg, a eutectic process reaction system) capable of wafer bonding at a temperature of less than 300 ° C.

An electroconductive support is formed through the electroplating (see FIG. 2) and the wafer bonding (see FIG. 3), and the vertical structure of the light emitting diode device is described in more detail as follows.

A vertical light emitting diode device manufacturing process using the support formed by the electroplating is shown in FIG. 2. First, a light emitting structure for a light emitting diode device composed of an n-type nitride cladding layer 20, a nitride-based active layer 30, and a p-type nitride cladding layer 40 is formed on the upper surface of the growth substrate 10. As shown in FIG. 2A (not shown), the trench 80 is used to perform an isolation process smaller than the laser beam size. Thereafter, the passivation layer 60 including the device passivation layer 50 and the current blocking region, and a seed layer 70a for forming a metal thick film such as Ni and Cu, which are electrically conductive materials, are formed by electroplating. It is formed on the upper surface or the side of the light emitting structure for the light emitting diode device. Thereafter, as shown in FIG. 2B, the organic material post 90 is erected in the trench 80, and at the same time, a seed layer 70a for forming a metal thick film such as Ni or Cu, which is an electrically conductive material, is formed by electroplating. It is also formed on the upper surface of the organic post 90. Thereafter, as shown in FIG. 2C, a metal thick film such as Ni or Cu, which is an electrically conductive material serving as the support 100, is formed by electroplating. Thereafter, as shown in FIG. 2D, the planarization process of removing the growth substrate 10 and removing the laser lift-off debris is performed by using the laser lift-off method. Thereafter, as shown in FIG. 2E, a surface texture 110 and an ohmic contact electrode and a pad 120 are formed in a portion of the n-type nitride cladding layer 20 exposed to the atmosphere. Thereafter, as shown in FIG. 2F, the unit chip is completed by mechanical or laser processing as a final process.

A vertical light emitting diode device manufacturing process using a support formed by wafer bonding is shown in FIG. 3. First, a light emitting structure for a light emitting diode device composed of an n-type nitride cladding layer 20, a nitride-based active layer 30, and a p-type nitride cladding layer 40 is formed on the upper surface of the growth substrate 10. As shown in FIG. 3A (not shown), the trench 80 is used to perform an isolation process smaller than the laser beam size. Thereafter, a device passivation layer 50, a reflective layer 60 including a current blocking region, and a conductive wafer bonding layer 70b are formed on the top or side surfaces of the light emitting structure for the light emitting diode device. Thereafter, as shown in FIG. 3B, the conductive wafer bonding layer 70b is used to bond wafers, such as Si, which are electrically conductive substrates, to the support 140. Thereafter, as shown in FIG. 3C, the planarization process of removing the growth substrate 10 and the laser lift-off process debris and the like is performed using the laser lift-off method. Thereafter, as shown in FIG. 3D, a surface texture 110, an ohmic contact electrode, and a pad 120 are formed in a portion of the n-type nitride cladding layer 20 exposed to the atmosphere. Then, as shown in FIG. 3E, the unit chip is completed by mechanical or laser processing as a final process.

As described above, the fabrication of a vertical structure light emitting diode device using a technology for forming a support base through electroplating and wafer bonding is common to a light emitting diode device having a scale smaller than a laser beam size before removing the growth substrate 10. It is characterized in that it comprises an isolation process for unifying the light emitting structure. Fabrication of a vertical light emitting diode device using such a flashing process makes it difficult to manufacture a light emitting device having a light emitting area larger than that of a laser beam.

In addition, in the fabrication of a vertical structure light emitting diode device using a technology for forming a support base through electroplating and wafer bonding, after removing the growth substrate 10 in common, post-annealing may be performed at a temperature of 300 ° C. or higher. It is difficult to manufacture a thermally stable high reliability single chip. For example, it is considered that a single chip manufactured without undergoing a heat treatment process of 300 ° C. or more may have many limitations in the future as a light source for illumination. For this reason, an electroplating thick film such as Ni or Cu, which is a support formed by electroplating, has not a dense structure but is composed of amorphous or polycrystal having many porosities. At the same time, a large amount of sulfur (S) and phosphorus (P) components are added in the thick film, which leads to the diffusion of these materials with the use time, which in turn causes problems in device reliability. In addition, since the bond formed by the wafer bonding is formed at a temperature below 300 ° C. in order to minimize the stress caused by the difference in thermal expansion coefficient, the post-process of 300 ° C. or more cannot be performed.

Therefore, in order to manufacture a large area vertical light emitting diode device as a next-generation lighting light source, a growth substrate removal process technology through thermally stable and dense electroconductive support formation should be developed first.

The present invention is to solve the above problems, when using a laser lift-off, mechanical polishing, or etching technology to perform the growth substrate for growth of the light emitting structure consisting of group III nitride-based semiconductor, the group An object of the present invention is to propose a vertical structure light emitting diode device and a method of manufacturing the same, which minimize damage of the light emitting structure for a group III nitride semiconductor light emitting diode device and improve electrical and optical characteristics. In order to successfully accomplish this purpose, a heatsink support of laminate structure must be formed through a technical process capable of wafer bonding under constant pressure and at least 300 ° C temperature conditions.

Another object of the present invention is to provide a manufacturing method of maximizing the characteristics of a unit chip which minimizes leakage current by blocking damage to a light emitting structure due to wafer bending (bending) that occurs during manufacturing of a conventional unified vertical structure light emitting diode device.

One embodiment of the vertical structure light emitting diode device according to the present invention includes an n-type ohmic contact electrode structure, an n-type nitride cladding layer, a nitride-based active layer, and a p-type nitride cladding layer formed on the lower surface of the n-type ohmic contact electrode structure. A p-type ohmic contact electrode layer and a first device passivation layer including a light emitting structure having a light emitting structure and a current blocking region formed on a lower surface of the light emitting structure, and a reflective ohmic contact formed on a lower surface of the p-type ohmic contact electrode layer and a first device passivation layer A p-type ohmic contact electrode structure formed on an electrode layer, a conductive wafer bonding layer formed on a lower surface of the reflective ohmic contact electrode layer, a heat sink support of a laminate structure formed on a lower surface of the conductive wafer bonding layer, and a lower surface of the heat sink support of the laminate structure. And Group III nitride semiconductor vertical spheres composed of a die bonding layer and a die bonding layer. In the light emitting diode device;

The p-type ohmic contact electrode layer is optically a transparent material having a transmittance of 75% or more, or is formed of a 80% or more reflector material having a high reflectance.

The current blocking region in the p-type ohmic contact electrode layer is formed of an air state or an electrically insulating material, or a material forming a schottky contact interface with the p-type nitride cladding layer.

The second device passivation layer protects the light emitting structure, the p-type ohmic contact electrode layer, the first device passivation layer, the reflective ohmic contact electrode layer, and the first conductive wafer bonding layer.

In addition, the reflective ohmic contact electrode layer is formed to be wider than the p-type ohmic contact electrode layer having a predetermined area,

In the laminate heatsink support, two electrical conductors are coupled to the conductive wafer bonding layer.

The n-type ohmic contact electrode structure is disposed on the n-type nitride-based cladding layer so as to face at the same position in the vertical direction with the current blocking region in the p-type ohmic contact electrode layer,

In addition, the n-type ohmic contact electrode structure is characterized in that the surface texture (surface texture) for forming a structural shape on the surface of the n-type nitride-based cladding layer is not formed.

Thus, the first embodiment of the method for manufacturing a vertical light emitting diode device according to the present invention is to manufacture a vertical light emitting diode device by separating a growth substrate using the laser lift-off, mechanical polishing, or etching process technique.

Performing an islanding process on the light emitting structure for the light emitting diode device grown on the upper surface of the growth substrate in a predetermined area (for example, the size of a chip); Forming a p-type ohmic contact electrode layer and a first device passivation layer on the light emitting structure for the light emitting diode device which has undergone the islanding process; Forming a reflective ohmic contact electrode layer on top of the p-type ohmic contact electrode layer and the first device passivation layer; Forming a first conductive wafer bonding layer on an upper surface of the reflective ohmic contact electrode layer; Forming first and second conductive wafer bonding layers on upper and lower surfaces of the first electrical conductor, respectively; Sequentially forming a first sacrificial separation layer and a second conductive wafer bonding layer on an upper surface of the first wafer plate; Bonding the growth substrate and the wafer plate to upper and lower surfaces of the first and second conductive wafer bonding layers on the upper and lower surfaces of the first electrical conductor to form a first sandwich composite; Separating the first wafer plate from the first sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Removing a second conductive wafer bonding layer from the first sandwich composite, and forming a third conductive wafer bonding layer; Forming third and fourth conductive wafer bonding layers on upper and lower surfaces of the second electrical conductor, respectively; Sequentially forming a second sacrificial separation layer and a fourth conductive wafer bonding layer on an upper surface of the second wafer plate; Bonding the first sandwich composite and the second wafer plate to upper surfaces of the third and fourth conductive wafer bonding layers on the upper and lower surfaces of the second electrical conductor to form a second sandwich composite; Separating the growth substrate from the second sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Etching the n-type nitride clad layer to be exposed to the atmosphere in the second sandwich composite from which the growth substrate is separated; Forming a second device passivation layer on the top and side surfaces of the islanded light emitting structure; Forming surface irregularities on an upper surface of the n-type nitride clad layer exposed to the air; Forming an n-type ohmic contact electrode structure on an upper surface of the n-type nitride clad layer on which the surface irregularities are formed; Performing etching and cutting processes in a vertical direction to an upper surface of the second wafer plate for a unit LED chip; Separating the second wafer plate using a laser lift off, mechanical polishing, or etching process; And forming a p-type ohmic contact electrode structure and a die bonding layer on a lower surface of the second electric conductor exposed to the atmosphere.

Accordingly, the second embodiment of the method for manufacturing a vertical light emitting diode device according to the present invention is to manufacture a vertical light emitting diode device by separating a growth substrate using the laser lift-off, mechanical polishing, or etching process technique.

Performing an islanding process on the light emitting structure for the light emitting diode device grown on the upper surface of the growth substrate in a predetermined area (for example, the size of a chip); Forming a p-type ohmic contact electrode layer and a first device passivation layer on the light emitting structure for the light emitting diode device which has undergone the islanding process; Forming a reflective ohmic contact electrode layer on top of the p-type ohmic contact electrode layer and the first device passivation layer; Forming a second device passivation layer on an upper surface or a side surface of the p-type ohmic contact electrode layer, the first device passivation layer, and the reflective ohmic contact electrode layer; Forming a first conductive wafer bonding layer on an upper surface of the reflective ohmic contact electrode layer; Forming first and second conductive wafer bonding layers on upper and lower surfaces of the first electrical conductor, respectively; Sequentially forming a first sacrificial separation layer and a second conductive wafer bonding layer on an upper surface of the first wafer plate; Bonding the growth substrate and the first wafer plate to upper and lower surfaces of the first and second conductive wafer bonding layers on the upper and lower surfaces of the first electrical conductor to form a first sandwich composite; Separating the first wafer plate from the first sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Removing a second conductive wafer bonding layer from the first sandwich composite, and forming a third conductive wafer bonding layer; Forming third and fourth conductive wafer bonding layers on upper and lower surfaces of the second electrical conductor, respectively; Sequentially forming a second sacrificial separation layer and a fourth conductive wafer bonding layer on an upper surface of the second wafer plate; Bonding the first sandwich composite and the second wafer plate to upper surfaces of the third and fourth conductive wafer bonding layers on the upper and lower surfaces of the second electrical conductor to form a second sandwich composite; Separating the growth substrate from the second sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Etching the n-type nitride cladding layer to be exposed to the atmosphere in the second sandwich composite from which the growth substrate is separated; Forming surface irregularities on an upper surface of the n-type nitride clad layer exposed to the air; Forming an n-type ohmic contact electrode structure on an upper surface of the n-type nitride clad layer on which the surface irregularities are formed; Performing etching and cutting processes in a vertical direction to an upper surface of the second wafer plate for a unit LED chip; Separating the second wafer plate using a laser lift off, mechanical polishing, or etching process; And forming a p-type ohmic contact electrode structure and a die bonding layer on a lower surface of the second electric conductor exposed to the atmosphere.

As described above, when the electric conductors are tightly coupled under the constant pressure proposed in the present invention and at least 300 ° C. or more, the light-emitting structure for the light emitting diode device is separated from the growth substrate without thermal and mechanical damage. In this way, a vertical light emitting diode device, which is a light source for next generation lighting, can be manufactured to realize a high-efficiency light emitting device even when a large current is injected.

In addition, since the heat sink support forming technology of the laminate structure according to the present invention is simpler than the heat sink support forming by the conventional electroplating or low temperature wafer bonding process technology, it takes time and cost to manufacture a light emitting diode device and a light emitting device. Significantly reduced.

Hereinafter, a wafer bonding process technology for manufacturing a vertical structure light emitting diode device, and a vertical structure light emitting diode device having a laminate structure heatsink support and a manufacturing method thereof will be described in detail with reference to FIGS. 4 to 32. Explain.

4 is a schematic cross-sectional view showing a process of manufacturing a vertical structure light emitting device using a group III nitride-based semiconductor through a wafer bonding process proposed by the present invention.

The manufacturing process of the light emitting device (ie, the light-related solid semiconductor device) is manufactured in plural using a predetermined wafer substrate, but for convenience of description in FIG. 4, two vertical structure group III nitride-based light emitting devices are manufactured. The process is illustrated.

As shown in Fig. 4A, the growth substrate 401 on which the light emitting structure 402 is grown, and the machined electroconductive heatsink support 403 is machined. The wafer plate 404 on which the sacrificial separation layer 405 is formed is prepared. Here, although not shown, a reflective ohmic contact electrode layer or a conductive wafer bonding layer may be formed on the upper and lower surfaces of the light emitting structure 402 and the heat sink supporter 403 in a single layer or a multi-layered structure. .

Further, the machined electroconductive heatsink support 403 does not limit the use of any material as long as it has a material having excellent thermal and electrical conductivity, but preferentially the machined Si, SiGe, ZnO, GaN, AlSiC, A GaAs substrate and a metal, alloy, or solid solution made of at least one of Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, and W components are used.

In addition, the wafer plate 404, which is a temporary substrate, preferentially uses the same material as the light emitting structure growth substrate, but any material may be used as long as the difference in thermal expansion coefficient with the growth substrate 401 is 2 ppm / ° C or less. Do not limit to.

In addition, the sacrificial separation layer 405 formed on the upper surface of the wafer plate 404 as a temporary substrate is a group 2-6 compound including ZnO, a group 3-5 compound including GaN, Al, Au, Ag, Cr, Ti, It is composed of various metals, alloys, organic materials including ITO, PZT, SU-8, etc.

Subsequently, as shown in FIG. 4B, the wafer plate 404 having the growth substrate 401 on which the light emitting structure 402 is grown and the sacrificial separation layer 405 are formed under a constant pressure and at least 300 ° C. or higher. The upper and lower surfaces of the machined electroconductive heat sink supporter 403 are simultaneously bonded to each other using a conductive wafer bonding layer (not shown) so that the two substrates 401 and 404 face each other to form a sandwich composite. Here, the conductive wafer bonding layer (not shown) is made of a multi-layer structure of a single layer or a double layer or more.

Next, as shown in FIG. 4C, the growth substrate 401 may be partially removed from the light emitting structure 402 by using a laser lift-off, mechanical polishing, or etching process technique. Or remove it front. Here, the laser lift-off technique is preferentially used in the case of the optically transparent growth substrate 401 such as sapphire. The laser beam used in the laser lift-off technique preferably has a larger energy (or shorter wavelength) than the energy band gap of the material interfacing with the growth substrate 401, and the laser beam is formed on the back of the growth substrate 401. Since the laser beam has a constant area, the growth substrate 401 having a large area is irradiated at regular intervals. When the laser beam irradiates the growth substrate 401 at regular intervals, the growth substrate 401 is sequentially separated from the portion to which the laser beam is irradiated. In this case, the heat sink supporter 403 must be closely bonded to the light emitting structure 402 through the conductive wafer bonding layer (not shown). In particular, when the laser beam irradiates the growth substrate 401 at regular intervals, minute cracks are generated in the light emitting structure 402 due to thermal and mechanical shock variations at the interface between the laser beam and the unirradiated portion. It also spreads widely and lowers overall product yield. In order to prevent this, in the prior art, the islanding process is performed, or in the prior domestic patent of the inventor (application number 10-2008-0030106) The functional composite film layer was inserted in the wafer bonding process directly on the upper surface of the light emitting structure 402 instead of the islanding process.

In addition, it is preferable to use diamond and SiC powder for the mechanical polishing.

In addition, the wet etching may be sulfuric acid, phosphoric acid, hydrochloric acid, trivalent chromic acid, hexavalent chromic acid, gallium (Ga), indium (In), aluminum (Al), magnesium (Mg), allue (4H3PO4 + 4CH3COOH + HNO3 +). H2O) is used as an etchant which is the main component of the mixed solution, and in order to improve the etching rate, it is preferable to increase the concentration of phosphoric acid and the temperature of the etchant. The temperature of the etching solution is preferably 200 ℃ to 500 ℃ for shortening the process time.

Next, as shown in FIG. 4D, after the growth substrate 401 is separated, the light emitting structure 402 is etched in unit chip units using an etching or cutting process technique, and the upper surface of the light emitting structure 402 is exposed to the atmosphere. The first ohmic contact electrode structure 406 is formed. Here, the first ohmic contact electrode structure 406 material is deposited, and then heat treatment is performed at a temperature and gas atmosphere to form an ohmic contact interface.

Next, as illustrated in FIG. 4E, an etching or cutting process is performed on the heat sink support 403 for manufacturing the unit chip. In particular, mechanical cutting or laser processing is used until the wafer plate 404 surface is exposed to air.

Finally, as shown in FIG. 4F, the sacrificial separation layer 405 formed on the upper surface of the wafer plate 404 is dissolved or thermally chemically decomposed to completely separate the wafer plate 404. In addition, although not shown, the wafer plate 404 is completely removed, and a second ohmic contact electrode structure is formed on the rear surface of the heat sink supporter 403. After depositing the second ohmic contact electrode structure material, heat treatment is performed at a temperature and a gas atmosphere to form an ohmic contact interface. Here, the wafer plate 404 is separated using a laser lift off, mechanical polishing, or etching process technique as shown in FIG. 4C.

5 to 18 are cross-sectional views illustrating a manufacturing process of a vertical light emitting diode device as a first embodiment according to the present invention.

FIG. 5 is a cross-sectional view showing a growth substrate prepared before forming a first sandwich composite as a first step of manufacturing a vertical light emitting diode device.

The n-type nitride cladding layer 502 including the buffer layer, the nitride-based active layer 503, and the p-type nitride cladding layer 504 are sequentially grown on the growth substrate 501, and then subjected to a islanding process. The p-type ohmic contact electrode layer 510 and the first device passivation layer 509 are stacked on the upper surface of the nitride nitride cladding layer 504. Next, the reflective ohmic contact electrode layer 511 is stacked on the upper surface of the p-type ohmic contact electrode layer 510 and the first device passivation layer 509, and then a first conductive wafer is formed on the reflective ohmic contact electrode layer 511. The bonding layer 508 is formed.

The growth substrate 501 may include sapphire (Al 2 O 3), silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN). ), Glass, and the like, and in particular, a sapphire substrate is typically used, which is the same as the crystal structure of the group III-nitride semiconductor material grown on the growth substrate 501 and forms a lattice match. Because it does not exist.

The n-type nitride cladding layer 502 grown on the growth substrate 501 has an Al x In y Ga (1-xy) N composition formula (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1). It can be made of a group III-nitride-based semiconductor material to which an n-type dopant having a) is added, in particular GaN is widely used. In addition, before the n-type nitride cladding layer 502 is grown, a material layer (referred to as a “buffer layer”) to alleviate stress caused by mismatched lattice matching and thermal expansion coefficient difference may be inserted. In particular, GaN and AlN may be inserted. , InGaN, AlGaN, SiC, SiCN are widely used.

The nitride-based active layer 503 formed on the n-type nitride-based cladding layer 502 has a quantum well structure and has an AlxInyGa (1-xy) N composition formula (where 0 ≦ x ≦ 1, 0 ≦ and a group III-nitride semiconductor material system having y ≦ 1, 0 ≦ x + y ≦ 1).

The p-type nitride cladding layer 504 formed on the upper surface of the nitride-based active layer 503 is similar to the n-type nitride-based cladding layer 502, where Al x In y Ga (1-xy) N composition formula (where 0 ≦ x ≦ 1 And a group III nitride semiconductor material having 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), and a p-type dopant is added.

The p-type nitride cladding layer 504 may separately include an interface modification layer. The surface modification layer is a superlattice structure, a surface formed of n-type conductive InGaN, GaN, AlInN, AlN, InN, AlGaN, p-type conductive InGaN, AlInN, InN, AlGaN, or nitrogen polarity (nitrogen- group III nitride system having a polar surface. In particular, the surface modification layer of the superlattice structure is composed of nitride or carbon nitride containing group 2, 3, or 4 element elements.

Here, the n-type nitride-based cladding layer 502, the nitride-based active layer 503, the p-type nitride-based cladding layer 504 is deposited by a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method, etc. It is preferably grown using a process, but especially by MOCVD.

The p-type ohmic contact electrode layer 510 forms an ohmic contact interface on the upper surface of the p-type nitride cladding layer 504 and includes a current blocking region. The current blocking region may be formed of an air or electrically insulating material, or a material forming a schottky contact interface with the p-type nitride cladding layer.

The first device passivation layer 509 is formed on the upper surface of the p-type nitride cladding layer 402 and the mesa-etched side surface. As the first device passivation layer 509, a silicon oxide thin film (SiO 2), a silicon nitride thin film (SiNx), an aluminum oxide thin film (Al 2 O 3), or the like is used, and the first device passivation layer 509 is 10 to 100 nm. It is preferable to form in thickness.

The reflective ohmic contact electrode layer 511 is formed on an upper surface of the p-type ohmic contact electrode layer 510 and the first device passivation layer 509, and the material constituting the reflective ohmic contact electrode layer 511 is nickel (Ni), an alloy related to Ni, a solid solution, or a silver ( Ag), Ag related alloys and solid solutions, aluminum (Al), Al related alloys and solid solutions, rhodium (Rh), Rh related alloys and solid solutions, platinum (Pt), Pt related alloys and solid solutions, palladium (Pd), Pd related alloys And various silicides such as solid solutions, gold (Au), Au-related alloys and solid solutions, Ag-Si, Al-Si, Rh-Si, Pd-Si, Ni-Si, Cr-Si, Pt-Si, and the like.

In addition, the reflective ohmic contact electrode layer 511 is formed wider than the p-type ohmic contact electrode layer 510 having a predetermined area.

The first conductive wafer bonding layer 508 forms Au, Ni, Cu, Ti, Ag, Al to form a dense adhesive force on a portion of the upper surface of the reflective ohmic contact electrode layer 511 under a predetermined pressure and a temperature condition of at least 300 ° C. At least one of Si, Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals; Present metals, alloys, solid solutions, compounds, in particular single or double layers or more.

FIG. 6 is a cross-sectional view showing a first electric conductor portion prepared before forming a first sandwich composite as a step of manufacturing a vertical light emitting diode device.

Conductive wafer bonding layers 602 and 603 are formed on upper and lower surfaces of the first electrical conductor 601. Here, A surface, which is an upper surface of the first electric conductor 601, is a surface on which the growth substrate portion on which the light emitting structure is grown is coupled, and B, an opposite surface, is a surface on which the first wafer plate, which is a temporary substrate, is coupled.

The first electrical conductor 601 has a thickness of 50 μm or less, and has a sheet, disk, or foil shape in which both surfaces are machined.

In addition, as long as the first electric conductor 601 is a material having excellent heat and electric conductivity, any material is not limited to use. In particular, the upper and lower surfaces consist of at least one of Si, SiGe, ZnO, GaN, AlSiC, GaAs substrates, and Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, W components machined Preference is given to using metals, alloys, or solid solutions.

The first conductive wafer bonding layer 602 and the second conductive wafer bonding layer 603 may be formed of Au, Ni, Cu, Ti, Ag, Al, Si, which form a dense adhesive force under a predetermined pressure and at least 300 ° C. Metals containing at least one of Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals, Alloys, solid solutions, compounds are used, in particular consisting of a multi-layer structure of more than a single layer or a double layer.

7 is a cross-sectional view of a first wafer plate prepared as a step of fabricating a vertical light emitting diode device, before forming the first sandwich composite.

The first sacrificial separation layer 702 and the second conductive wafer bonding layer 703 are sequentially formed on the first wafer plate 701 as a temporary substrate. Here, the first wafer plate 701 preferentially uses the same material as that of the growth substrate 501 of the light emitting structure, and any material type having a thermal expansion coefficient difference of 2 ppm / ° C. or less from the growth substrate 501 may be used. The substance is not limited to use.

In addition, the first sacrificial separation layer 702 formed on the upper surface of the first wafer plate 701 may be a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, Ti, and the like. It is composed of various metals, alloys, organics, including ITO, PZT, SU-8 and the like.

The second conductive wafer bonding layer 703 is Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, Rh, W, Mo to form a dense adhesive force under a constant pressure and temperature conditions of 300 ℃ or more Metals, alloys, solid solutions, compounds containing at least one of V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals are used, in particular monolayers. Or it consists of a multilayer structure more than a bilayer.

8 is a cross-sectional view of a first sandwich composite in which a vertical structure light emitting diode device is manufactured and wafer-bonded to a growth substrate portion, a first electrical conductor portion, and a first wafer plate portion at the same time.

The growth substrate portion A includes an n-type nitride cladding layer 502, a nitride-based active layer 503, a p-type nitride cladding layer 504, a p-type ohmic contact electrode layer 510 on an upper surface of the growth substrate 501, The first device passivation layer 509, the reflective ohmic contact electrode layer 511, and the first conductive wafer bonding layer 508 are stacked.

In the first electrical conductor part B, first and second conductive wafer bonding layers 602 and 603 are stacked on upper and lower surfaces of the first electrical conductor 601, respectively.

In the first wafer plate portion C, a rare separation layer 702 and a second conductive wafer bonding layer 703 are sequentially stacked on an upper surface of the wafer plate 701 which is a temporary substrate.

The growth substrate portion A, the first electrical conductor portion B, and the first wafer plate portion C may be bonded to each other between the first conductive wafer bonding layer 508/602 and the second conductive wafer bonding layer, respectively. 603/703) at a constant pressure and at temperatures above 300 ° C.

Here, the process gas atmosphere of wafer bonding is preferably vacuum, nitrogen (N 2), argon (Ar) gas, but in some cases, oxygen (O 2) gas may be added.

9 is a step of manufacturing a vertical light emitting diode device, and after separating the first wafer plate and the second conductive wafer bonding layer from the wafer-bonded first sandwich composite, the third conductive material to the first electrical conductor exposed to the atmosphere It is sectional drawing which shows the process of forming a wafer bonding layer.

The process of separating the first wafer plate 701, which is a temporary substrate, from the first sandwich composite may include thermo-chemical decomposition, wet etching, or chemical-mechanical polishing (CMP) or mechanical polishing using a laser beam having strong energy. ) And the like.

In addition, the second conductive wafer bonding layers 603 and 703 of the first electric conductor 601 may be removed by wet etching, chemical-mechanical polishing (CMP), mechanical polishing, or the like.

On the other hand, Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, which forms a dense adhesive force on the rear surface of the first electrical conductor 601 exposed to the atmosphere under a certain pressure and temperature conditions of more than 300 ℃ Metals, alloys, solid solutions, compounds containing at least one of Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals In particular, a third conductive wafer bonding layer 604 formed of a multi-layer structure of more than a single layer or a double layer is formed.

FIG. 10 is a cross-sectional view showing a second electric conductor portion prepared before forming a second sandwich composite as a step of manufacturing a vertical light emitting diode device. FIG.

Third and fourth conductive wafer bonding layers 606 and 607 are formed on upper and lower surfaces of the second electrical conductor 605. Here, A surface, which is an upper surface of the second electric conductor 605, is a surface to which the first sandwich composite portion on which the light emitting structure is formed is coupled, and B, an opposite surface, is a surface to which the second wafer plate, which is a temporary substrate, is coupled.

The second electrical conductor 605 has a thickness of 10 μm to 1 mm or less, and has a sheet, disk, or foil shape in which both surfaces are machined.

Further, the second electric conductor 605 is not limited to use any material as long as the material has excellent heat and electrical conductivity. In particular, the upper and lower surfaces consist of at least one of Si, SiGe, ZnO, GaN, AlSiC, GaAs substrates, and Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, W components machined Preference is given to using metals, alloys, or solid solutions.

The third conductive wafer bonding layer 606 and the fourth conductive wafer bonding layer 607 are formed of Au, Ni, Cu, Ti, Ag, Al, Si, which form dense adhesion under a predetermined pressure and at least 300 ° C. Metals containing at least one of Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals, Alloys, solid solutions, compounds are used, in particular consisting of a multi-layer structure of more than a single layer or a double layer.

FIG. 11 is a cross-sectional view of a second wafer plate prepared as a step of manufacturing a vertical light emitting diode device, before forming a second sandwich composite. FIG.

The second sacrificial separation layer 705 and the fourth conductive wafer bonding layer 706 are sequentially formed on the upper surface of the second wafer plate 704 which is a temporary substrate. Here, the second wafer plate 704 preferentially uses the same material as that of the growth substrate 501 of the light emitting structure, and any material system having a thermal expansion coefficient difference of 2 ppm / ° C. or less from the growth substrate 501 may be used. The substance is not limited to use.

In addition, the second sacrificial separation layer 705 formed on the upper surface of the second wafer plate 704 may include a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, Ti, and the like. It is composed of various metals, alloys, organics, including ITO, PZT, SU-8 and the like.

The fourth conductive wafer bonding layer 706 is Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, Rh, W, Mo to form a dense adhesive force under a constant pressure and temperature conditions of 300 ℃ or more Metals, alloys, solid solutions, compounds containing at least one of V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals are used, in particular monolayers. Or it consists of a multilayer structure more than a bilayer.

12 is a cross-sectional view of a second sandwich composite in which a first sandwich composite, a second electric conductor portion, and a second wafer plate portion are wafer bonded at the same time as a step of fabricating a vertical light emitting diode device.

The first sandwich composite (D) includes an n-type nitride cladding layer 502, a nitride-based active layer 503, a p-type nitride cladding layer 504, and a p-type ohmic contact electrode layer 510 on the growth substrate 501. , A first device passivation layer 509, a reflective ohmic contact electrode layer 511, a first conductive wafer bonding layer 508, a first conductive wafer bonding layer 602, a first electrical conductor 601, a third conductive wafer The bonding layer 604 is sequentially stacked.

Third and fourth conductive wafer bonding layers 606 and 607 are stacked on the upper and lower surfaces of the second electrical conductor 605, respectively.

In the second wafer plate part F, a second sacrificial separation layer 705 and a fourth conductive wafer bonding layer 706 are sequentially stacked on an upper surface of the second wafer plate 704 which is a temporary substrate.

The first sandwich composite (D), the second electric conductor portion (E), and the second wafer plate portion (F) are bonded to each other between the third conductive wafer bonding layer (604/606) and the fourth conductive wafer bonding layer, respectively. It is performed at a constant pressure and a temperature of 300 ° C. or higher through the joining of the livers 607/706.

Here, the process gas atmosphere of wafer bonding is preferably vacuum, nitrogen (N 2), argon (Ar) gas, but in some cases, oxygen (O 2) gas may be added.

FIG. 13 is a cross-sectional view illustrating a process of separating a growth substrate from a wafer-bonded second sandwich composite as a step of fabricating a vertical light emitting diode device.

Process technology for separating the growth substrate 501 from the second sandwich composite (G) may be a laser lift-off method using an excimer laser, etc., dry and wet It can also be done by etching. In particular, when the growth substrate 501 is sapphire and SiC, it is preferable to perform the laser lift-off method. That is, when the growth substrate 501 is focused and irradiated with an excimer laser beam having a predetermined wavelength, the n-type nitride cladding layer 502 including the growth substrate 501 and the buffer layer may be formed. Thermal energy is concentrated at the interface, so that the interface of the n-type nitride semiconductor 502 including the buffer layer is thermally chemically decomposed into gallium (Ga) and nitrogen (N) molecules, and at the moment where the laser beam passes. Separation of the growth substrate 501 takes place.

FIG. 14 is a cross-sectional view illustrating a process of forming a second device passivation layer after a growth substrate is separated as a step of manufacturing a vertical light emitting diode device.

The second device passivation layer 800 includes an upper surface of the n-type nitride cladding layer 502 exposed to the atmosphere, a first device passivation layer 509, a p-type ohmic contact electrode layer 510, and a reflective ohmic contact electrode layer 511. And a side or top surface of the first conductive wafer bonding layer 508.

In addition, as the second device passivation layer 512, a silicon oxide thin film (SiO 2), a silicon nitride thin film (SiNx), an aluminum oxide thin film (Al 2 O 3), or the like is used. It is preferable to form in thickness of 1000 nm.

FIG. 15 is a cross-sectional view illustrating a process of forming surface irregularities on an upper surface of an n-type nitride clad layer exposed to the atmosphere after removing a portion of the second device passivation layer as a step of manufacturing a vertical light emitting diode device.

After removing a portion of the device passivation layer 800 existing on the top surface of the n-type nitride cladding layer 502, surface irregularities 900 forming a structural shape on the top surface of the n-type nitride based cladding layer 502 are formed. Introduce. The introduction of the surface irregularities 900 may greatly help to emit light generated in the nitride based active layer 503 to the outside, thereby significantly improving the external light emitting efficiency of the vertical light emitting diode device.

Here, the surface unevenness 900 may be formed by using a wet solution to form a pattern having no regularity, or by forming a pattern by various lithography processes, and then forming a bend on the surface of the chip through an etching process. I use it.

FIG. 16 is a cross-sectional view illustrating a process of forming an n-type ohmic contact electrode structure on a top surface of an n-type nitride cladding layer on which surface irregularities are formed as a step of manufacturing a vertical structure light emitting diode device.

An n-type ohmic contact electrode structure 1000 is formed on an upper surface of the n-type nitride cladding layer 502 into which the surface irregularities 900 are introduced. Here, the n-type ohmic contact electrode structure 1000 is formed in a partial region or the entire region by using a mask. In particular, the position of the n-type ohmic contact electrode structure 1000 formed on the n-type nitride-based cladding layer 502 is opposite to the current blocking area in the p-type ohmic contact electrode layer 510.

17 is a cross-sectional view illustrating a process of cutting a vertical light emitting diode device in a vertical direction.

The first conductive wafer bonding layer 602, the first electrical conductor 601, the third conductive wafer bonding layers 604 and 606, and the second electrical conductor 605 to fabricate a completely unified vertical structure light emitting diode device. The first conductive wafer bonding layers 607 and 706 and the second sacrificial separation layer 705 are cut 1100 in the vertical direction. Here, the second wafer plate 704, which is the temporary substrate, is performed until it is exposed to the atmosphere.

18 is a final step of fabricating a vertical light emitting diode device, and after separating the vertical light emitting diode device from the second wafer plate, the temporary substrate, a p-type ohmic contact electrode sphere and a die bonding layer on the rear surface of the second electric conductor. Is a cross-sectional view.

After lifting off a plurality of vertical structure light emitting diode elements unified from the second wafer plate 704 which is the temporary substrate, the p-type ohmic contact electrode 1200 is formed on the rear surface of the second electric conductor 605. And a die bonding layer 1300 is formed. The process of separating the second wafer plate 704, which is the temporary substrate, uses thermo-chemical decomposition, wet etching, or chemical-mechanical polishing (CMP), mechanical polishing, or the like using a laser beam having strong energy.

19 to 31 are cross-sectional views illustrating a process of manufacturing a vertical light emitting diode device as a second embodiment according to the present invention.

19 is a cross-sectional view showing a growth substrate prepared before forming a sandwich composite as a first step of fabricating a vertical light emitting diode device.

The n-type nitride cladding layer 502 including the buffer layer, the nitride-based active layer 503, and the p-type nitride-based cladding layer 504 are sequentially grown on the growth substrate 501 and then subjected to the islanding process. The p-type ohmic contact electrode layer 510 and the first device passivation layer 509 are stacked on the upper surface of the type nitride cladding layer 504. Next, the reflective ohmic contact electrode layer 511 is laminated on the p-type ohmic contact electrode layer 510 and the first device passivation layer 509, and then the first device passivation layer 509 and the reflective ohmic contact electrode layer are successively stacked. A second element passivation layer 800 is formed on the upper surface or the side surface. Thereafter, after removing a portion of the second device passivation layer 800, a first conductive wafer bonding layer 508 is formed on the reflective ohmic contact electrode layer 511.

The growth substrate 501 may include sapphire (Al 2 O 3), silicon carbide (SiC), silicon (Si), gallium arsenide (GaAs), aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN). ), Glass, and the like, and in particular, a sapphire substrate is typically used, which is the same as the crystal structure of the group III-nitride semiconductor material grown on the growth substrate 501 and forms a lattice match. Because it does not exist.

The n-type nitride cladding layer 502 grown on the growth substrate 501 has an Al x In y Ga (1-xy) N composition formula (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ x + y ≦ 1). It can be made of a group III-nitride-based semiconductor material to which an n-type dopant having a) is added, in particular GaN is widely used. In addition, before the n-type nitride cladding layer 502 is grown, a material layer (referred to as a “buffer layer”) to alleviate stress caused by mismatched lattice matching and thermal expansion coefficient difference may be inserted. In particular, GaN and AlN may be inserted. , InGaN, AlGaN, SiC, SiCN are widely used.

The nitride-based active layer 503 formed on the n-type nitride-based cladding layer 502 has a quantum well structure and has an AlxInyGa (1-xy) N composition formula (where 0 ≦ x ≦ 1, 0 ≦ and a group III-nitride semiconductor material system having y ≦ 1, 0 ≦ x + y ≦ 1).

The p-type nitride cladding layer 504 formed on the upper surface of the nitride-based active layer 503 is similar to the n-type nitride-based cladding layer 502, where Al x In y Ga (1-xy) N composition formula (where 0 ≦ x ≦ 1 And a group III nitride semiconductor material having 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), and a p-type dopant is added.

The p-type nitride cladding layer 504 may separately include an interface modification layer. The surface modification layer is a superlattice structure, a surface formed of n-type conductive InGaN, GaN, AlInN, AlN, InN, AlGaN, p-type conductive InGaN, AlInN, InN, AlGaN, or nitrogen polarity (nitrogen- group III nitride system having a polar surface. In particular, the surface modification layer of the superlattice structure is composed of nitride or carbon nitride containing group 2, 3, or 4 element elements.

Here, the n-type nitride-based cladding layer 502, the nitride-based active layer 503, the p-type nitride-based cladding layer 504 is deposited by a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method, etc. It is preferably grown using a process, but especially by MOCVD.

The p-type ohmic contact electrode layer 510 forms an ohmic contact interface on the upper surface of the p-type nitride cladding layer 504 and includes a current blocking region. The current blocking region may be formed of an air or electrically insulating material, or a material forming a schottky contact interface with the p-type nitride cladding layer.

The first device passivation layer 509 is formed on the upper surface of the p-type nitride cladding layer 402 and the mesa-etched side surface.

In addition, as the first device passivation layer 509, a silicon oxide thin film (SiO 2), a silicon nitride thin film (SiNx), an aluminum oxide thin film (Al 2 O 3), or the like may be used. It is preferable to form in thickness of 100 nm.

The reflective ohmic contact electrode layer 511 is formed on an upper surface of the p-type ohmic contact electrode layer 510 and the first device passivation layer 509, and the material constituting the reflective ohmic contact electrode layer 511 is nickel (Ni), an alloy related to Ni, a solid solution, or a silver ( Ag), Ag related alloys and solid solutions, aluminum (Al), Al related alloys and solid solutions, rhodium (Rh), Rh related alloys and solid solutions, platinum (Pt), Pt related alloys and solid solutions, palladium (Pd), Pd related alloys And various silicides such as solid solutions, gold (Au), Au-related alloys and solid solutions, Ag-Si, Al-Si, Rh-Si, Pd-Si, Ni-Si, Cr-Si, Pt-Si, and the like.

In addition, the reflective ohmic contact electrode layer 511 is formed wider than the p-type ohmic contact electrode layer 510 having a predetermined area.

The second device passivation layer 800 is formed on the top or side surfaces of the first device passivation layer 509 and the reflective ohmic contact electrode layer 511.

In addition, as the second device passivation layer 800, a silicon oxide thin film (SiO 2), a silicon nitride thin film (SiNx), an aluminum oxide thin film (Al 2 O 3), or the like is used, and the second device passivation layer 800 may be 100. It is preferable to form in thickness of -1000 nm.

The first conductive wafer bonding layer 508 forms Au, Ni, Cu, Ti, Ag, Al to form a dense adhesive force on a portion of the upper surface of the reflective ohmic contact electrode layer 511 under a predetermined pressure and a temperature condition of at least 300 ° C. At least one of Si, Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals; Present metals, alloys, solid solutions, compounds, in particular single or double layers or more.

20 is a cross-sectional view of a first light emitting diode device prepared as a step of manufacturing a vertical light emitting diode device and prepared before forming a sandwich composite.

Conductive wafer bonding layers 602 and 603 are formed on upper and lower surfaces of the first electrical conductor 601. Here, A surface, which is the upper surface of the first electric conductor 601, is a surface to which the growth substrate portion on which the light emitting structure is grown is coupled, and B, which is the opposite surface, is a surface to which the first wafer plate, which is a temporary substrate, is coupled.

The first electrical conductor 601 has a thickness of 50 μm or less, and has a sheet, disk, or foil shape in which both surfaces are machined.

In addition, as long as the first electric conductor 601 is a material having excellent heat and electric conductivity, any material is not limited to use. In particular, the upper and lower surfaces consist of at least one of Si, SiGe, ZnO, GaN, AlSiC, GaAs substrates, and Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, W components machined Preference is given to using metals, alloys, or solid solutions.

The first conductive wafer bonding layer 602 and the second conductive wafer bonding layer 603 may be formed of Au, Ni, Cu, Ti, Ag, Al, Si, which form a dense adhesive force under a predetermined pressure and at least 300 ° C. Metals containing at least one of Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals, Alloys, solid solutions, compounds are used, in particular consisting of a multi-layer structure of more than a single layer or a double layer.

21 is a cross-sectional view showing a wafer plate prepared before forming a sandwich composite as a step of manufacturing a vertical light emitting diode device.

The first sacrificial separation layer 702 and the second conductive wafer bonding layer 703 are sequentially formed on the first wafer plate 701 as a temporary substrate. Here, the first wafer plate 701 preferentially uses the same material as that of the growth substrate 501 of the light emitting structure, and any material type having a thermal expansion coefficient difference of 2 ppm / ° C. or less from the growth substrate 501 may be used. The substance is not limited to use.

In addition, the first sacrificial separation layer 702 formed on the upper surface of the first wafer plate 701 may be a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, Ti, and the like. It is composed of various metals, alloys, organics, including ITO, PZT, SU-8 and the like.

The second conductive wafer bonding layer 703 is Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, Rh, W, Mo to form a dense adhesive force under a constant pressure and temperature conditions of 300 ℃ or more Metals, alloys, solid solutions, compounds containing at least one of V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals are used, in particular It consists of a multilayer structure of more than a single layer or a double layer.

FIG. 22 is a cross-sectional view of a first sandwich composite in which a growth substrate, a first electrical conductor, and a first wafer plate are simultaneously bonded to each other by fabricating a vertical light emitting diode device.

The growth substrate part G may include an n-type nitride cladding layer 502, a nitride-based active layer 503, a p-type nitride cladding layer 504, a p-type ohmic contact electrode layer 510, and an upper surface of the growth substrate 501. The first device passivation layer 509, the reflective ohmic contact electrode layer 511, and the first conductive wafer bonding layer 508 are stacked.

In the first electrical conductor part H, first and second conductive wafer bonding layers 602 and 603 are stacked on upper and lower surfaces of the first electrical conductor 601, respectively.

The sacrificial separation layer 702 and the second conductive wafer bonding layer 703 are sequentially stacked on the upper surface of the wafer plate 701 which is a temporary substrate.

The growth substrate portion G, the first electrical conductor portion H, and the first wafer plate portion I may be bonded to each other between the first conductive wafer bonding layer 508/602 and the second conductive wafer bonding layer, respectively. 603/703) at a constant pressure and at temperatures above 300 ° C.

Here, the process gas atmosphere of wafer bonding is preferably vacuum, nitrogen (N 2), argon (Ar) gas, but in some cases, oxygen (O 2) gas may be added.

FIG. 23 illustrates fabricating a vertical light emitting diode device, in which a first wafer plate and a second conductive wafer bonding layer are separated from a wafer-bonded first sandwich composite, and then a third conductivity is applied to the first electrical conductor exposed to the atmosphere. It is sectional drawing which shows the process of forming a wafer bonding layer.

The process of separating the first wafer plate 701, which is a temporary substrate, from the first sandwich composite may include thermo-chemical decomposition, wet etching, or chemical-mechanical polishing (CMP) or mechanical polishing using a laser beam having strong energy. ) And the like.

In addition, the second conductive wafer bonding layers 603 and 703 of the first electric conductor 601 may be removed by wet etching, chemical-mechanical polishing (CMP), mechanical polishing, or the like.

On the other hand, Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, which forms a dense adhesive force on the rear surface of the first electrical conductor 601 exposed to the atmosphere under a certain pressure and temperature conditions of more than 300 ℃ Metals, alloys, solid solutions, compounds containing at least one of Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals In particular, a third conductive wafer bonding layer 604 formed of a multi-layer structure of more than a single layer or a double layer is formed.

24 is a cross-sectional view illustrating a second electric conductor portion prepared before forming a second sandwich composite as a step of manufacturing a vertical light emitting diode device.

Third and fourth conductive wafer bonding layers 606 and 607 are formed on the upper and lower surfaces of the second electrical conductor 605, respectively. Here, A surface, which is an upper surface of the second electric conductor 605, is a surface to which the first sandwich composite on which the light emitting structure is grown is coupled, and B, an opposite surface, is a surface to which the second wafer plate, which is a temporary substrate, is bonded.

The second electrical conductor 605 has a thickness of 10 μm to 1 mm or less, and has a sheet, disk, or foil shape in which both surfaces are machined.

Further, the second electric conductor 605 is not limited to use any material as long as the material has excellent heat and electrical conductivity. In particular, the upper and lower surfaces consist of at least one of Si, SiGe, ZnO, GaN, AlSiC, GaAs substrates, and Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, W components machined Preference is given to using metals, alloys, or solid solutions.

The third conductive wafer bonding layer 606 and the fourth conductive wafer bonding layer 607 are formed of Au, Ni, Cu, Ti, Ag, Al, Si, which form dense adhesion under a predetermined pressure and at least 300 ° C. Metals containing at least one of Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, rare earth metals, Alloys, solid solutions, compounds are used, in particular consisting of a multi-layer structure of more than a single layer or a double layer.

FIG. 25 is a cross-sectional view of a second wafer plate prepared as a step of manufacturing a vertical light emitting diode device, before forming a second sandwich composite. FIG.

The second sacrificial separation layer 705 and the fourth conductive wafer bonding layer 706 are sequentially formed on the upper surface of the second wafer plate 704 which is a temporary substrate. Here, the second wafer plate 704 preferentially uses the same material as that of the growth substrate 501 of the light emitting structure, and any material system having a thermal expansion coefficient difference of 2 ppm / ° C. or less from the growth substrate 501 may be used. The substance is not limited to use.

In addition, the second sacrificial separation layer 705 formed on the upper surface of the second wafer plate 704 may include a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, Ti, and the like. It is composed of various metals, alloys, organics, including ITO, PZT, SU-8 and the like.

The fourth conductive wafer bonding layer 706 is Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, Rh, W, Mo to form a dense adhesive force under a constant pressure and temperature conditions of 300 ℃ or more Metals, alloys, solid solutions, compounds containing at least one of V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, Nb, Mn, Mn, Cr, and rare earth metals are used, in particular monolayers. Or it consists of a multilayer structure more than a bilayer.

FIG. 26 is a cross-sectional view of a second sandwich composite in which a first sandwich composite, a second electrical conductor portion, and a second wafer plate portion are wafer bonded at the same time as a step of manufacturing a vertical light emitting diode device.

The first sandwich composite K includes an n-type nitride cladding layer 502, a nitride-based active layer 503, a p-type nitride cladding layer 504, and a p-type ohmic contact electrode layer 510 on the growth substrate 501. , A first device passivation layer 509, a reflective ohmic contact electrode layer 511, a first conductive wafer bonding layer 508, a first conductive wafer bonding layer 602, a first electrical conductor 601, a third conductive wafer The bonding layer 604 is sequentially stacked.

Third and fourth conductive wafer bonding layers 606 and 607 are stacked on upper and lower surfaces of the second electrical conductor 605, respectively.

In the second wafer plate portion M, a second sacrificial separation layer 705 and a fourth conductive wafer bonding layer 706 are sequentially stacked on an upper surface of the second wafer plate 704 which is a temporary substrate.

The first sandwich composite K, the second electric conductor portion L, and the second wafer plate portion M may be bonded to each other between the third conductive wafer bonding layer 604/606 and the fourth conductive wafer bonding layer, respectively. It is performed at a constant pressure and a temperature of 300 ° C. or higher through the joining of the livers 607/706.

Here, the process gas atmosphere of wafer bonding is preferably vacuum, nitrogen (N 2), argon (Ar) gas, but in some cases, oxygen (O 2) gas may be added.

27 is a cross-sectional view illustrating a process of separating a growth substrate from a wafer-bonded second sandwich composite as a step of fabricating a vertical light emitting diode device.

Process technology for separating the growth substrate 501 from the second sandwich composite (N) may be a laser lift-off method using an excimer laser, etc., dry and wet It can also be done by etching. In particular, when the growth substrate 501 is sapphire and SiC, it is preferable to perform the laser lift-off method. That is, when the growth substrate 501 is focused and irradiated with an excimer laser beam having a predetermined wavelength, the n-type nitride cladding layer 502 including the growth substrate 501 and the buffer layer may be formed. Thermal energy is concentrated at the interface, so that the interface of the n-type nitride semiconductor 502 including the buffer layer is thermally chemically decomposed into gallium (Ga) and nitrogen (N) molecules, and at the moment where the laser beam passes. Separation of the growth substrate 501 takes place.

FIG. 28 is a cross-sectional view illustrating a process of forming surface irregularities on an upper surface of an n-type nitride cladding layer exposed to air as a step of manufacturing a vertical light emitting diode device.

Surface irregularities 900 are formed on the n-type nitride based cladding layer 502 exposed to the atmosphere to form a structural shape. The introduction of the surface irregularities 900 may greatly help to emit light generated in the nitride based active layer 503 to the outside, thereby significantly improving the external light emitting efficiency of the vertical light emitting diode device.

Here, the surface unevenness 900 may be formed by using a wet solution to form a pattern having no regularity, or by forming a pattern by various lithography processes, and then forming a bend on the surface of the chip through an etching process. I use it.

29 is a cross-sectional view illustrating a process of forming an n-type ohmic contact electrode structure on a top surface of an n-type nitride cladding layer on which surface irregularities are formed as a step of manufacturing a vertical structure light emitting diode device.

An n-type ohmic contact electrode structure 1000 is formed on an upper surface of the n-type nitride cladding layer 502 into which the surface irregularities 900 are introduced. Here, the n-type ohmic contact electrode structure 1000 is formed in a partial region or the entire region by using a mask. In particular, the position of the n-type ohmic contact electrode structure 1000 formed on the n-type nitride-based cladding layer 502 is opposite to the current blocking area in the p-type ohmic contact electrode layer 510.

30 is a cross-sectional view illustrating a process of cutting a vertical light emitting diode device in a vertical direction.

The first conductive wafer bonding layer 602, the first electrical conductor 601, the third conductive wafer bonding layers 604 and 606, and the second electrical conductor 605 to fabricate a completely unified vertical structure light emitting diode device. The first conductive wafer bonding layers 607 and 706 and the second sacrificial separation layer 705 are cut 1100 in the vertical direction. Here, the second wafer plate 704, which is the temporary substrate, is performed until it is exposed to the atmosphere.

31 is a final step of manufacturing a vertical light emitting diode device, and after separating the vertical light emitting diode device from the second wafer plate, which is the temporary substrate, a p-type ohmic contact electrode sphere and a die bonding layer on the rear surface of the second electric conductor. Is a cross-sectional view.

After lifting off a plurality of vertical structure light emitting diode elements unified from the second wafer plate 704 which is the temporary substrate, the p-type ohmic contact electrode 1200 is formed on the rear surface of the second electric conductor 605. And a die bonding layer 1300 is formed. The process of separating the second wafer plate 704, which is the temporary substrate, uses thermo-chemical decomposition, wet etching, or chemical-mechanical polishing (CMP), mechanical polishing, or the like using a laser beam having strong energy.

32 is a cross-sectional view illustrating a vertical structure light emitting diode device using a single crystal group III-nitride semiconductor manufactured according to the present invention.

Referring to FIG. 32A, a light emitting structure for a light emitting diode device, which is structurally and electrically connected by two conductive wafer bonding layers 508 and 602, is formed on an upper surface of a heat sink support O having a laminate structure. Here, the p-type ohmic contact electrode layer 510 and the reflective ohmic contact electrode layer 511 are formed between the p-type nitride cladding layer 504 and the two conductive wafer bonding layers 508 and 602 of the light emitting structure. Vertically structured light emitting diode devices excellent in electrical and optical characteristics can be manufactured. Furthermore, the p-type ohmic contact electrode layer 410 includes a current blocking area, so that the p-type ohmic contact electrode structure 1200 connected to the n-type ohmic contact electrode structure 1000 and the die bonding layer 1300. When the external current is injected through it can avoid the current concentration around the n-type ohmic contact electrode structure 1000.

In addition, since the light emitting structure is completely protected from external conductive materials and moisture by the two device passivation layers 509 and 800, high device reliability can be ensured. In particular, the second device passivation layer 800 is in contact with the first conductive wafer bonding layer 602 on the top surface of the heat sink support O of the laminate structure.

As another vertical light emitting diode device manufactured according to the present invention, referring to FIG. 32B, structurally and electrically connected to a top surface of a heat sink support O of a laminate structure by two conductive wafer bonding layers 508 and 602. A light emitting structure for a light emitting diode device is formed. Here, the p-type ohmic contact electrode layer 510 and the reflective ohmic contact electrode layer 511 are formed between the p-type nitride cladding layer 504 and the two conductive wafer bonding layers 508 and 602 of the light emitting structure. Vertical and light emitting diode devices excellent in electrical and optical characteristics can be manufactured. Furthermore, the p-type ohmic contact electrode layer 410 includes a current blocking area, so that the p-type ohmic contact electrode structure 1200 connected to the n-type ohmic contact electrode structure 1000 and the die bonding layer 1300. When the external current is injected through the current concentration around the n-type right contact electrode structure 1000 can be avoided.

In addition, since the light emitting structure is completely protected from external conductive materials and moisture by the two device passivation layers 509 and 800, high device reliability can be ensured. In particular, the second device passivation layer 800 is separated from the first conductive wafer bonding layer 602 on the top surface of the heat sink support O of the laminate structure.

On the other hand, while the present invention has been shown and described with respect to specific preferred embodiments, various modifications and variations of the present invention without departing from the spirit or field of the invention provided by the claims below It will be readily apparent to one of ordinary skill in the art that it can be used.

1 is a cross-sectional view showing a light emitting diode device having a group III nitride-based horizontal structure in a unit chip form according to the prior art;

FIG. 2 is a view illustrating a process of manufacturing a group III nitride-based vertical structure light emitting diode device in a unit chip form according to the prior art; FIG.

3 is a diagram illustrating a process of manufacturing a group III nitride-based vertical structure light emitting diode device in a unit chip form according to the prior art;

4 is a schematic cross-sectional view showing a process for manufacturing a vertical structure light emitting device using a group III nitride semiconductor through a wafer bonding process proposed by the present invention.

5 to 18 are cross-sectional views illustrating a manufacturing process of a vertical light emitting diode device as a first embodiment according to the present invention.

19 to 31 are cross-sectional views illustrating a process of manufacturing a vertical light emitting diode device as a second embodiment according to the present invention.

32 is a cross-sectional view illustrating a vertical structure light emitting diode device using a single crystal group III-nitride semiconductor manufactured according to the present invention.

Claims (26)

an n-type ohmic contact electrode structure; A light emitting structure including an n-type nitride cladding layer, a nitride-based active layer, and a p-type nitride cladding layer formed on the bottom of the n-type ohmic contact electrode structure; A p-type ohmic contact electrode layer and a first device passivation layer including a current blocking area formed on a bottom surface of the light emitting structure; A reflective ohmic contact electrode layer formed on a lower surface of the p-type ohmic contact electrode layer and the first device passivation layer; A conductive wafer bonding layer formed on a lower surface of the reflective ohmic contact electrode layer; A second device passivation layer surrounding the light emitting structure, the p-type ohmic contact electrode layer, the first device passivation layer, the reflective ohmic contact electrode layer, and the conductive wafer bonding layer; A heatsink support having a laminate structure formed on a lower surface of the conductive wafer bonding layer; And a p-type ohmic contact electrode structure and a die bonding layer formed on the bottom surface of the heat sink support of the laminate structure. The method of claim 1, The p-type nitride cladding layer has a superlattice structure, a surface formed of n-type InGaN, GaN, AlInN, AlN, InN, AlGaN, p-type InGaN, AlInN, InN, AlGaN, or nitrogen polarity. A group III nitride semiconductor vertical structure light emitting diode device comprising a surface modification layer which is a group III nitride having a nitrogen-polar surface. The method of claim 2, The superlattice structure is a group III nitride semiconductor vertical structure light emitting diode device comprising a nitride or carbon nitride containing a group 2, 3, or 4 element element. The method of claim 1, The p-type ohmic contact electrode layer is a group III-nitride-based semiconductor vertical structure light emitting diode device, characterized in that it is optically a transparent member having a transmittance of 75% or more or a reflector having a reflectance of 80% or more. The method of claim 1, The group blocking group of the current blocking region included in the p-type ohmic contact electrode layer is formed of an air state, an electrically insulating material, or a material forming a schottky contact interface with the p-type nitride semiconductor. Semiconductor vertical structure light emitting diode device. The method of claim 1, And the reflective ohmic contact electrode layer is wider than the p-type ohmic contact electrode layer having a predetermined area. The method of claim 1, A group III-nitride semiconductor vertical structure light emitting diode device characterized in that a side surface of a light emitting structure composed of an n-type nitride cladding layer, a nitride-based active layer, and a p-type nitride cladding layer is protected by two element passivation layers as insulator films. . The method of claim 1, The laminate heatsink support is a structure in which two machined electrical conductors are joined by a conductive wafer bonding layer, and the electrical conductors are not limited to any materials as long as they have excellent thermal and electrical conductivity. A group III nitride semiconductor vertical structure light emitting diode device. The method of claim 8, The electrical conductors of the laminate heatsink support are Si, SiGe, ZnO, GaN, AlSiC, GaAs substrates, and Cu, Ni, Ag, Al, Nb, Ta, Ti, Au, Pd, Pd, W components. A group III-nitride semiconductor vertical structure light emitting diode device, characterized in that the metal, alloy, or solid solution composed of at least one of the above. The method of claim 8, The electrical conductor constituting the laminate heatsink support has a group, group III, nitride-based semiconductor light emitting structure characterized by having a sheet, disk, or foil shape having a thickness of 1 mm or less. Diode elements. The method of claim 1, A group III-nitride semiconductor vertical structure light emitting diode device, characterized in that the conductive wafer bonding layer is formed of a single layer or a double layer or more multilayered structure that forms a dense bonding force under a constant pressure and at least 300 ° C. or higher temperature conditions. The method of claim 1, The conductive wafer bonding layer is Au, Ni, Cu, Ti, Ag, Al, Si, Ge, Pt, Pd, Rh, W, Mo, V, Sc, Hf, Ir, Re, Co, Zr, Ru, Ta, A group III-nitride semiconductor vertical structure light emitting diode device characterized by having a metal, an alloy, or a solid solution material containing at least one of Nb, Mn, Mn, Cr, and rare earth metals. Performing an isolating process on a light emitting structure for a light emitting diode device grown on an upper surface of the growth substrate with a predetermined area; Forming a p-type ohmic contact electrode layer and a first device passivation layer on the light emitting structure for the light emitting diode device which has undergone the islanding process; Forming a reflective ohmic contact electrode layer on top of the p-type ohmic contact electrode layer and the first device passivation layer; Forming a first conductive wafer bonding layer on an upper surface of the reflective ohmic contact electrode layer; Forming first and second conductive wafer bonding layers on upper and lower surfaces of the first electrical conductor, respectively; Sequentially forming a first sacrificial separation layer and a second conductive wafer bonding layer on an upper surface of the first wafer plate; Bonding the growth substrate and the wafer plate to upper and lower surfaces of the first and second conductive wafer bonding layers on the upper and lower surfaces of the first electrical conductor to form a first sandwich composite; Separating the first wafer plate from the first sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Removing a second conductive wafer bonding layer from the first sandwich composite, and forming a third conductive wafer bonding layer; Forming third and fourth conductive wafer bonding layers on upper and lower surfaces of the second electrical conductor, respectively; Sequentially forming a second sacrificial separation layer and a fourth conductive wafer bonding layer on an upper surface of the second wafer plate; Bonding the first sandwich composite and the second wafer plate to upper surfaces of the third and fourth conductive wafer bonding layers on the upper and lower surfaces of the second electrical conductor to form a second sandwich composite; Separating the growth substrate from the second sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Etching the n-type nitride clad layer to be exposed to the atmosphere in the second sandwich composite from which the growth substrate is separated; Forming a second device passivation layer on the top and side surfaces of the islanded light emitting structure; Forming surface irregularities on an upper surface of the n-type nitride clad layer exposed to the air; Forming an n-type ohmic contact electrode structure on an upper surface of the n-type nitride clad layer on which the surface irregularities are formed; Performing an etching and cutting process in a vertical direction to an upper surface of the second wafer plate for the unitary LED chip; Separating the second wafer plate using a laser lift off, mechanical polishing, or etching process; And Forming a p-type ohmic contact electrode structure and a die bonding layer on a lower surface of the second electric conductor exposed to the atmosphere; The method of claim 13, The first and second wafer plates, which are temporary substrates, preferentially use the same material as the light emitting structure growth substrate for the light emitting diode device, and any material may be used as long as the difference in thermal expansion coefficient with the growth substrate is 2 ppm / ° C. or less. A method for manufacturing a group III nitride semiconductor vertical structure light emitting diode device without limitation. The method of claim 13, The first and second sacrificial separation layers formed on the upper surfaces of the first and second wafer plates, which are temporary substrates, include a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, and Ti. A method for producing a group III nitride semiconductor vertical structure light emitting diode device, characterized by consisting of ITO, PZT, and SU-8. The method of claim 13, The process of forming the first and second sandwich composites is preferably carried out in a vacuum, nitrogen (N 2), argon (Ar) atmosphere, which is tightly bonded under a constant pressure and at least 300 ° C. or higher temperature. Is a group III-nitride semiconductor vertical structure light emitting diode device in which oxygen (O 2) gas is added. The method of claim 13, After depositing the n-type ohmic contact electrode structure, the p-type ohmic contact electrode structure, the p-type ohmic contact electrode layer, the reflective ohmic contact electrode layer, or the conductive wafer bonding layer, in some cases, heat treatment to improve mechanical, electrical, or optical properties. A group 3 nitride-based semiconductor vertical structure light emitting diode device manufacturing method characterized by performing a. The method of claim 13, And a thickness of the first device passivation layer and the second device passivation layer is 10 to 100 nm and 100 to 1000 nm, respectively. The method of claim 13, In the manufacture of optoelectronics and electronics composed of group III nitride semiconductors other than the group III nitride semiconductors on the upper surface of the heat sink support of the laminate structure, the wafer of the present invention A manufacturing method that applies various techniques related to the bonding process. Performing an isolating process on a light emitting structure for a light emitting diode device grown on an upper surface of the growth substrate with a predetermined area; Forming a p-type ohmic contact electrode layer and a first device passivation layer on the light emitting structure for the light emitting diode device having undergone the islanding process; Forming a reflective ohmic contact electrode layer on top of the p-type ohmic contact electrode layer and the first device passivation layer; Forming a second device passivation layer on an upper surface or a side surface of the p-type ohmic contact electrode layer, the first device passivation layer, and the reflective ohmic contact electrode layer; Forming a first conductive wafer bonding layer on an upper surface of the reflective ohmic contact electrode layer; Forming first and second conductive wafer bonding layers on upper and lower surfaces of the first electrical conductor, respectively; Sequentially forming a first sacrificial separation layer and a second conductive wafer bonding layer on an upper surface of the first wafer plate; Bonding the growth substrate and the first wafer plate to upper and lower surfaces of the first and second conductive wafer bonding layers on the upper and lower surfaces of the first electrical conductor to form a first sandwich composite; Separating the first wafer plate from the first sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Removing a second conductive wafer bonding layer from the first sandwich composite, and forming a third conductive wafer bonding layer; Forming third and fourth conductive wafer bonding layers on upper and lower surfaces of the second electrical conductor, respectively; Sequentially forming a second sacrificial separation layer and a fourth conductive wafer bonding layer on an upper surface of the second wafer plate; Bonding the first sandwich composite and the second wafer plate to upper surfaces of the third and fourth conductive wafer bonding layers on the upper and lower surfaces of the second electrical conductor to form a second sandwich composite; Separating the growth substrate from the second sandwich composite using laser lift off, mechanical polishing, or etching process techniques; Etching the n-type nitride clad layer to be exposed to the atmosphere in the second sandwich composite from which the growth substrate is separated; Forming surface irregularities on an upper surface of the n-type nitride clad layer exposed to the air; Forming an n-type ohmic contact electrode structure on an upper surface of the n-type nitride clad layer on which the surface irregularities are formed; Performing an etching and cutting process in a vertical direction to an upper surface of the second wafer plate for the unitary LED chip; Separating the second wafer plate using a laser lift off, mechanical polishing, or etching process; And Forming a p-type ohmic contact electrode structure and a die bonding layer on a lower surface of the second electrical conductor exposed to the atmosphere; The method of claim 20, The first and second wafer plates, which are temporary substrates, preferentially use the same material as the light emitting structure growth substrate for the light emitting diode device, and any material may be used as long as the difference in thermal expansion coefficient with the growth substrate is 2 ppm / ° C. or less. A method for manufacturing a group III nitride semiconductor vertical structure light emitting diode device without limitation. The method of claim 20, The first and second sacrificial separation layers formed on the upper surfaces of the first and second wafer plates, which are temporary substrates, include a Group 2-6 compound including ZnO, a Group 3-5 compound including GaN, Al, Au, Ag, Cr, and Ti. A method for producing a group III nitride semiconductor vertical structure light emitting diode device, characterized by consisting of ITO, PZT, and SU-8. The method of claim 20, The process of forming the first and second sandwich composites is preferably carried out in a vacuum, nitrogen (N 2), argon (Ar) atmosphere, which is tightly bonded under a constant pressure and at least 300 ° C. or higher temperature. Is a group III-nitride semiconductor vertical structure light emitting diode device in which oxygen (O 2) gas is added. The method of claim 20, After depositing the n-type ohmic contact electrode structure, the p-type ohmic contact electrode structure, the p-type ohmic contact electrode layer, the reflective ohmic contact electrode layer, or the conductive wafer bonding layer, in some cases, heat treatment to improve mechanical, electrical, or optical properties. A group 3 nitride-based semiconductor vertical structure light emitting diode device manufacturing method characterized by performing a. The method of claim 20, And a thickness of the first device passivation layer and the second device passivation layer is 10 to 100 nm and 100 to 1000 nm, respectively. The method of claim 20, In the manufacture of optoelectronics and electronics composed of group III nitride semiconductors other than the group III nitride semiconductors on the upper surface of the heat sink support of the laminate structure, the wafer of the present invention A manufacturing method that applies various techniques related to the bonding process.

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