JP2010093186A - Method of manufacturing gallium nitride-based compound semiconductor light-emitting element, layered structure of gallium nitride-based compound semiconductor element, gallium nitride-based compound semiconductor light-emitting element, and lamp - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a method of manufacturing a gallium nitride-based compound semiconductor light-emitting element, which can prevent a buffer layer from disappearing in a formation process of a semiconductor layer, can remove a substrate from a compound semiconductor layer with a simple method, and can provide the light-emitting element excelling in a luminescent characteristic with a good yield and high efficiency; a layered structure of a gallium nitride-based compound semiconductor element; and a gallium nitride-based compound semiconductor light-emitting element. <P>SOLUTION: The method of manufacturing the gallium nitride-based compound semiconductor light-emitting element includes: a buffer layer formation step of laminating a ZnO buffer layer 22 and an AlN buffer layer 23 on a substrate 21 on this order; a semiconductor layer formation step of forming a semiconductor layer formed of a gallium nitride-based compound on the AlN buffer layer 23; and a removal step of removing the substrate 21 by removing the ZnO buffer layer 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a gallium nitride-based compound semiconductor light-emitting device suitably used for a light-emitting diode (LED), a laser diode (LD), an electronic device, and the like, a laminated structure of a gallium nitride-based compound semiconductor device, and a gallium nitride-based compound The present invention relates to a semiconductor light emitting element and a lamp.

  Group III nitride semiconductors such as gallium nitride compounds have a direct transition type band gap of energy corresponding to the range of visible light to ultraviolet light, and are excellent in luminous efficiency. Have been commercialized as semiconductor light emitting devices such as laser diodes (LD) and the like, and are used in various applications. Even when used in an electronic device, the group III nitride semiconductor can provide an electronic device having superior characteristics as compared to the case of using a conventional group III-V compound semiconductor.

Conventionally, as a group III nitride semiconductor single crystal wafer, a method in which crystals are grown on single crystal wafers of different materials is generally used. There is a large lattice mismatch between such a heterogeneous substrate and a group III nitride semiconductor crystal epitaxially grown thereon. For example, when gallium nitride (GaN) is grown on a sapphire (Al ₂ O ₃ ) substrate, there is a 16% lattice mismatch between them, and when gallium nitride is grown on a SiC substrate. There is a 6% lattice mismatch between the two. In general, when there is a large lattice mismatch as described above, it is difficult to epitaxially grow a crystal directly on a substrate, and a crystal with good crystallinity cannot be obtained even when grown. There is.

  In addition, when a sapphire substrate is used for a light emitting element, there are problems such as an insulative material and low thermal conductivity in addition to the above-described lattice mismatch problem. For example, since the sapphire substrate is an insulating substrate, a so-called upper and lower electrode structure in which electrodes are formed on the upper and lower sides of a chip as used in a general LED cannot be employed. For this reason, there is a problem that there is a limit to downsizing the light emitting element chip to a certain size or less. Further, since the sapphire substrate has low thermal conductivity, it is difficult to dissipate heat generated by the applied electric power, and there is a problem that the temperature of the chip rises and the light emission characteristics are deteriorated.

  In order to solve such a problem, for example, a technique for producing an LED by peeling a sapphire substrate from a compound semiconductor layer has been proposed. For example, a method of detaching a sapphire substrate by irradiating the back surface of the polished sapphire substrate with laser, absorbing the laser in a layer where dislocations are concentrated at the interface between the sapphire substrate and GaN, and generating heat to break the substrate. Etc. have been proposed. However, in such a method, since it is difficult to control the sapphire substrate to be peeled uniformly, there is a problem that the characteristics and yield of the light emitting element are not stable. In addition, since damage is caused by the crystal being broken by the laser, there is a problem that characteristics of the light-emitting element are deteriorated. For this reason, development of a buffer layer for eliminating lattice mismatch between the sapphire substrate and GaN is required, and a method for peeling the sapphire substrate from GaN without using a method having a large impact such as laser irradiation is required. .

The use of a buffer layer made of ZnO has been proposed as a technique that can achieve both of the above-described elimination of lattice mismatch between a sapphire substrate and GaN and exfoliation of the sapphire substrate without laser irradiation.
First, the buffer layer is configured as a double buffer layer, ZnO is used as a first buffer layer of low-temperature growth formed on the substrate, and Ga and In are contained as a second buffer layer of substantially single crystal thereon. It has been proposed to use non-nitrides (see, for example, Patent Documents 1 and 2).

Further, a technique has been proposed in which a spacer layer is formed on a substrate, a compound semiconductor layer is formed on the spacer layer, and then the substrate is peeled off by absorbing light by light irradiation (for example, a patent) References 3, 4) According to Patent Documents 3 and 4, as the spacer layer, GaN or Al _0.1 is formed on a ZnO film formed by sputtering on a sapphire substrate by using a metal organic chemical vapor deposition (MOCVD) method. It is described that Ga _0.9 N is formed. Thus, according to Patent Documents 3 and 4, it is a technique for stacking nitride on ZnO by a method such as MOCVD.

However, ZnO has low chemical stability at high temperatures, and when exposed to an environment of a film forming method using NH ₃ or the like, there is a characteristic that a reaction action occurs suddenly and crystallinity is lowered. For this reason, when the techniques described in Patent Documents 1 to 4 are used, there is a problem that the crystallinity of ZnO is lowered and further lost in the step of forming each layer on ZnO.

On the other hand, a Zn _1-x Mg _x O (0 ≦ x ≦ 0.3) buffer layer is formed on the substrate, and a nitride buffer layer is formed thereon so as to have a cation polarity. A technique for growing a nitride layer by a method and manufacturing a GaN substrate by lift-off has been proposed (see, for example, Patent Document 5). Patent Document 5 describes that a ZnO buffer layer is formed by a molecular beam epitaxy (MBE) method, and a GaN buffer layer is formed thereon by an MBE method. As described above, since the nitride buffer layer can be formed on the ZnO buffer layer at a low temperature by using the MBE method, it is possible to prevent the disappearance of the ZnO buffer layer when the nitride buffer layer is formed. It becomes.

However, when each buffer layer is formed using the MBE method as in the technique described in Patent Document 5, since the MBE method is difficult to maintain an ultra-high vacuum state and is not a film formation method suitable for mass production, the manufacturing efficiency is large. There is a problem of lowering.
Further, as in Patent Document 5, when a base layer made of GaN is grown using the HVPE method, a crystal with good crystallinity cannot be obtained unless the film thickness is increased. There is a problem that becomes thicker. When the base layer is formed thick in this manner, the warpage of the substrate becomes large, so that subsequent process processing becomes difficult, and it takes a long time for film formation, so it is difficult to ensure high productivity. Problem arises.

In addition, a technique for peeling a substrate by dissolving and removing a ZnO layer formed on the substrate with an etching solution has been proposed (see, for example, Patent Document 6).
However, in the technique described in Patent Document 6, since the ZnO layer is formed on the AlN buffer layer and the compound semiconductor layer made of GaN is formed thereon, the ZnO layer is exposed to a high temperature during the GaN film formation. The For this reason, similarly to the above, the crystallinity of the ZnO layer is lowered in the compound semiconductor layer forming step, and there is a problem that ZnO may disappear in some cases.
JP 2000-133842 A JP 2004-48076 A JP 2003-218470 A JP 2007-13191 A JP 2008-74671 A JP 2007-95845 A

The present invention has been made in view of the above problems, and the buffer layer is not lost in the process of forming the semiconductor layer, and the substrate can be peeled off from the compound semiconductor layer by a simple method, and has excellent light emitting characteristics. It is an object of the present invention to provide a method for manufacturing a gallium nitride compound semiconductor light emitting device that can obtain the light emitting device with high yield and high efficiency, a laminated structure of the gallium nitride compound semiconductor device, and a gallium nitride compound semiconductor light emitting device.
Furthermore, it aims at providing the lamp | ramp which is excellent in the light emission characteristic using said gallium nitride type compound semiconductor light-emitting device.

The inventors of the present invention have intensively studied in order to solve the above problems, and have completed the present invention.
That is, the present invention relates to the following.

[1] A buffer layer forming step of laminating a ZnO buffer layer and an AlN buffer layer in this order on a substrate; a semiconductor layer forming step of forming a semiconductor layer made of a gallium nitride compound on the AlN buffer layer; And a removing step of peeling off the substrate by removing the ZnO buffer layer.
[2] In the buffer layer forming step, the ZnO buffer layer is formed by using any one of a molecular beam epitaxy (MBE) method, a pulse laser deposition (PLD) method, and a sputtering method. The method for producing a gallium nitride-based compound semiconductor light-emitting device according to [1] above.
[3] The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to the above [2], wherein the buffer layer forming step forms the ZnO buffer layer by a sputtering method.
[4] In the buffer layer forming step, the AlN buffer layer is formed using any one of a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and a sputtering method. The method for producing a gallium nitride-based compound semiconductor light-emitting device according to any one of the above [1] to [3].
[5] The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to the above [4], wherein the buffer layer forming step forms the AlN buffer layer using a sputtering method.
[6] The above [4] or [5], wherein the buffer layer forming step forms the AlN buffer layer at a temperature of 600 ° C. or lower using nitrogen (N ₂ ) gas as a nitrogen source. The manufacturing method of the gallium nitride type compound semiconductor light-emitting device of description.
[7] In the buffer layer forming step, the AlN buffer layer is formed on the substrate so that the AlN buffer layer is larger than the ZnO buffer layer in plan view. The method for producing a gallium nitride-based compound semiconductor light-emitting element according to any one of the above [1] to [6], wherein the gallium nitride-based compound semiconductor light-emitting element is formed so as to cover the gallium nitride compound semiconductor light-emitting element.

[8] The gallium nitride-based compound semiconductor light-emitting element according to any one of [1] to [7], wherein in the removing step, the ZnO buffer layer is dissolved and removed using an etching method. Production method.
[9] The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to the above [8], wherein the removing step includes dissolving and removing the ZnO buffer layer by an etching method using HCl or oxalic acid.
[10] In the semiconductor layer forming step, the semiconductor layer is formed by sequentially stacking an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the AlN buffer layer. The manufacturing method of the gallium nitride type compound semiconductor light-emitting device in any one of-[9].
[11] The gallium nitride-based compound semiconductor light-emitting element according to the above [10], wherein the semiconductor layer forming step further includes forming a base layer between the AlN buffer layer and the n-type semiconductor layer. Manufacturing method.
[12] The gallium nitride compound semiconductor light-emitting element according to the above [11], wherein the underlayer and / or the n-type semiconductor layer is formed using a metal organic chemical vapor deposition (MOCVD) method. Manufacturing method.
[13] The method for producing a gallium nitride-based compound semiconductor light-emitting element according to the above [11] or [12], wherein a total film thickness of the n-type semiconductor layer and the base layer is 15 μm or less. .
[14] The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to the above [11] or [12], wherein a total film thickness of the n-type semiconductor layer and the base layer is 10 μm or less. .
[15] The method for producing a gallium nitride-based compound semiconductor light-emitting element according to the above [11] or [12], wherein a total film thickness of the n-type semiconductor layer and the base layer is 4 μm or less. .

[16] A support substrate bonding step for bonding a support substrate made of an oxide or nitride of Si to the p-type semiconductor layer side of the semiconductor layer is provided between the semiconductor layer forming step and the removing step. The method for producing a gallium nitride-based compound semiconductor light-emitting element according to any one of the above [10] to [15], wherein:
[17] After the removing step, the semiconductor layer is formed by forming a negative electrode on the n-type semiconductor layer side of the semiconductor layer, and then attaching a temporary adhesive substrate to the negative electrode, and then peeling the support substrate. The method further comprises an electrode forming step of exposing the p-type semiconductor layer side, forming a positive electrode on the exposed p-type semiconductor layer, and then peeling the temporary adhesive substrate from the negative electrode. [16] The method for producing a gallium nitride compound semiconductor light-emitting device according to [16].
[18] A support substrate bonding step of bonding a support substrate made of Si to the p-type semiconductor layer side of the semiconductor layer between the semiconductor layer forming step and the removing step is provided. The method for producing a gallium nitride-based compound semiconductor light-emitting element according to any one of [10] to [15] above.
[19] The plating process for forming a positive electrode made of metal plating on the p-type semiconductor layer side of the semiconductor layer between the semiconductor layer forming step and the removing step. [10] The method for producing a gallium nitride compound semiconductor light-emitting device according to any one of [15].
[20] The gallium nitride according to the above [18] or [19], further comprising a negative electrode forming step of forming a negative electrode on the n-type semiconductor layer side of the semiconductor layer after the removing step. Of manufacturing a compound semiconductor light emitting device.

[21] A substrate, a ZnO buffer layer and an AlN buffer layer that are sequentially stacked on the substrate, and a semiconductor layer formed on the AlN buffer layer and made of a gallium nitride compound, A laminated structure of gallium nitride compound semiconductor elements.
[22] The laminated structure of a gallium nitride-based compound semiconductor element according to [21], wherein the substrate is made of any one of sapphire, silicon, SiC, and spinel.
[23] The stacked structure of a gallium nitride-based compound semiconductor device according to [21] or [22], wherein the ZnO buffer layer is made of single-crystal ZnO.
[24] The stacked structure of a gallium nitride compound semiconductor device according to any one of [21] to [23], wherein the surface of the ZnO buffer layer has a Zn polarity.
[25] The laminated structure of the gallium nitride-based compound semiconductor element according to any one of [21] to [24], wherein the ZnO buffer layer has a thickness in a range of 10 to 1000 nm.
[26] The laminated structure of a gallium nitride compound semiconductor device according to any one of [21] to [25], wherein the AlN buffer layer is made of single crystal AlN.
[27] The stacked structure of gallium nitride-based compound semiconductor elements according to any one of [21] to [26], wherein the AlN buffer layer is made of polycrystalline AlN having columnar crystals.
[28] The laminated structure of the gallium nitride-based compound semiconductor element according to any one of [21] to [27], wherein the thickness of the AlN buffer layer is in a range of 10 to 100 nm.
[29] On the substrate, the AlN buffer layer is formed larger than the ZnO buffer layer in plan view, and the AlN buffer layer is formed so as to cover the surface and side surfaces of the ZnO buffer layer. The laminated structure of gallium nitride-based compound semiconductor elements according to any one of the above [21] to [28], wherein
[30] The above-mentioned [21] to [29], wherein the semiconductor layer is formed by sequentially laminating an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the AlN buffer layer. Laminated structure of gallium nitride compound semiconductor elements.
[31] The gallium nitride compound semiconductor device according to [30], wherein the semiconductor layer further includes a base layer provided between the AlN buffer layer and the n-type semiconductor layer. Laminated structure.
[32] The laminated structure of the gallium nitride-based compound semiconductor element according to [31], wherein a total film thickness of the base layer and the n-type semiconductor layer is 1512 μm or less.
[33] The stacked structure of a gallium nitride-based compound semiconductor element according to the above [31], wherein a total film thickness of the base layer and the n-type semiconductor layer is 10 μm or less.
[34] The stacked structure of gallium nitride compound semiconductor elements according to [31] above, wherein a total film thickness of the base layer and the n-type semiconductor layer is 4 μm or less.

[35] The AlN buffer layer is formed by removing the ZnO buffer layer and the substrate provided in the stacked structure of the gallium nitride compound semiconductor device according to any one of [30] to [34]. A layered structure having an exposed configuration is used, and a negative electrode is provided on the n-type semiconductor layer exposed by removing at least a part of the AlN buffer layer, and a positive electrode is provided on the p-type semiconductor layer. A gallium nitride-based compound semiconductor light-emitting element characterized by being provided.
[36] A gallium nitride compound semiconductor light-emitting device obtained by the manufacturing method according to any one of [1] to [20].
[37] A lamp comprising the gallium nitride-based compound semiconductor light-emitting device according to [35] or [36].

According to the method for manufacturing a gallium nitride compound semiconductor light emitting device of the present invention, a buffer layer forming step of laminating a ZnO buffer layer and an AlN buffer layer in this order on a substrate, and a gallium nitride compound on the AlN buffer layer. a semiconductor layer forming step of forming a semiconductor layer made of, since method and a removing step of removing the substrate by etching away the ZnO buffer layer, a semiconductor layer forming step, or using NH _3, and the film forming process by the high-temperature Even when the step is performed, the crystallinity of the ZnO buffer layer is not reduced, and disappearance due to dissolution does not occur. Further, the substrate can be easily peeled by etching away the ZnO buffer layer. Thereby, it becomes possible to manufacture a gallium nitride compound semiconductor light emitting device having excellent light emitting characteristics with high yield and high productivity.

  Further, according to the laminated structure of the gallium nitride-based compound semiconductor of the present invention, the gallium nitride is formed on the substrate, the ZnO buffer layer and the AlN buffer layer that are sequentially stacked on the substrate, and the AlN buffer layer. Since it has a laminated structure including a semiconductor layer made of a compound, it is excellent in crystallinity of each layer and enables easy peeling of the substrate. By manufacturing a gallium nitride-based compound semiconductor light-emitting device using such a stacked structure, it becomes possible to obtain a gallium nitride-based compound semiconductor light-emitting device that is excellent in yield and productivity and excellent in light emission characteristics.

  Further, according to the gallium nitride compound semiconductor light emitting device of the present invention, the gallium nitride compound semiconductor light emitting device of the present invention is manufactured by the method for manufacturing a gallium nitride compound semiconductor light emitting device of the present invention. By removing the ZnO buffer layer and the substrate, a stacked structure in which the AlN buffer layer is exposed is used, and on the n-type semiconductor layer exposed by removing at least a part of the AlN buffer layer. Since the negative electrode is provided and the positive electrode is provided on the p-type semiconductor layer, the emission characteristics and the production efficiency are excellent.

  Furthermore, since the lamp of the present invention uses the gallium nitride-based compound semiconductor light-emitting element of the present invention, it has excellent light emission characteristics.

Hereinafter, a method for manufacturing a gallium nitride-based compound semiconductor light-emitting device (hereinafter sometimes abbreviated as a light-emitting device) according to the present invention, a laminated structure of gallium nitride-based compound semiconductor devices (hereinafter sometimes abbreviated as a semiconductor laminated structure). ), A gallium nitride compound semiconductor light emitting device, and an embodiment of a lamp will be described with reference to the drawings as appropriate.
FIG. 1 is a schematic cross-sectional view showing an example of a gallium nitride-based compound semiconductor light-emitting device according to this embodiment. FIG. 2 is a schematic cross-sectional view of a laminated structure of the gallium nitride-based compound semiconductor according to this embodiment. FIG. 13 and FIG. 14 are schematic cross-sectional views showing other examples of the light-emitting element, and FIG. 15 shows the embodiment of the present invention. FIG. 16 is a measurement graph of an X-ray peak value of the laminated structure of the gallium nitride compound semiconductor according to the present embodiment. The drawings referred to in the following description are drawings for explaining a manufacturing method of a gallium nitride compound semiconductor light emitting device, a laminated structure of gallium nitride compound semiconductor devices, a gallium nitride compound semiconductor light emitting device, and a lamp. The size, thickness, dimensions, and the like of each part shown in the drawing are different from the dimensional relationship of an actual gallium nitride-based compound semiconductor light emitting element.

[Gallium nitride compound semiconductor light emitting device]
As shown in FIG. 1, the light-emitting element 1 according to the present embodiment is an upper and lower electrode type, and includes a positive electrode 4, a semiconductor layer 11 disposed on the positive electrode 4, and a negative electrode 9 disposed on the semiconductor layer 11. And is roughly composed of the following. The semiconductor layer 11 is formed by laminating the p-type semiconductor layer 6, the light emitting layer 7, and the n-type semiconductor layer 8 in order from the positive electrode 4 side. In the illustrated light emitting device 1, a reflective p-type electrode layer 5 is further provided between the p-type semiconductor layer 6 and the positive electrode 4.

  The upper surface of the semiconductor layer 11 is a light extraction surface 11a for extracting light from the light emitting layer 7 to the outside, and the negative electrode 9 is formed on the light extraction surface 11a. Further, the light extraction surface 11a is roughened by means such as etching, whereby the light extraction efficiency of the light emitting element 1 is further increased.

Further, in the light emitting device 1 of the example shown in FIG. 1, a protective insulating film 10 made of an insulating material such as SiO ₂ is formed on the side surface 11b of the semiconductor layer 11 and the outer peripheral portion on the light extraction surface 11a side. Yes. By forming such an insulating film 10, for example, even when foreign matter adheres to the side surface 11 b of the semiconductor layer 11, a short circuit between the n-type semiconductor layer 8 and the p-type semiconductor layer 6 due to the foreign matter is prevented.
In the illustrated light-emitting element 1, a gallium nitride compound semiconductor element stacked structure 2 (see FIG. 2A) described later and the light-emitting element between the outer peripheral portion of the light extraction surface 11 a and the insulating film 10. A part of the AlN buffer layer 23 described in the manufacturing method remains.

  The light emitting device 1 of the present embodiment can be obtained by using the semiconductor multilayer structure 2 of the present embodiment as shown in FIG. Specifically, the substrate 21 is peeled off by removing the ZnO buffer layer 22 from the semiconductor multilayer structure 2, and at least a part of the AlN buffer layer 23 is removed. And while providing the negative electrode 9 on the exposed n-type semiconductor layer 8, and providing the positive electrode 4 via the reflective p-type electrode layer 5 in the p-type semiconductor layer 6 side, the light emitting element 1 of this embodiment is obtained. It is done.

The negative electrode (n-type electrode) 9 is in negative contact with the semiconductor layer 11 by making ohmic contact with the n-type semiconductor layer 8 of the semiconductor layer 11. As the negative electrode 9, for example, a three-layer structure including a Cr film in contact with the n-type semiconductor layer 8, a Ti film laminated on the Cr film, and an Au film laminated on the Ti film can be adopted. However, the negative electrode used in the present invention is not limited to such a configuration. For example, the negative electrode may be configured as a multilayer structure of four or more layers in which each film is laminated, or a single layer, a two-layer structure, etc. In addition, the film quality and layer structure of the negative electrode can be appropriately adopted. It is.
As will be described later, the negative electrode 9 is formed by sequentially laminating each film after the light extraction surface 11a is treated with plasma, and thereby an ohmic contact with the n-type semiconductor layer 8 without annealing. Can be obtained.

  For example, when the AlN buffer layer 23 is doped to have conductivity, the negative electrode 9 can be formed in the AlN buffer layer 23 without removing the AlN buffer layer 23. is there.

Next, the positive electrode 4 is a p-type electrode connected to a p-type semiconductor layer 6 described later, and serves as a base of the light-emitting element 1 of the present embodiment. In the example described in the present embodiment, The p-type semiconductor layer 6 is connected via the conductive p-type electrode layer 5.
The material used for the positive electrode 4 is not particularly limited, and electrode materials used in the semiconductor field such as a gallium nitride compound semiconductor light emitting device can be used without any limitation. For example, a metal wafer made of Cu, Al, or the like. Etc. Moreover, as a material used for the positive electrode 4, it is preferable to use a material having low electrical resistance and high thermal conductivity as a material of an electrode (base) of the light emitting element 1 having an upper and lower electrode structure.

  The thickness of the positive electrode 4 made of the material as described above is preferably set to, for example, 100 μm or more and less than 200 μm in consideration of the strength of the semiconductor wafer as a substrate and the splitting property in a dicing process described later. If the thickness of the positive electrode 4 is less than 100 μm, the strength decreases, and if it is 200 μm or more, there is a possibility that division (chip formation) in the dicing process becomes difficult.

  For example, the positive electrode may be configured to be bonded to the p-type semiconductor layer 6 (reflective p-type electrode layer 5) side through a bonding layer such as Ni and Au using a substrate made of Si. . In such a case, in the supporting substrate bonding step provided in the manufacturing method described later, the supporting substrate made of the Si substrate is bonded to the p-type semiconductor layer side and used as the base of the light emitting element without being peeled off. (See the positive electrode 4 in FIG. 1).

The positive electrode can also be configured as a metal layer made of metal plating. In such a case, for example, a seed layer can be provided on the semiconductor layer 11 and the reflective p-type electrode layer 5 side, and a positive electrode made of metal plating can be formed by electroplating using this seed layer as a base. When the positive electrode is made of metal plating, the material is preferably Cu. Cu can be plated at room temperature, is not easily affected by thermal expansion during plating formation, and has a low electrical resistance and high thermal conductivity. Preferred as the material.
Moreover, in this embodiment, the effect that the thermal radiation efficiency of the light emitting element 1 is improved by providing the electrode 4 which has the function as a base | substrate as mentioned above is also acquired.

Next, as described above, the reflective p-type electrode layer 5 is provided between the p-type semiconductor layer 6 provided in the semiconductor layer 11 and the positive electrode 4.
The reflective p-type electrode layer 5 is electrically connected to the positive electrode 4, whereby the positive electrode 4 serves as an extraction electrode for the reflective p-type electrode layer 5. Further, the reflective p-type electrode layer 5, the positive electrode 4, and the negative electrode 9 are arranged on the opposite side in the thickness direction of the semiconductor layer 11. Thereby, the light emitting diode 1 of this embodiment is a light emitting diode having a so-called upper and lower electrode structure.

The reflective p-type electrode layer 5 described in the present embodiment includes an ohmic contact layer in contact with the semiconductor layer 11, a reflective layer in contact with the ohmic contact layer, and an interdiffusion prevention layer in contact with the reflective layer. By providing the reflective layer, the reflective p-type electrode layer 5 is a reflective layer that reflects the light emitted from the light emitting layer 7 toward the light extraction surface 11a.
The reflective p-type electrode layer 5 is formed by, for example, laminating an ohmic contact layer by an RF sputtering method, and laminating the reflective layer and the mutual diffusion prevention layer by using, for example, a DC sputtering method. An ohmic contact with the p-type semiconductor layer 6 can be obtained without application.

  As performance required for the ohmic contact layer, it is essential that the contact resistance with the p-type semiconductor layer 6 is small. From the viewpoint of contact resistance with the p-type semiconductor layer 6, the ohmic contact layer is preferably a platinum group such as Pt, Ru, Os, Rh, Ir, Pd, or Ag, and more preferably Pt, Ir, Rh, or Ru. Pt is particularly preferred. Use of Ag is preferable for obtaining good reflection, but the contact resistance is higher than Pt. Therefore, Ag can be used for applications that do not require such a low contact resistance. The thickness of the ohmic contact layer is preferably 0.1 nm or more in order to stably obtain a low contact resistance. More preferably, it is 1 nm or more, and uniform contact resistance is obtained.

  A reflection layer such as an Ag alloy or an Al alloy is laminated on the ohmic contact layer. Pt, Ir, Rh, Ru, OS, Pd, and the like have a lower reflectance from visible light to ultraviolet region than Ag alloys. Therefore, it is difficult to obtain an element with high output because the light from the light emitting layer 7 is not sufficiently reflected. In this case, it is better to form an ohmic contact layer that is sufficiently thin to transmit light, and to form a reflective layer such as an Ag alloy to obtain reflected light. Can be created. In this case, the film thickness of the ohmic contact layer is preferably 30 nm or less. More preferably, it is 10 nm or less. The thickness of the reflective layer is preferably 0.1 nm or more in order to obtain good reflectance. More preferably, it is 1 nm or more, and uniform adhesion is obtained. The Ag alloy is easy to cause migration, so the thinner one is preferable. Therefore, the film thickness is preferably 200 nm or less.

  The mutual diffusion preventing layer is formed to prevent mutual diffusion between the constituent elements of the reflective layer and the constituent elements of the positive electrode 4. For example, Pt is preferably used as the interdiffusion prevention layer.

Next, the semiconductor layer 11 is roughly composed of the p-type semiconductor layer 6, the light emitting layer 7, and the n-type semiconductor layer 8 as described above.
As a material constituting the p-type semiconductor layer 6, the light emitting layer 7, and the n-type semiconductor layer 8, a well-known semiconductor such as a gallium nitride (GaN) single crystal, a GaP single crystal, a GaAs single crystal, or a ZnO single crystal is used. Although a light emitting material can be used, a gallium nitride compound semiconductor single crystal is preferable in that it can be epitaxially grown on a substrate made of a sapphire single crystal, an SiC single crystal, or the like, which will be described later.

The semiconductor layer of a gallium nitride-based compound semiconductor single crystal, for example, and by the general formula _{Al X Ga Y In Z N 1} -A M A (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1, X + Y + Z = 1, symbol M represents a group V element different from nitrogen (N), and 0 ≦ A <1)), and many GaN-based semiconductors represented by the present invention are also known in the present invention. and the general formula _{Al X Ga Y in Z N 1} -a M a (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1 , including the well-known GaN based semiconductor, X + Y + Z = 1 . the symbol M A GaN-based semiconductor represented by a group V element different from nitrogen (N) and 0 ≦ A <1 can be used without any limitation.

  The n-type semiconductor layer 8 is configured by laminating an n-type contact layer and an n-type cladding layer in contact with the light emitting layer 7. The n-type contact layer can also serve as an underlayer 27 and / or an n-type cladding layer described later.

As an n-type contact layer, an Al _X Ga _1-X N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1) is used in the same manner as the underlayer described later. It is preferable that it is comprised from these. The n-type contact layer is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm. ^If it contains in the density | concentration of ³ , it is preferable at the point of maintenance of favorable ohmic contact with the negative electrode 9, suppression of crack generation, and maintenance of favorable crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge, More preferably, it is Si.
The GaN-based semiconductor constituting the n-type contact layer preferably has the same composition as the underlayer described later, and the total film thickness of the n-type contact layer and the underlayer is 1 to 20 μm, preferably 2 to 15 μm, It is preferable to set in the range of 3 to 12 μm. When the total film thickness of the n-type contact layer and the base layer is in the above range, the crystallinity of the semiconductor is maintained well.

An n-type cladding layer is preferably provided between the n-type contact layer and the light emitting layer 7. This is because deterioration of flatness generated on the surface of the n-type contact layer can be filled. The n-type cladding layer can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. Needless to say, when the n-type cladding layer is formed of GaInN, it is preferably larger than the GaInN band gap of the light emitting layer 7.
The film thickness of the n-type cladding layer is not particularly limited, but is preferably 0.005 to 0.5 μm, more preferably 0.005 to 0.1 μm. The n-type dopant concentration of the n-type cladding layer is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . A dopant concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.

  Further, in the present embodiment, a base layer 27 is provided between the AlN buffer layer 23 and the n-type semiconductor layer 8 as in the semiconductor stacked structure 2A in the example shown in FIG. You can also. By forming the base layer 27 on the AlN buffer layer 23, the crystallinity of the semiconductor layer 11 including the n-type semiconductor layer 8 thereon can be improved.

Underlayer 27 is _{Al X Ga 1-X} N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, and more preferably 0 ≦ x ≦ 0.1) preferably being composed. The film thickness is 0.1 μm or more, preferably 0.5 μm or more, more preferably 1 μm or more. An Al _X Ga _1-X N layer with good crystallinity is more easily obtained when the thickness is increased.

  Further, the film thickness of the underlayer 27 is preferably 15 μm or less, more preferably 10 μm or less, and most preferably 4 μm or less in terms of the total film thickness with the n-type semiconductor layer 8. By making the total film thickness of the underlayer 27 and the n-type semiconductor layer 8 in the vapor range, it is possible to prevent the substrate from warping and to maintain high productivity.

The underlayer 27 may be doped with n-type impurities within the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , but undoped (<1 × 10 ¹⁷ / cm ³ ) is better. This is preferable in terms of maintaining crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge, More preferably, it is Si.

Next, as the light emitting layer 7 stacked below the n-type semiconductor layer 8, light emission made of a GaN-based semiconductor, preferably a Ga _{1- Ins} N (0 <s <0.4) GaN-based semiconductor. Layers are commonly used in the present invention. Although it does not specifically limit as a film thickness of the light emitting layer 7, For example, Preferably it is 1-10 nm, More preferably, it is 2-6 nm. It is preferable in terms of light emission output that the film thickness of the light emitting layer 7 is in the above range.
In addition to the single quantum well (SQW) structure as described above, the light emitting layer 7 uses the Ga _{1 -s} In _s N as a well layer, and Al _c Ga _1-1 having a larger band gap energy than the well layer. _A multiple quantum well (MQW) structure including a _c N (0 ≦ c <0.3) barrier layer may be employed. The well layer and the barrier layer may be doped with impurities.

Next, the p-type semiconductor layer 6 is configured by laminating a p-type cladding layer in contact with the light emitting layer 7 and a p-type contact layer. However, the p-type contact layer may also serve as the p-type cladding layer.
The p-type cladding layer is not particularly limited as long as it has a composition larger than the band gap energy of the light emitting layer 7 and can confine carriers in the light emitting layer 7, but is preferably Al _d Ga _1-d N. (0 <d ≦ 0.4, preferably 0.1 ≦ d ≦ 0.3). When the p-type cladding layer is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer 7. Although the film thickness of a p-type cladding layer is not specifically limited, Preferably it is 1-400 nm, More preferably, it is 5-100 nm. The p-type dopant concentration of the p-type cladding layer is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dopant concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.

The p-type contact layer includes at least Al _e Ga _1-e N (0 ≦ e <0.5, preferably 0 ≦ e ≦ 0.2, more preferably 0 ≦ e ≦ 0.1). It is a semiconductor layer. When the Al composition is within the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the reflective p-type electrode layer 5. When a p-type impurity (dopant) is contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably at a concentration of 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact It is preferable from the standpoints of maintaining the thickness, preventing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned. Although a film thickness is not specifically limited, 0.01-0.5 micrometer is preferable, More preferably, it is 0.05-0.2 micrometer. When the film thickness is within this range, it is preferable in terms of light emission output.

[Laminated structure of gallium nitride compound semiconductor device]
The laminated structure (semiconductor laminated structure) 2 of the gallium nitride-based compound semiconductor element of this embodiment includes a substrate 21 and ZnO that is sequentially laminated on the substrate 21 as shown in the cross-sectional view of FIG. A buffer layer 22 and an AlN buffer layer 23, and a semiconductor layer 11 formed on the AlN buffer layer 23 and made of a gallium nitride compound are provided and schematically configured (see also the example shown in FIG. 2B). .

Further, as described above, by using the stacked structure in which the ZnO buffer layer 22 is removed from the semiconductor stacked structure 2 of the present embodiment as shown in FIG. The light emitting element 1 can be obtained. Specifically, at least a part of the AlN buffer layer 23 exposed by the removal of the ZnO buffer layer 22 and the substrate 21 (the entire AlN buffer layer 23 in the example of the light emitting element 1 shown in FIG. 1) is further removed. Then, the light emission of the present embodiment is achieved by providing the negative electrode 9 on the exposed n-type semiconductor layer 8 and providing the positive electrode 4 on the p-type semiconductor layer 6 side through the reflective p-type electrode layer 5. Element 1 is obtained.
Hereinafter, the semiconductor multilayer structure 2 will be described in detail. In the following description, detailed description of the configuration common to the light-emitting element 1 of the present embodiment described above will be omitted.

[substrate]
In the semiconductor multilayer structure 2 of the present embodiment, it is most preferable to use sapphire as the material used for the substrate 21. By forming the ZnO buffer layer 22 and the AlN buffer layer 23 on the substrate 21 made of sapphire, it becomes possible to further grow a gallium nitride compound semiconductor crystal having excellent crystallinity.
In addition, since sapphire is chemically stable, it is very suitable because it is not broken by etching in the removal step of etching the ZnO buffer layer 22 as described in the method of manufacturing a light emitting element described later. is there.
In addition to sapphire, silicon, SiC, spinel, etc. can be used as the material of the substrate 21 to grow a gallium nitride compound semiconductor crystal with good crystallinity on the ZnO buffer layer 22 and the AlN buffer layer 23. It is preferable at the point which can be made. In the present invention, any substrate material can be used as long as it is a substrate material capable of forming a gallium nitride compound semiconductor crystal having sufficient crystallinity to constitute a light emitting element. .

[ZnO buffer layer]
The ZnO buffer layer 22 provided in the semiconductor multilayer structure 2 of the present embodiment is a buffer layer formed on the substrate 21.
The ZnO buffer layer 22 is preferably made of single crystal ZnO. Further, the ZnO buffer layer 22 may have a crystal structure (polycrystal) having a single crystal grain as a basic unit, such as an aggregate of columnar crystals. However, in the case where the ZnO buffer layer 22 is constituted by an aggregate of columnar crystals, lattice planes parallel to the substrate 21 are aligned, and the lattice planes not parallel to the substrate 21 have a certain orientation. It is necessary to be. Such orientation can be measured by an asymmetric surface X-ray measurement method, but it is necessary that at least a peak showing 6-fold symmetry appears.

  Moreover, although ZnO has polarity, it is preferable that the surface (outermost surface) 22a of the ZnO buffer layer 22 has Zn polarity.

  The method for forming the ZnO buffer layer 22 is not particularly limited, and any method may be adopted. In particular, examples of a method for stacking the ZnO buffer layer 22 as a layer having excellent lattice matching with the substrate 21 include MBE, PLD, sputtering, CVD, ion plating, and the like. Among these, examples of a method that is inexpensive and that can be expected to provide stable productivity include a PLD method, a sputtering method, and an ion plating method.

  The film thickness of the ZnO buffer layer 22 is preferably in the range of 10 to 1000 nm. If the thickness of the ZnO buffer layer 22 is less than 10 nm, the influence of the material constituting the substrate 21, for example, sapphire, cannot be blocked, and there is a possibility that the layer laminated thereon becomes a distorted crystal. Further, when the thickness of the ZnO buffer layer 22 exceeds 1000 nm, the surface 22a may be uneven. The film thickness of the ZnO buffer layer 22 is more preferably in the range of 50 to 500 nm, and most preferably in the range of 80 to 300 nm.

[AlN buffer layer]
The AlN buffer layer 23 provided in the semiconductor multilayer structure 2 of the present embodiment is a buffer layer that is stacked on the ZnO buffer layer 22 formed on the substrate 21.
The AlN buffer layer 23 is preferably made of single crystal AlN, like the ZnO buffer layer 22, but may have a crystal structure (polycrystal) having single crystal grains as a basic unit, such as an aggregate of columnar crystals. Absent. Among such polycrystal structures, an aggregate of columnar crystals having a hexagonal column as a basic structure is preferable.

The AlN buffer layer 23 is formed on the substrate 21 so as to be larger than the ZnO buffer layer 22 in plan view, and the AlN buffer layer 23 is formed so as to cover the surface 22a and the side surface 22b of the ZnO buffer layer 22. Preferably it is. As a result, the AlN buffer layer 23 serves as a coating layer that protects the ZnO buffer layer 22 from reactive gases and the like.
When a gap is generated in the AlN buffer layer 23 and a part of the surface 22a or the side surface 22b of the ZnO buffer layer 22 is exposed, the reactive source gas comes into contact with the surface 22a when the semiconductor layer 11 is formed. There is a risk of damaging the ZnO buffer layer 22.

As a method of forming the AlN buffer layer 23, it is necessary to use a method of performing a film forming process at a low temperature without using a highly reactive raw material. Here, the highly reactive raw material is a raw material gas such as NH ₃ or H ₂ , and the low temperature means a film forming temperature of 700 ° C. or lower. That is, it is preferable to use a physical film formation method such as an MBE method, a PLD method, a sputtering method, or an ion plating method for forming the AlN buffer layer 23. Among these, examples of a method that is inexpensive and that can be expected to provide stable productivity include a PLD method, a sputtering method, and an ion plating method.

  The film thickness of the AlN buffer layer 23 is preferably in the range of 10 to 100 nm. If the thickness of the AlN buffer layer 23 is less than 10 nm, it is difficult to completely cover the ZnO buffer layer 22 on the substrate 21. Further, if the thickness of the AlN buffer layer 23 exceeds 100 nm, the surface 23a may be uneven.

  When a nitride such as AlN is formed on the ZnO buffer layer 22, an amorphous or polycrystalline layer, which is a reaction layer in which Zn, Al, O, N, etc. are mixed, is formed at the interface. For example, it can be confirmed by a method such as TEM. Such a reaction layer is formed by being mixed with a growing film by ZnO being damaged and decomposed during the formation of a nitride such as AlN. Therefore, in the present embodiment, as described above, the AlN buffer layer 23 is formed at a low temperature without using a highly reactive raw material, so that the interface between the ZnO buffer layer 22 and the AlN buffer layer 23 is formed. The reaction layer is not formed.

[Method of Manufacturing Gallium Nitride Compound Semiconductor Light Emitting Element]
Next, a method for manufacturing a gallium nitride-based compound semiconductor light-emitting device according to the present invention will be described with reference to FIGS. 3 to 12 (the light-emitting device 1 in FIG. 1, the semiconductor stack in FIGS. 2A and 2B). Structure 2, 2A, see also light-emitting element 3 in FIG. 13).
In the method for manufacturing the light emitting device 1 of the present embodiment, a ZnO buffer layer 22 and an AlN buffer layer 23 are stacked in this order on a substrate 21, and a gallium nitride compound is formed on the AlN buffer layer 23. A semiconductor layer forming step for forming the semiconductor layer 11 and a removing step for removing the substrate 21 by removing the ZnO buffer layer 22.
The manufacturing method described in this embodiment is an example of a procedure for manufacturing a light-emitting element, and for each process described below, while considering the specifications and productivity of the finally obtained light-emitting element, For example, it is possible to adopt a method in which the order of steps is appropriately changed.

<Example of manufacturing method>
Below, each process is demonstrated in detail about an example of the manufacturing method of the light emitting element of this embodiment.
In this example, in addition to each of the above steps, between the semiconductor layer forming step and the removing step, the p-type semiconductor layer 6 side of the semiconductor layer 11 (in the example shown in FIG. 5, the reflective p-type electrode layer 5 side). ) Is provided with a support substrate bonding step of attaching a support substrate (positive electrode 4). Further, in this example, after performing the removing step, an insulating film forming step for forming a protective insulating film 10 is provided on each side surface (peripheral surface) 11b of the plurality of semiconductor layers 11, Between the insulating film forming step and the electrode forming step, a roughening step for roughening the light extraction surface 11a of the n-type semiconductor layer 8 is provided. Furthermore, in this example, after the electrode forming step, a dividing step for dividing the wafer into device units by cutting the positive electrode 4 is provided.

"Buffer layer formation process"
In the buffer layer forming step, as shown in FIGS. 3A to 3C, a substrate 21 made of sapphire having a main surface 21a made of c-plane is prepared, and a ZnO buffer layer is formed on the substrate 21. The AlN buffer layer 22 and the AlN buffer layer 23 are sequentially stacked according to each procedure described below.

"ZnO buffer layer"
First, a ZnO buffer layer 22 made of ZnO single crystal is formed on the main surface 21a of the substrate 21.
Specifically, as shown in FIGS. 3A to 3B, any of the MBE method, the PLD method, the sputtering method, the CVD method, the ion plating method, and the like is applied to the main surface 21a of the substrate 21. Using this method, the ZnO buffer layer 22 is formed. As a method for forming the ZnO buffer layer 22, the PLD method, the sputtering method, and the ion plating method are preferable because the apparatus is inexpensive and stable productivity can be expected, and the sputtering method is the most preferable. preferable.
In the buffer layer forming step, the ZnO buffer layer 22 can be stacked as a layer excellent in lattice matching with the substrate 21 by employing the above method.

"AlN buffer layer"
Next, an AlN buffer layer 23 made of AlN single crystal is formed on the ZnO buffer layer 22.
Specifically, as shown in FIG. 3C, the MBE method, the PLD method, the sputtering method, the ion plating method, and the like, as in the case where the ZnO buffer layer 22 is formed on the surface 22a of the ZnO buffer layer 22. Of these, the AlN buffer layer 23 is formed using any of the physical film formation methods. As a method of forming the AlN buffer layer 23 from single crystal AlN having excellent crystallinity, it is necessary to use a method of performing a film formation process at a low temperature without using a highly reactive raw material. However, examples of such a method include the above-described methods. Among the above methods, the PLD method, the sputtering method, and the ion plating method are preferable, and the sputtering method is most preferable because the apparatus is inexpensive and stable productivity can be expected. Here, the highly reactive material described in the present invention is a material gas such as NH ₃ or H ₂ , and the low temperature refers to a film forming temperature of 700 ° C. or less.

In the buffer layer forming step of the present embodiment, it is preferable to use nitrogen (N ₂ ) gas as a nitrogen source when forming the AlN buffer layer 23. As described above, when a single crystal AlN film having excellent crystallinity is formed, it is not preferable to use a highly reactive material such as NH ₃ or H _2, but nitrogen gas is used as a nitrogen source. From the viewpoint of low reactivity and low cost.
Further, as described above, the film forming temperature when forming the AlN buffer layer 23 needs to be low in order to form a single crystal AlN having excellent crystallinity, and is formed at a temperature of 700 ° C. or lower. Preferably, the temperature is set to 600 ° C. or lower.

  In the buffer layer forming step of this embodiment, the ZnO buffer layer 22 and the AlN buffer layer 23 may be formed by the same method or may be formed by different methods. In the case where the ZnO buffer layer 22 and the AlN buffer layer 23 are formed by the same method, the same chamber may be used to change the film forming conditions and the source gas each time, or the substrate may be transferred in and out using different chambers. It is good also as a method of forming each film | membrane separately by performing. However, in consideration of the waiting time associated with the switching of the source gas, the change of the film forming temperature, etc., it is preferable to form the film using different dedicated chambers.

In the buffer layer forming step of the present embodiment, the AlN buffer layer 23 is formed on the substrate 21 so as to be larger than the ZnO buffer layer 22 in plan view, and the AlN buffer layer 23 is formed on the surface 22a and side surfaces of the ZnO buffer layer 22. It is preferable to form so as to cover 22b.
When the ZnO buffer layer 22 is formed on the substrate 21, the side surface 22 b is unavoidably exposed at the outer peripheral portion, and there is a possibility that the reactive gas is contacted. For this reason, it is preferable that the side surface 22 a of the ZnO buffer layer 22 is also covered with the AlN buffer layer 23. Specifically, a region in which the ZnO buffer layer 22 is formed on the main surface 21a of the substrate 21 may be slightly reduced so that both the surface 22a and the side surface 22b can be covered with the AlN buffer layer 23. . In this case, for example, when the ZnO buffer layer 22 is formed, a method of performing a film forming process by masking the outer peripheral portion of the wafer with a jig or the like can be employed.

"Semiconductor layer formation process"
Next, in the semiconductor layer forming step, as shown in FIGS. 4A to 4C, the n-type semiconductor layer 8 made of a gallium nitride compound is formed on the AlN buffer layer 23 on the substrate 21. The layer 7 and the p-type semiconductor layer 6 are sequentially stacked to form the semiconductor layer 11. In the present embodiment, an example in which the semiconductor layer forming step includes a step of laminating the reflective p-type electrode layer 5 on the p-type semiconductor layer 6 after the formation of the semiconductor layer 11 is completed will be described.

Specifically, first, as shown in FIG. 4A, the n-type semiconductor layer 8, the light emitting layer 7, and the p-type semiconductor layer 6 are sequentially stacked on the AlN buffer layer 23.
The n-type semiconductor layer 8 is preferably doped with Si or the like as an n-type dopant, and the p-type semiconductor layer 6 is preferably doped with Mg or the like as a p-type dopant.

  At this time, the growth method of the n-type semiconductor layer 8, the light-emitting layer 7 and the p-type semiconductor layer 6 constituting the semiconductor layer 11 is not particularly limited, and sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride). All methods known to grow GaN-based semiconductors such as vapor phase epitaxy) and MBE (molecular beam epitaxy) can be applied. A preferable growth method is a sputtering method or an MOCVD method from the viewpoint of film thickness controllability and mass productivity.

In the sputtering method, it is preferable to form a GaN-based semiconductor by a so-called reactive sputtering method using a target containing Ga and using a mixed gas of argon and nitrogen as a plasma gas.
In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a group III source, trimethyl aluminum (TMA) or Al as a source Triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as an N source as a group V raw material are used. In addition, as a dopant, for n-type, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a Si raw material, germanium gas (GeH ₄ ) or tetramethyl germanium ((CH ₃ ) ₄ Ge) is used as a Ge raw material. And organic germanium compounds such as tetraethylgermanium ((C ₂ H ₅ ) ₄ Ge) can be used.
In the MBE method, elemental germanium can also be used as a doping source. For the p-type, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) or bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) may be used as the Mg raw material.

  In the present embodiment, a base layer 27 is formed on the surface 23a of the AlN buffer layer 23 before the n-type semiconductor layer 8 is formed, as in the example shown in FIG. A method of stacking the n-type semiconductor layer 8 thereon can be employed. By forming the foundation layer 27 between the AlN buffer layer 23 and the n-type semiconductor layer 8, the crystallinity of the semiconductor layer 11 including the n-type semiconductor layer 8 is improved.

  Next, as shown in FIG. 4B, in addition to the n-type semiconductor layer 8, the light-emitting layer 7 and the p-type semiconductor layer 6 sequentially stacked on the substrate 21 by the above procedure, a ZnO buffer layer 22 and an AlN buffer are also provided. The layer 23 is divided into a plurality of stacked bodies, and the separation groove 12 is formed.

  Specifically, a mask is formed on the p-type semiconductor layer 6 constituting the semiconductor layer 11, and as shown in FIG. 4B, the p-type semiconductor layer 6, the light emitting layer 7 and the n-type layer are formed by means such as dry etching. The stacked body composed of the type semiconductor layer 8 is divided into a lattice shape by etching. The etching process ends when the substrate 21 is exposed. As a result, a stacked body composed of the p-type semiconductor layer 6, the light emitting layer 7, the n-type semiconductor layer 8, the AlN buffer layer 23, and the ZnO buffer layer 22 is formed into a stacked body divided into a plurality along the separation groove 12.

  In the present invention, after the ZnO buffer layer 22 and the AlN buffer layer 23 are previously laminated on the substrate 21 in the buffer layer forming step, the n-type semiconductor layer 8 constituting the semiconductor layer 11 and the light emission are formed thereon. Each of the layer 7 and the p-type semiconductor layer 6 is formed. That is, when a sapphire substrate is used as the substrate 21 and GaN is formed as the n-type semiconductor layer 8, the lattice constants of the substrate 21 and the n-type semiconductor layer 8 are different by 10% or more. In the present invention, by using the AlN buffer layer 23 and the ZnO buffer layer 22 made of AlN and ZnO having an intermediate lattice constant between the substrate 21 and the n-type semiconductor layer 8, GaN crystals constituting the n-type semiconductor layer 8 are used. It becomes possible to improve the property.

Further, in the semiconductor layer forming step of the present embodiment, as a method for forming a base layer 27 between the AlN buffer layer 23 and the n-type semiconductor layer 8 as in the example shown in FIG. Also good. Further, as a method for forming the underlayer 27, it is preferable to use the MOCVD method from the viewpoint of obtaining a layer with good crystallinity.
In the semiconductor layer forming step, the total film thickness of the n-type semiconductor layer 8 and the base layer 27 is preferably 15 μm or less, more preferably 10 μm or less, and 4 μm or less. Is most preferred.

"Formation of reflective p-type electrode layer"
Next, in this example, as shown in FIG. 4C, an ohmic contact layer, a reflective layer, and an interdiffusion prevention layer are sequentially stacked on the p-type semiconductor layer 6 by photolithography and patterned. Thus, the reflective p-type electrode layer 5 is formed. Further, the reflective p-type electrode layer 5 in the illustrated example is smaller than the p-type semiconductor layer 6 in plan view on the p-type semiconductor layer 6 and is formed in the vicinity of the approximate center excluding the edge 61.

  In forming the ohmic contact layer on the p-type semiconductor layer 6, it is preferable to form the ohmic contact layer by a sputtering film forming method using RF discharge. By using a sputtering film formation method by RF discharge, an electrode having a lower contact resistance can be formed than by using a vapor deposition method or a DC discharge sputtering film formation method. That is, by forming the ohmic contact layer by the sputtering film formation method by RF discharge, the constituent elements of the p-type semiconductor layer 6 are mixed in the ohmic contact layer, and the constituent elements of the ohmic contact layer are mixed in the p-type semiconductor layer 6. As a result, the ohmic contact layer and the p-type semiconductor layer 6 are in ohmic contact.

  In sputtering film formation by RF discharge, energy is given to sputtered atoms attached to the p-type semiconductor layer 6 by the ion assist effect, and surface diffusion is promoted between the p-type semiconductor, for example, Mg-doped p-GaN. it is conceivable that. Furthermore, it is considered that the film formation also has an effect of imparting energy to the outermost surface atoms of the p-type semiconductor layer 6 to promote the diffusion of a semiconductor material such as Ga into the ohmic contact layer.

  The film formation by RF discharge has an effect of lowering the contact resistance in the initial stage. However, when the film thickness is increased, the film is sparse, so that the reflectivity is inferior to the film formation by DC discharge. Therefore, it is preferable to form an ohmic contact layer that is thinned and increases the light transmittance within a range in which contact resistance is kept low by RF discharge, and a reflective layer and an interdiffusion prevention layer are formed thereon by DC discharge.

Sputtering can be carried out by appropriately selecting conventionally known conditions using a conventionally known sputtering apparatus. The substrate 21 on which the semiconductor layer 11, the AlN buffer layer 23, and the ZnO buffer layer 22 are stacked is housed in a chamber, and the substrate temperature is set in the range of room temperature to 500 ° C. Substrate heating is not particularly required, but may be appropriately heated in order to promote diffusion of the constituent elements of the ohmic contact layer and the constituent elements of the p-type semiconductor layer 6. The chamber is evacuated until the degree of vacuum is 10 ⁻⁴ to 10 ⁻⁷ Pa. As the sputtering gas, He, Ne, Ar, Kr, Xe, or the like can be used. Ar is desirable because of availability. One of these gases is introduced into the chamber and the discharge is performed after the pressure is set to 0.1 to 10 Pa. Preferably it sets to the range of 0.2-5Pa. The supplied power is preferably in the range of 0.2 to 2.0 kW. At this time, the thickness of the layer to be formed can be adjusted by adjusting the discharge time and supply power.

"Formation of semiconductor stack structure"
In the method for manufacturing the light-emitting element 1 according to the present embodiment, the ZnO buffer layer 22, the AlN buffer layer 23, and the semiconductor layer 11 are sequentially stacked on the substrate 21 by performing the above-described buffer layer forming step to semiconductor layer forming step. Thus, the semiconductor multilayer structure 2 of the present embodiment is obtained (see FIG. 4C).
In this embodiment, after forming a plurality of semiconductor stacked structures 2 as shown in FIG. 4C, a protective film is formed in advance on each side surface of the semiconductor layer 11 in subsequent steps. From the viewpoint that the semiconductor layer 11 can be protected.

  In the manufacturing method of the present embodiment, the ZnO buffer layer 22 and the substrate 21 are removed from the semiconductor multilayer structure 2 to form the positive electrode 4 and the negative electrode 9 by further performing the steps described below. Thus, the light emitting device 1 of this embodiment is manufactured.

"Support substrate bonding process"
Next, in the support substrate bonding step, as shown in FIG. 5, the support substrate (positive electrode 4) is attached to the p-type semiconductor layer 6 side of the semiconductor layer 11.
Specifically, as shown in FIG. 5, the positive electrode 4 is bonded as a conductive support substrate made of Si to the p-type semiconductor layer 6 side of the semiconductor layer 11, that is, the reflective p-type electrode layer 5. Thus, when the positive electrode 4 made of Si is used as the support substrate, a method of bonding to the semiconductor layer 11 side with the metal bonding layer can be employed.

  In this example, in order to facilitate the handling of the laminated body from which the substrate 21 has been peeled off, a positive electrode 4 needs to be bonded in advance to the semiconductor layer 11 side as a support substrate before the below-described removal step. As described above, as a method of providing the substrate for supporting the stacked body, in addition to the method of bonding the positive electrode 4 as in this embodiment, as in other examples of this embodiment described later, for example, a semiconductor layer The method of forming the support substrate (refer the positive electrode 40 in Fig.11 (a), (b)) which consists of metal plating to 11 side is mentioned. In such a configuration, since the metal plating has conductivity, the support substrate can be used as it is as an electrode, that is, a positive electrode.

  Note that the support substrate does not necessarily have conductivity, but if a support substrate having conductivity such as a Si substrate is used as in the present embodiment, it can be used as it is as the positive electrode 4. In this case, it is preferable because a so-called vertical structure light emitting element (LED) having electrodes on the front and back surfaces of the semiconductor multilayer structure can be formed. In this way, when a conductive support substrate made of Si or the like is used and the support substrate is used as it is as the positive electrode 4, the positive electrode 4 is placed on the p-type semiconductor layer side through a bonding layer made of, for example, Ni and Au. It can be set as the structure joined.

When a support substrate made of metal, such as metal plating, is used, it is necessary to cover the surface of the support substrate with a protective layer or the like before the step of removing the ZnO buffer layer 22 and the substrate 21. In this case, as a material used for the protective layer, NiP or the like can be used in addition to oxides or nitrides such as SiO ₂ , SiN, Al ₂ O ₃ , and AlN.

  In addition, the support substrate used in the present embodiment is not limited to the conductive substrate as described above, and can be formed of an insulating material such as an oxide or nitride of Si, for example. Specifically, although detailed illustration is omitted, a method of bonding a support substrate made of Si oxide or nitride to the p-type semiconductor layer 6 side of the semiconductor layer 11, that is, the reflective p-type electrode layer 5. It can be set as the method of joining by.

"Removal process"
Next, in the removing step, as shown in FIGS. 6A to 6C, the ZnO buffer layer 22 is removed, and the substrate 21 is peeled off.
Specifically, as shown in FIGS. 6A to 6B, for example, the ZnO buffer layer 22 is dissolved and removed by an etching method (chemical lift-off method) using an etching solution such as an acid. Then, as shown in FIG. 6C, the substrate 21 is peeled from the semiconductor layer 11 and the AlN buffer layer 23 side as the ZnO buffer layer 22 is melted.

  In the removal step of the present embodiment, it is preferable to use HCl or oxalic acid as an etching solution used for dissolving the ZnO buffer layer 22. By etching using HCl or oxalic acid, the ZnO buffer layer 22 can be efficiently and reliably removed, and the substrate 21 can be easily peeled off from the semiconductor layer 11 and the AlN buffer layer 23 side. It becomes.

Further, in the removing process, the etching solution can be efficiently brought into contact with the ZnO buffer layer 22 to improve the efficiency of the process.
Here, since a dense crystal film is not usually formed on the outer periphery of the substrate 21 where the ZnO buffer layer 22 is not formed, the substrate 21 can be peeled off simply by immersing the laminate in an etching solution. . However, depending on the film formation state of the ZnO buffer layer 22 and the AlN buffer layer 23 on the substrate 21, it may be better to grind the outer peripheral portion of the substrate 21 and then immerse it in the etching solution. For example, a case where the AlN buffer layer 23 is formed so as to cover the surface 22a and the side surface 22b of the ZnO buffer layer 22 as in the example described in the present embodiment.

  On the other hand, when a large-diameter substrate such as 4 inches or more is used, it takes a long time to completely dissolve the ZnO buffer layer 22 only by penetration of the etching solution from the outer peripheral portion. In this case, a method of forming a hole reaching the substrate 21 from the semiconductor layer 11 side and allowing the etching solution to penetrate into the ZnO buffer layer 22 in a short time can be employed.

"Insulating film formation process"
Next, in the insulating film forming step, as shown in FIG. 7, a protective insulating film 10 is formed on each side surface (peripheral surface) 11 b of the semiconductor layer 11.
Specifically, as shown in FIG. 7, the insulating film 10 made of SiO _{2 is} formed on the side surface 11b of each semiconductor layer 11 and the light extraction surface 11a of each semiconductor layer 11 by means such as CVD or sputtering. It forms so that an outer peripheral part may be covered. The target insulating film 10 can be formed by forming the insulating film 10 on the entire semiconductor layer 11, forming a resist on a portion other than the central portion of the light extraction surface 11 a, and performing dry etching.
The insulating film 10 may be formed at least on the outer peripheral portion of the side surface 11b of the semiconductor layer 11 and the light extraction surface 11a. Moreover, in each drawing (FIGS. 8 to 10 and FIG. 12) referred to in the present invention, the insulating film on the side surface of the semiconductor layer or the like in the drawing is intentionally deleted in order to clearly indicate the reference numerals. In the light emitting device according to the present invention, an insulating film is continuously present on each side surface.

"Roughening process"
Next, in the roughening step, the light extraction surface 11a of the n-type semiconductor layer 8 is roughened.
Specifically, as shown in FIG. 8, a portion of the light extraction surface 11a exposed without being covered with the central insulating film 10 is immersed in a heated KOH solution or TMAH (Tetramethylammonium hydride) solution. When the AlN buffer layer 23 is removed and a base layer (see the base layer 27 in FIG. 2B) is provided, the base layer is removed and the light extraction of the n-type semiconductor layer 8 is performed. The surface 11a is roughened.
Note that PEC (photoelectrochemical etch) can be used to remove the AlN buffer layer 23 and the underlayer and to roughen the light extraction surface 11a, and dry etching can also be applied.

The above-described removal operation of the AlN buffer layer 23 is an operation for forming a later-described negative electrode 9 on the n-type semiconductor layer 8. However, if the AlN buffer layer 23 is doped, the AlN buffer layer 23 is removed. It is also possible to form the negative electrode 9 on this, and this removal operation becomes unnecessary.
In addition, when the underlayer is provided, the above-described underlayer removal operation is an operation necessary when the underlayer is an undoped layer, and when the underlayer is doped with Si or the like, As in the case of the AlN buffer layer 23, it is not necessary to remove the underlayer.
In this example, an example in which the AlN buffer layer 23 and the underlayer are removed using a heated KOH solution or TMAH solution used for roughening the light extraction surface 11a is described. It is not limited. For example, the AlN buffer layer 23 and the underlying layer may be thermally decomposed by laser irradiation or the like and removed as appropriate.

  Further, in the roughening step of the present embodiment, in the removal operation of the AlN buffer layer 23 and the underlayer, for example, a method of removing only the negative electrode 9 formation region by patterning can be employed, and it may be adopted as appropriate. .

"Electrode formation process"
Next, in the electrode forming step, as shown in FIG. 9, the negative electrode 9 is formed on the n-type semiconductor layer 8 of the semiconductor layer 11.
Specifically, first, a semiconductor wafer including the semiconductor layer 11 is accommodated in a chamber of a plasma dry etching apparatus, and a reaction gas composed of an etching gas containing the same element as the dopant element in the n-type semiconductor layer 8 is contained in the chamber. And plasma is generated above the semiconductor layer 11 to expose the plasma containing the etching gas to the light extraction surface 11a.

As the etching gas used in this case, when the dopant element in the n-type semiconductor layer 8 is silicon (Si), it is preferable to use silicon halide as the etching gas, and specifically, SiCl ₄ or SiF ₄ is preferable. .
The pressure in the chamber when the reaction gas is introduced is preferably in the range of 0.2 to 2 Pa, the flow rate of the etching gas is preferably in the range of 15 sccm to 50 sccm, and the plasma power is preferably about 120 W. The bias is preferably about 50 W, and the processing time is preferably about 150 seconds.
By performing such an etching process, it is considered that Si contained in the etching gas is implanted in the vicinity of the surface of the n-type semiconductor layer 8 to increase the Si concentration in the vicinity of the surface.

  Next, as shown in FIG. 9, the negative electrode 9 is formed on the n-type semiconductor layer 8 after the plasma treatment. For example, the negative electrode 9 can be formed by sequentially laminating a Cr film, a Ti film, and an Au film. However, the present invention is not limited to this, and the material and the laminated structure of the negative electrode 9 may be appropriately adopted. Is possible. Moreover, the formation process of such a negative electrode 9 should just use sputtering method and a vapor deposition method, for example.

  As described above, the negative electrode 9 and the n-type semiconductor layer 8 can be brought into ohmic contact by stacking the layers constituting the negative electrode 9 after treating the surface of the n-type semiconductor layer 8 with plasma. In this case, annealing after the formation of the negative electrode 9 is not required. Rather, annealing may deteriorate the electrical characteristics, and the Ag alloy of the reflective film causes migration and the reflectance decreases, which is not preferable.

  In this example, as described in the support substrate bonding step described above, an example in which the positive electrode 4 is formed of a conductive support substrate and bonded to the reflective p-type electrode layer 5 will be described. However, the present invention is not limited to this. For example, as will be described in detail in another example of the manufacturing method of the present embodiment described later, the positive electrode 4 is formed as a metal plating layer on the p-type semiconductor layer 6 (on the reflective p-type electrode layer 5) by using a plating method. It may be formed.

Further, in this example, an example in which the positive electrode 4 is configured by using a conductive support substrate made of Si has been described. However, as described above, the present invention is not limited to such an example. It is also possible to employ a method using a support substrate made of an insulating material such as an oxide or nitride. In such a case, for example, after removing the support substrate made of an insulating material, the positive electrode 4 can be formed on the reflective p-type electrode layer 5.
In the case of such a method, specifically, although detailed illustration is omitted, for example, the method described below can be used.

First, a temporary attachment substrate made of, for example, a glass (quartz) substrate or the like is attached to the negative electrode 9 formed on the n-type semiconductor layer 8 side with an adhesive or the like, and then the temporary attachment substrate is peeled off by a conventionally known method. The reflective p-type electrode layer 5 on the p-type semiconductor layer 6 is exposed.
Next, on the reflective p-type electrode layer 5 exposed on the p-type semiconductor layer 6, for example, a metal wafer made of Cu, Al, or the like is bonded onto the reflective p-type electrode layer 5, thereby forming a positive electrode. Form. And after forming a positive electrode in the said procedure, it can be set as the method of peeling the temporary sticking board | substrate stuck to the negative electrode 9 by a conventionally well-known method, and exposing the negative electrode 9. FIG.

  In the present embodiment, as described above, when the AlN buffer layer 23 is doped to have conductivity, the AlN buffer layer 23 is not removed and the AlN buffer layer 23 has a negative electrode. It is also possible to form 9.

  For example, when an insulating support substrate made of an oxide or nitride of Si is used, it is possible to form a through hole in the support substrate and attach a positive electrode to the through hole.

"Division process"
Next, in the dividing step, as shown in FIGS. 9 to 10, the positive electrode 4 that is the base is cut along the semiconductor layer 11 divided into a plurality of parts.
Specifically, as shown in FIG. 9, the positive electrode 4 is irradiated with laser along the dividing groove 12 between each of the plurality of semiconductor layers 11 formed on the positive electrode 4 by using, for example, a laser scribing method. And cut.

Moreover, when performing division by such a laser scribing method, for example, a method can be used in which a pressure-sensitive adhesive tape is stuck on a dicing table and a wafer is stuck on the table. By dividing in such a manner, it becomes possible to easily divide and take out a plurality of light-emitting elements cut by laser scribing without damaging them. In addition, by performing the dividing step with the adhesive tape affixed on the table, it is possible to prevent the table from being burned by the laser.
By performing such a dicing process, a plurality of light emitting elements 1 as shown in FIG. 10 (see also FIG. 1) can be obtained.

<Other examples of manufacturing methods>
Hereinafter, each process is demonstrated in detail about the other example of the manufacturing method of the light emitting element of this invention. In addition, in this example, about the structure which is common with an example of the manufacturing method of this embodiment as mentioned above, it attaches | subjects a common code | symbol and demonstrates using a common drawing, Moreover, about the process which is common in each example The drawings and detailed description thereof are omitted.

The manufacturing method of the light emitting element 3 of this example is a p-type semiconductor of the semiconductor layer 11 between the semiconductor layer forming step and the removing step instead of the electrode forming step provided in the example of the manufacturing method of the present embodiment. It differs from an example of the manufacturing method of the light emitting element 1 of this embodiment mentioned above in the point provided with the plating process which forms the positive electrode 40 which consists of metal plating in the layer 6 side.
Further, in this example, the buffer layer forming step to the semiconductor layer forming step are common to the example of the manufacturing method, and therefore, the steps after the plating step will be mainly described.

  Further, in the light emitting device manufactured by the method of this example, like the light emitting device 3 shown in FIG. 13, the positive electrode 40 is formed on the reflective p-type electrode layer 5, and the seed layer 42. The configuration of the positive electrode is different from that of the light-emitting element 1 obtained by the example of the manufacturing method in that the metal plating layer 41 is formed thereon.

"Plating process"
In this example, after performing the buffer layer forming process to the semiconductor layer forming process similar to the example of the manufacturing method of the present embodiment, as shown in FIGS. A positive electrode 40 composed of a metal plating layer 41 and a seed layer 42 is formed on the reflective p-type electrode property 5.

  Specifically, first, as shown in FIG. 11A, a seed layer 42 serving as a base for the metal plating layer 41 is formed on the reflective p-type electrode property 5. At this time, a seed layer 42 is formed by sequentially stacking a Ti film, a Ta film, and a Cu film so as to cover the reflective p-type electrode property 5. The seed layer 42 may be formed by sequentially stacking a Ni film, an Au film, a Ti film, a Ta film, and a Cu film, or may be a single layer film made of Cu. Here, the Ta film functions as a barrier for Cu forming the metal plating layer 41.

  When the seed layer 42 is formed, the resist layer 26 is embedded in advance in the separation groove 12 provided between each of the plurality of semiconductor layers 11 on the substrate 21. Then, a seed layer 42 is formed so as to cover the reflective p-type electrode layer 5 and the resist layer 26 provided in the plurality of semiconductor layers 11.

  In addition, the seed layer 42 is not necessarily a laminated film essential as a constituent member of the light emitting element. If the reflective p-type electrode layer 5 provided in the semiconductor layer 11 can have a function as an underlayer for plating, the seed layer 42 may be used. Layer 42 may be omitted.

Next, as shown in FIG. 11B, a metal plating layer 41 is formed so as to cover the seed layer 42. The metal plating layer 41 can be formed by electroplating while applying current to the seed layer 42.
The material of the metal plating layer 41 preferably corresponds to the material of the seed layer 42. In this embodiment, the metal plating layer 41 is formed using Cu, which is the same material as the Cu film of the seed layer 42. preferable. Cu can be plated at room temperature and is not easily affected by thermal expansion during the formation of the plating layer. Further, Cu is preferable as a material for the base of the light emitting element 3 having the upper and lower electrode structures from the viewpoint of low electric resistance and high thermal conductivity.

"Negative electrode forming process"
Next, in the manufacturing method of this example, a negative electrode forming step of forming the negative electrode 9 on the n-type semiconductor layer 8 side of the semiconductor layer 11 is provided after the removing step.
Specifically, as shown in FIG. 12, the AlN buffer layer 23 (and the underlying layer) is used in the roughening step using the same procedure as the electrode forming step described in the example of the manufacturing method of the present embodiment. A negative electrode 9 is formed on the light extraction surface 11a of the n-type semiconductor layer 8 exposed by removing at least a part of the negative electrode 9.

  Also in this example, similarly to the electrode forming step in the example of the manufacturing method of the present embodiment, if the AlN buffer layer 23 (and the underlying layer) is doped, the AlN buffer is not removed without removing these layers. The negative electrode 9 can be formed on the layer 23.

Next, in this example, a method similar to the example of the manufacturing method of the present embodiment described above can be used for the removing step, the insulating film forming step, the roughening step, and the dividing step.
In this example, the AlN buffer layer 22 is removed from the n-type semiconductor layer 8 to form the negative electrode 9, and then the resist layer embedded in the separation groove 12 between each of the plurality of semiconductor layers 11. A method of removing 26 by ashing or the like can be employed.
According to another example of the method for manufacturing a light emitting device of this embodiment, the upper and lower electrode type light emitting device 3 as shown in FIG.

According to the manufacturing method of the gallium nitride compound semiconductor light emitting device of the present embodiment as described above, the buffer layer forming step of laminating the ZnO buffer layer 22 and the AlN buffer layer 23 on the substrate 21 in this order, and the AlN buffer In the semiconductor layer forming step, the method includes a semiconductor layer forming step of forming the semiconductor layer 11 made of a gallium nitride compound on the layer 23 and a removing step of peeling the substrate 21 by etching away the ZnO buffer layer 22. Even when NH ₃ is used or a film formation process is performed at a high temperature, the crystallinity of the ZnO buffer layer 22 is not reduced, and disappearance due to dissolution does not occur. Further, the substrate 21 can be easily peeled off by etching away the ZnO buffer layer 22. As a result, the light emitting element 1 (3) having excellent light emission characteristics can be manufactured with high yield and high productivity.

  In the manufacturing method of the present embodiment, an example of manufacturing a light emitting element having an upper and lower electrode structure as shown in FIG. 1 is described. However, the present invention is not limited to this example. For example, the example shown in FIG. As described above, the present invention can also be applied to a so-called flip-chip light emitting element in which electrodes are formed on the same surface side of a semiconductor layer.

[lamp]
By combining the upper and lower electrode type light emitting element 1 (see FIG. 1) according to the present invention and the phosphor as described above, a lamp can be configured using means well known to those skilled in the art. Conventionally, a technique for changing an emission color by combining a light emitting element and a phosphor is known. In the present invention, such a technique can be employed without any limitation.
For example, it is possible to obtain light having a longer wavelength than that of the light emitting element by appropriately selecting the phosphor, and white light emission by mixing the light emission wavelength of the light emitting element itself with the wavelength converted by the phosphor. It can also be set as the lamp which exhibits.
Further, the lamp can be used for any purpose such as a general bullet type, a side view type for a portable backlight, and a top view type used for a display.

For example, when the upper and lower electrode type light emitting elements 1 are mounted in a shell shape as in the example shown in FIG. 15, the light emitting element 1 is silver paste on one of the two frames (frame 81 in FIG. 15). The positive electrode 4 of the light-emitting element 1 (see reference numeral 4 shown in FIG. 1) is bonded to the frame 81 by bonding with a conductive adhesive such as, and the negative electrode 9 (see reference numeral 9 shown in FIG. 1) of the light-emitting element 1 is connected to the wire 83. To the frame 82. Then, by sealing the periphery of the light emitting element 1 with a mold 84 made of a transparent resin, a bullet-type lamp 80 as shown in FIG. 15 can be manufactured.
Since the lamp 80 of the present invention as described above uses the light emitting element 1 obtained by the method for manufacturing a light emitting diode according to the present invention, the lamp 80 has excellent light emission characteristics.

[Other semiconductor elements (devices)]
A laminated structure of a gallium nitride compound semiconductor obtained in the present invention and having excellent crystallinity (see the light emitting element 1 in FIG. 1 in addition to the semiconductor laminated structures 2 and 2A in FIGS. 2A and 2B). In addition to the semiconductor layer provided in the light emitting element such as the light emitting diode (LED) or the laser diode (LD) as described above, a photoelectric conversion element such as a solar cell or a light receiving element, or an HBT (Heterojunction Bipolar Transistor) or HEMT. The present invention can also be applied to a stacked structure of an electronic device such as (High Electron Mobility Transistor). Many of these semiconductor elements are known in various structures, and the laminated structure of the gallium nitride compound semiconductor according to the present invention is not limited at all including these known element structures.

  Next, although the manufacturing method of the gallium nitride compound semiconductor light emitting device of the present invention, the laminated structure of the gallium nitride compound semiconductor device, and the gallium nitride compound semiconductor light emitting device will be described in more detail with reference to examples and comparative examples, The present invention is not limited to these examples.

[Example 1]
FIG. 1 shows a schematic cross-sectional view of a gallium nitride-based compound semiconductor light-emitting device manufactured in this example. In this example, a ZnO buffer layer 22 made of ZnO single crystal and having Zn polarity is formed on the c-plane of the substrate 21 made of sapphire using RF sputtering, and a similar RF sputtering method is formed thereon. Then, an AlN buffer layer 23 made of AlN single crystal was formed, and an underlayer made of Si-doped GaN was further formed thereon using MOCVD. Next, an n-type contact layer and an n-type clad layer constituting the n-type semiconductor layer 8 are laminated on the underlayer using the MOCVD method, and a light emitting layer 7 and a p-type semiconductor layer 6 are further laminated. By forming the semiconductor layer 11, the semiconductor multilayer structure 2 was produced. In the semiconductor multilayer structure 2, a reflective p-type electrode layer 5 is formed on the p-type semiconductor layer 6, and a support made of Si is formed on the reflective p-type electrode layer 5 using an Au—Au junction. The substrate 24 was bonded. Thereafter, the substrate 21 is peeled and removed by removing the ZnO buffer layer 22 using hydrochloric acid as an etchant, and after removing the AlN buffer layer 23 and the underlying layer, the negative electrode is formed on the exposed n-type semiconductor layer 8. 9 was formed. The positive electrode 4 was bonded to the p-type semiconductor layer 6 side of the semiconductor layer 11, that is, to the reflective p-type electrode 5.

"Buffer layer formation process"
In the buffer layer forming step, the ZnO buffer layer 22 and the AlN buffer layer 23 were formed using a sputtering apparatus having a configuration in which two chambers were connected by a vacuum transfer.

First, a substrate 21 made of (0001) c-plane sapphire having a diameter of 2 inches whose surface was mirror-polished was introduced into the chamber. At this time, a target made of ZnO was used.
Then, the substrate 21 is heated to 500 ° C. in the chamber, the pressure in the chamber is maintained at 1.0 Pa while introducing nitrogen gas, a high frequency bias is applied to the substrate 21 side, and the substrate 21 is exposed to nitrogen plasma. The surface was cleaned. Thereafter, the pressure in the chamber of the sputtering apparatus was reduced to 6.0 × 10 ⁻⁶ Pa.

(Formation of ZnO buffer layer)
Next, argon and nitrogen gas were introduced into the sputtering apparatus while keeping the temperature of the substrate 21 as it was. Then, a high frequency bias is applied to the ZnO target side, the pressure in the furnace is kept at 0.5 Pa, and 25% oxygen is introduced into the Ar gas, and the substrate 21 made of sapphire is made of ZnO. A single crystal ZnO buffer layer 22 was formed. Then, after depositing 500 nm of ZnO (ZnO buffer layer 22) by processing for a prescribed time in accordance with the film formation rate (0.8 nm / s) measured in advance, the plasma operation is stopped and the substrate 21 is transferred to the transfer chamber. Carried out.

(Formation of AlN buffer layer)
Next, the substrate 21 on which the ZnO buffer layer 22 was formed was introduced into the AlN film forming chamber. At this time, the heater for heating the substrate in the chamber was heated to 500 ° C. in advance and held for a certain period of time in order to stabilize the temperature.
Next, argon and nitrogen gas were introduced into the sputtering apparatus. Then, a high frequency bias is applied to the AlN target side, the pressure in the furnace is kept at 0.5 Pa, and Ar gas and nitrogen gas are introduced under the condition that the ratio of nitrogen in the whole gas is 75%, and is made of sapphire. An AlO buffer layer 23 made of AlN single crystal was formed on the substrate 21. Then, according to the film formation rate (0.067 nm / s) measured in advance, after the film formation of 40 nm of AlN (AlN buffer layer 23) by the treatment for the specified time, the plasma operation is stopped and the temperature of the substrate 21 is lowered. I let you.

  Then, an X-ray rocking curve (XRC) of the surface of the AlN buffer layer 23 on the ZnO buffer layer 22 formed on the substrate 21 is used with an X-ray measuring apparatus (Spectris Co., Ltd., model number: X'pert Pro MRD). Measured. This measurement was performed using a CuKα ray X-ray generation source as a light source. As a result, the XRC half-value width of the AlN buffer layer 23 formed on the ZnO buffer layer 22 has an excellent characteristic of 0.1 °, and the ZnO buffer layer 22 and the AlN buffer layer 23 are well oriented. I was able to confirm.

“Formation of n-type semiconductor layers”
(Formation of underlayer)
Next, the substrate 21 on which the ZnO buffer layer 22 and the AlN buffer layer 23 are formed is taken out from the sputtering apparatus and transferred to the MOCVD apparatus, and a base layer made of GaN is formed on the AlN buffer layer 23 by the following procedure. Filmed.
First, the substrate 21 was introduced into a reaction furnace (MOCVD apparatus). Next, after flowing nitrogen gas through the reaction furnace, the heater was operated to raise the substrate temperature from room temperature to 500 ° C. Then, while keeping the temperature of the substrate to 500 ° C., and allowed to flow NH ₃ gas and nitrogen gas, the pressure of the vapor phase growth reaction furnace was 95 kPa. Subsequently, the substrate temperature was raised to 1000 ° C., and the surface of the substrate was subjected to thermal cleaning. Note that the supply of nitrogen gas into the vapor growth reactor was continued even after the thermal cleaning was completed.

Then, while continuing the circulation of ammonia gas, the temperature of the substrate was raised to 1100 ° C. in a hydrogen atmosphere, and the pressure in the reaction furnace was set to 40 kPa. After confirming that the substrate temperature is stabilized at 1100 ° C., supply of trimethylgallium (TMG) and silane (SiH ₄ ) into the vapor phase growth reactor is started, and the underlayer 14 a is formed on the buffer layer 12. A process of forming a Si-doped gallium nitride compound semiconductor (GaN) was started. After growing GaN in this way, the valves of the TMG and silane pipes were switched, the supply of raw materials to the reactor was terminated, and the growth of GaN was stopped.
Through the above steps, on the ZnO buffer layer 22 made of single crystal ZnO formed on the substrate 21 and the AlN buffer layer 23 made of single crystal AlN, the lower layer made of GaN having a thickness of 8 μm is doped with Si. A formation was formed.

(Formation of n-type contact layer)
Subsequent to the formation of the underlayer, an n-type contact layer made of GaN was formed by the same MOCVD apparatus. The n-type contact layer was doped with Si in the same manner as the underlayer. Si of 2.5 × ¹⁰ 18 ^{cm -3} is the dopant concentration in the base layer, the n-type contact layer was 5 × ¹⁰ 18 ^{cm -3.} The crystal growth at this time was performed under the same conditions as the underlayer except that the flow rate of SiH _{4 as} the Si dopant raw material was changed.

  And about the laminated structure of the base layer and n type contact layer formed into a film on the said conditions, when the XRC half value width of the surface was measured by the same method as the above, (0002) plane is 70 arcsec and (10-10) plane is It was 350 arcsec, and excellent crystallinity was confirmed.

Through the above steps, a ZnO buffer layer 22 made of single crystal ZnO and an AlN buffer layer 23 made of single crystal AlN are formed on a substrate 21 made of sapphire whose surface has been reverse sputtered. 5 and × ¹⁰ 18 ^cm carrier concentration ^-3 consists 8μm of Si-doped GaN having n-type base layer, an n-type contact layer made of 2μm of Si-doped GaN having a carrier concentration of 5 × ¹⁰ 18 ^{cm -3} is formed did. The substrate taken out from the apparatus after film formation was colorless and transparent, and the surface of the GaN layer (here, n-type contact layer) was a mirror surface.

(Formation of n-type cladding layer)
After the substrate on which the n-type contact layer was grown by the above procedure was introduced into the MOCVD apparatus, the substrate temperature was lowered to 760 ° C. using nitrogen as the carrier gas while circulating ammonia.
At this time, the supply amount of SiH ₄ was set while waiting for the temperature change in the furnace. The amount of SiH ₄ to be circulated was calculated in advance and adjusted so that the electron concentration of the Si-doped layer was 4 × 10 ¹⁸ cm ⁻³ . Ammonia continued to be fed into the furnace at the same flow rate.

Next, while circulating ammonia in the chamber, SiH ₄ gas and vapors of TMI and TEG generated by bubbling were circulated into the furnace, and a layer composed of Ga _0.99 In _0.01 N was 1.7 nm, Each layer of GaN was formed at 1.7 nm. After 19 cycles of such a film formation process, finally, a layer made of Ga _0.99 In _0.01 N was grown again at 1.7 nm. In addition, while this process was performed, the distribution of SiH ₄ was continued. As a result, an n-type cladding layer having a superlattice structure of Si-doped Ga _0.99 In _0.01 N and GaN was formed.

"Formation of light emitting layer"
Subsequently, the light emitting layer 7 was laminated | stacked by MOCVD method on the n-type clad layer produced in the said procedure.
The light emitting layer 7 is composed of a barrier layer made of GaN and a well layer made of Ga _0.92 In _0.08 N, and has a multiple quantum well structure. In forming the light emitting layer 7, a barrier layer is first formed on an n-type clad layer having a superlattice structure of Si-doped GaInN and GaN, and Ga _0.92 In _0.08 is formed on the barrier layer. A well layer made of N was formed. In this example, after repeating such a stacking procedure six times, the seventh barrier layer is formed on the sixth stacked well layer, and the barrier layers are formed on both sides of the light emitting layer 7 having the multiple quantum well structure. The structure was arranged.

First, supply of TEG and SiH _{4 into} the furnace is started with the substrate temperature kept at 760 ° C., an initial barrier layer made of GaN doped with Si for a predetermined time is formed to 0.8 nm, and supply of TEG and SiH ₄ is performed. Stopped. Thereafter, the temperature of the susceptor was raised to 920 ° C. Then, the supply of TEG and SiH _{4 into} the furnace was restarted, and the 1.7 nm intermediate barrier layer was grown while the substrate temperature remained at 920 ° C., and then the supply of TEG and SiH _{4 into} the furnace was stopped. did. Subsequently, the susceptor temperature is lowered to 760 ° C., the supply of TEG and SiH ₄ is started, and after the growth of the final barrier layer of 3.5 nm, the supply of TEG and SiH ₄ is stopped again, and the GaN Finished the growth of the barrier layer. By the three-stage film formation process as described above, a barrier layer made of Si-doped GaN having a total film thickness of 6 nm was formed, which was composed of three layers of an initial barrier layer, an intermediate barrier layer, and a final barrier layer. The amount of SiH ₄ was adjusted so that the Si concentration was 1 × 10 ¹⁷ cm ⁻³ .

After the growth of the barrier layer, TEG and TMI were supplied into the furnace to form a well layer, and a Ga _0.92 In _0.08 N layer (well layer) having a thickness of 3 nm was formed. .
Then, after the growth of the well layer made of Ga _0.92 In _0.08 N, the setting of the TEG supply amount was changed. Subsequently, the supply of TEG and SiH ₄ was restarted to form a second barrier layer.
By repeating the above procedure six times, a barrier layer made of 6 Si-doped GaN and a well layer made of 6 Ga _0.92 In _0.08 N were formed.

A sixth well layer composed of Ga _0.92 In _0.08 N was formed, and then a seventh barrier layer was formed. In the formation process of the seventh barrier layer, first, the supply of SiH ₄ is stopped, an initial barrier layer made of undoped GaN is formed, and then the substrate temperature is kept at 920 ° C. while the supply of TEG into the furnace is continued. The intermediate barrier layer was grown for a specified time at a substrate temperature of 920 ° C., and then the supply of TEG into the furnace was stopped. Subsequently, the substrate temperature was lowered to 760 ° C., the supply of TEG was started, and after the final barrier layer was grown, the supply of TEG was stopped again, and the growth of the barrier layer was completed. As a result, a barrier layer made of undoped GaN having a total film thickness of 4 nm was formed, consisting of three layers of an initial barrier layer, an intermediate barrier layer, and a final barrier layer.

  The light emitting layer 7 having a multiple quantum well structure including a well layer having a non-uniform thickness and a well layer having a uniform thickness was formed by the above procedure.

“Formation of p-type semiconductor layer”
Subsequent to the above steps, a p-type cladding layer having a superlattice structure composed of four layers of non-doped Al _0.06 Ga _0.94 N and three layers of Mg-doped GaN is formed using the same MOCVD apparatus. Further, a p-type contact layer made of Mg-doped GaN having a thickness of 200 nm was formed thereon to form a p-type semiconductor layer 6.

First, the substrate temperature was raised to 975 ° C. while supplying NH ₃ gas, and then the carrier gas was switched from nitrogen to hydrogen at this temperature. Subsequently, the substrate temperature was changed to 1050 ° C. Then, by supplying TMG and TMA into the furnace, a 2.5 nm layer made of non-doped Al _0.06 Ga _0.94 N was formed. Subsequently, without taking an interval, the TMA valve was closed and the Cp ₂ Mg valve was opened to form a Mg-doped GaN layer of 2.5 nm.
The above operation was repeated three times, and finally a p-type cladding layer having a superlattice structure was formed by forming an undoped Al _0.06 Ga _0.94 N layer.

Thereafter, only Cp ₂ Mg and TMG were supplied into the furnace to form a p-type contact layer made of 200-nm p-type GaN, thereby forming a p-type semiconductor layer 6.

The epitaxial wafer for a light emitting device (LED) manufactured as described above has a ZnO buffer layer 22 made of single crystal ZnO and an AlN buffer layer 23 made of single crystal AlN on a substrate 21 made of sapphire having a c-plane. An n-type contact layer composed of an 8 μm undoped GaN layer (underlying layer) and 2 μm Si-doped GaN having an electron concentration of 5 × 10 ¹⁸ cm ⁻³ in order from the substrate 21 side. A clad layer having an Si concentration of 10 ¹⁸ cm ⁻³ and having a superlattice structure composed of 20 layers of 1.7 nm Ga _0.99 In _0.01 N and 19 layers of 1.7 nm GaN (n-type clad Layer), a barrier layer made of Si-doped GaN having a layer thickness of 6 nm, and a layer thickness of 6 nm. And undoped well layer made of _Ga 0.92 _{In 0.08} N, the multiple quantum well structure (the light-emitting layer 7) consisting of a top-barrier layer made of undoped GaN, thickness 2.5nm of undoped Al ₀ and four layers consisting of _.06 Ga _0.94 N, p-type cladding layer composed of three layers having a thickness having a superlattice structure composed of 2.5nm of Mg-doped _Al 0.01 _{Ga 0.99} N And a p-type semiconductor layer 6 composed of a p-type contact layer made of Mg-doped GaN having a thickness of 200 nm.

“Formation of reflective p-type electrode layer”
Next, the reflective p-type electrode layer 5 was formed on the p-type semiconductor layer 6 side of the semiconductor layer 11. Specifically, first, a resist film was formed on the surface of the p-side semiconductor layer 6 cleaned with acid by a general photolithography technique in a portion other than the region where the reflective p-type electrode layer 5 was to be formed.
Next, this substrate is introduced into the vacuum chamber of the sputtering apparatus, and a Pt layer for forming ohmic contact, an Ag alloy layer for reflecting light, and an Au alloy layer for bonding the support substrate 24 are formed in sequence. Thus, the reflective p-type electrode layer 5 was formed. Finally, the resist film was removed.

“Formation of separation grooves”
Next, a separation groove 12 reaching the substrate 21 from the reflective p-type electrode layer 5 side was formed in the semiconductor layer 11. Specifically, a protective film in which only the region for forming the separation groove was exposed was formed by photolithography, and a groove reaching the substrate 21 was formed by performing laser scribing vertically and horizontally. At this time, a residue called “debris” generated by laser scribing was removed by phosphoric acid treatment. Then, the protective film was removed.

"Joining of support substrates"
Next, a support substrate 24 made of Si was bonded onto the reflective p-type electrode layer 5 by bonding to the p-type semiconductor layer 6 side of the semiconductor layer 11, that is, the reflective p-type electrode layer 5. Note that a bonding layer whose outermost surface is an Au alloy was formed in advance on the support substrate 24 made of Si, and bonded by an activated bonding method. In this embodiment, the support substrate 24 functions as a positive electrode due to the above configuration.

“Removal of ZnO buffer layer and substrate”
Next, the ZnO buffer layer 22 was dissolved and removed using hydrochloric acid as an etching solution, and the substrate 21 was peeled off from the semiconductor layer 11 and the AlN buffer layer 23 side. At this time, before the wafer is impregnated with hydrochloric acid, holes reaching the substrate 21 are formed at a plurality of locations on the wafer by using a narrow diameter drill by a technique called grooving, and the etching solution is passed through the holes to the ZnO buffer layer 22. I was going to go around.

"Roughening of the light extraction surface"
Next, the AlN buffer layer 23 on the light extraction surface 11a and the base layer constituting the n-type semiconductor layer 8 were removed, and the light extraction surface 11a of the n-type semiconductor layer 8 was roughened.
Specifically, the light extraction surface 11a of the n-type semiconductor layer 8 was immersed in a heated KOH solution to remove the AlN buffer layer 23 and the base layer, and the light extraction surface 11a was roughened.

“Formation of negative electrode (n-type electrode)”
Next, a negative electrode (n-type electrode) 9 was formed on the n-type semiconductor layer 8 side by the procedure described below.
Specifically, first, a protective film made of a resist is formed in a portion other than a region where the negative electrode 9 is formed by a generally known photolithography technique, and an n-type semiconductor layer in a region where no resist film is formed A negative electrode 9 was formed on 8 by sputtering.

"Formation of insulating film"
Next, the insulating film 10 made of SiO ₂ was formed by using a sputtering method so as to cover the side surface 11 b of each semiconductor layer 11 and the outer peripheral portion of the light extraction surface 11 a of each semiconductor layer 11.
Specifically, after the insulating film 10 is formed on the entire semiconductor layer 11, a resist is formed on a portion other than the central portion of the light extraction surface 11a, and dry etching is performed to obtain the insulating film 10 having the above shape.

“Division into element units”
Next, the support substrate 24 as a base was cut along the semiconductor layer 11 divided into a plurality of parts, and the wafer on which the semiconductor layer 11 was laminated was divided into element units.
Specifically, the support substrate 24 was irradiated with a laser by a laser scribing method along the dividing grooves 12 between the plurality of semiconductor layers 11 formed on the positive electrode 4 and cut.
Thus, a plurality of light emitting elements 1 as shown in FIG. 11 (see also FIG. 1) were manufactured.

“Creating an LED”
Subsequently, LED (lamp) was produced using the light emitting element 1 obtained by the method of each said Example.
Specifically, as shown in FIG. 15, the light emitting element 1 in which the positive electrode 4 and the negative electrode 9 are formed by the above-described procedure is used, and one of the two frames (frame 81 in FIG. 15) is used. The light emitting element 1 is bonded with a conductive adhesive such as silver paste, and the positive electrode 4 (see reference numeral 4 shown in FIG. 1) of the light emitting element 1 is joined to the frame 81, and the negative electrode 9 (see reference numeral 9 shown in FIG. 1). The wire 83 was joined to the frame 82. Then, the periphery of the light emitting element 1 was sealed with a mold 84 made of a transparent resin, so that a shell-type lamp 80 was produced.

  When a forward current was passed between the p-side (positive electrode 4) and n-side (negative electrode 9) electrodes of the lamp 80 produced as described above, the forward voltage at a current of 20 mA was 3.1V. Moreover, when the light emission state was observed through the light extraction surface 11a of the n-type semiconductor layer 8, the light emission wavelength was 450 nm, and the light emission output was 35 mW. Such characteristics of the lamp (light-emitting element) were obtained with no variation for light-emitting elements manufactured from almost the entire surface of the manufactured wafer.

[Example 2]
In this comparative example, a flip-chip type light emitting element 50 as illustrated in FIG. 14 was manufactured using a semiconductor substrate (see FIG. 2A and the like) having the same LED laminated structure as in Example 1 above. . Specifically, until the “formation of the p-type semiconductor layer” in Example 1 above, a semiconductor wafer is manufactured by the same procedure except that the base layer is undoped, and then the procedure described below is performed. A light emitting device and a lamp were produced.

“Formation of positive electrode (p-type electrode)”
Using a wafer in which each layer is formed on a substrate (not shown) by the same process up to the “formation of the p-type semiconductor layer” in the first embodiment, the p-type semiconductor layer 56 of the semiconductor layer is used as in the first embodiment. A reflective p-type electrode layer 55 was formed on the side, and then a positive electrode (p-type electrode) 54 was formed thereon.
Specifically, first, a resist film was formed on the surface of the p-side semiconductor layer 56 cleaned with acid by a general photolithography technique in a portion other than the region where the positive electrode 54 was to be formed.
Next, this substrate is introduced into a vacuum chamber of a sputtering apparatus, and sequentially formed a Pt layer for ohmic contact formation, an Ag alloy layer for light reflection, and an Au alloy layer for bonding a support substrate, A reflective p-type electrode layer 55 was formed, and then a positive electrode 54 was formed on the reflective p-type electrode layer 55.

“Formation of negative electrode (n-type electrode)”
Next, the negative electrode 59 was formed on the n-type semiconductor layer 58 by the procedure described below.
Specifically, first, a protective film made of a resist is formed in a portion other than a region where the negative electrode 59 is formed by a generally known photolithography technique, and a dry etching method is performed using a gas composed of only SiCl _4. In addition to the p-type semiconductor layer 56 and the light emitting layer 57 in the region where the resist film is not formed, a part of the n-type semiconductor layer 58 was removed to expose the n-type semiconductor layer 58. Next, after removing dirt on the surface of the n-type semiconductor layer 58 exposed by wet processing, a negative electrode 59 was formed on the n-type semiconductor layer 58 by sputtering. Similarly to the positive electrode 54, an Au bonding layer for bonding to the support substrate is formed on the outermost surface of the negative electrode 59, and each height is finally substantially equal to the height of the outermost surface of the positive electrode 54. The electrode thickness was designed and adjusted. Finally, the resist film was removed.

“Formation of separation grooves”
Next, a separation groove reaching the substrate from the positive electrode 54 side was formed in the semiconductor layer. Specifically, a protective film exposing only the region where the separation groove is to be formed was formed by photolithography, and laser scribe was applied vertically and horizontally to form the separation groove reaching the substrate. At this time, a residue called “debris” generated by laser scribing was removed by phosphoric acid treatment. Then, the protective film was removed.

“Division into element units”
Next, the substrate was cut along a plurality of divided semiconductor layers, and the wafer on which the semiconductor layers were stacked was divided into element units.
Specifically, the laser was radiated from the substrate side along the dividing groove between each of the chip patterns formed in the semiconductor layer by a laser scribing method and cut.

"Joining of support substrates"
Next, the divided chips were placed on the support substrate 51 made of Ge with the sapphire surface facing up, and bonded by eutectic bonding. Specifically, a substrate having a wiring pattern (not shown) formed of Au alloy on the surface of a substrate made of insulating Ge is used as the support substrate 51, and the positive electrode 54 on the p-type semiconductor layer 56 side of the semiconductor layer is used. The bonding layer formed on the outermost layer of the negative electrode 59 and the wiring pattern on the support substrate 51 were placed in conformity and bonded by a method called a pulse heating method.

“Removal of ZnO buffer layer and substrate”
Next, the ZnO buffer layer (not shown) was dissolved and removed using hydrochloric acid as an etching solution, and the substrate was peeled off from the semiconductor layer and AlN buffer layer 53 side.

"Roughening of the light extraction surface"
Next, the AlN buffer layer 53 on the light extraction surface and a base layer (not shown) were removed, and the light extraction surface of the n-type semiconductor layer 58 was roughened.
Specifically, the AlN buffer layer 53 and the base layer were removed by immersing the light extraction surface of the n-type semiconductor layer 58 in a heated KOH solution, and the light extraction surface was roughened.

"Formation of insulating film"
Next, an insulating film made of SiO ₂ was formed using a sputtering method so as to cover the side surface of each semiconductor layer and the outer peripheral portion of the light extraction surface of each semiconductor layer.
Specifically, after an insulating film was formed on the entire semiconductor layer, a resist was formed on a portion other than the central portion of the light extraction surface, and dry etching was performed to obtain the insulating film having the above shape.
As a result, a plurality of light-emitting elements having a flip chip type (not shown) were manufactured.

“Creating an LED”
Subsequently, LED (lamp) was produced using the light emitting element obtained by the method of each of the above examples (see also FIG. 15).
Specifically, by wire bonding to the wire bonding region of the wiring pattern drawn on the support substrate, wiring was performed on the lead frame in the same manner as a normal two-wire chip. And the SMD type package was produced by sealing the periphery of a light emitting element with the mold which consists of transparent resin.

  When a forward current was passed between the p-side (positive electrode) and n-side (negative electrode) electrodes of the package produced as described above, the forward voltage at a current of 20 mA was 3.1V. Moreover, when the light emission state was observed through the light extraction surface 11a of the n-type semiconductor layer 8, the light emission wavelength was 447 nm and the light emission output was 30 mW. Such characteristics of the lamp (light-emitting element) were obtained with no variation for light-emitting elements manufactured from almost the entire surface of the manufactured wafer.

[Comparative example]
In this comparative example, the same procedure as in Example 1 was used, except that a ZnO buffer layer was formed on the c-plane of a sapphire substrate, and then a semiconductor layer was formed without forming an AlN buffer layer. Each step of manufacturing a light emitting element was performed.

  However, in this comparative example, after forming the foundation layer (n-type semiconductor layer) constituting the semiconductor layer by using the MOCVD method, the stacked structure was confirmed. As a result, no ZnO buffer layer remained on the substrate, It was confirmed that GaN was formed on the substrate. However, it has become clear that this GaN peels off from the substrate with only a slight stimulus to the wafer. This is probably because when the semiconductor layer was grown on the ZnO buffer layer by the MOCVD method, the ZnO buffer layer was sublimated, so that GaN was not formed in a stable state. For this reason, in this comparative example, subsequent measurement of the XRC half width, etc. became impossible.

[Experimental example]
In this experimental example, first, a sample substrate in which a ZnO buffer layer was formed on a substrate made of sapphire and a sample substrate in which an AlN buffer layer was further formed thereon were produced under the same conditions as in experimental example 1. These sample substrates are housed in a vacuum chamber having a plasma generation mechanism, exposed to nitrogen plasma at different temperatures, and the X-ray peak values of the sample substrates processed in the chamber are measured. This is shown in 16 graphs.

As shown in the graph of FIG. 16, in the sample substrate (□ mark) on which only the ZnO buffer layer was formed, the X-ray peak intensity of ZnO decreased at a processing temperature of about 500 ° C., and at a processing temperature of 700 ° C. or higher. It was observed that the ZnO film thickness decreased. Further, at this time, it was revealed that a reaction layer was formed on the surface of the ZnO buffer layer even when damage was suppressed.
On the other hand, in the sample substrate in which the AlN buffer layer is formed on the ZnO buffer layer (marked with ◇), even if the processing temperature is close to 1000 ° C., there is no significant change in the X-ray peak intensity of ZnO. It was.
From this experimental example, it can be said that ZnO is decomposed when it is brought into contact with an activated nitrogen atom species such as a plasma state or ammonia at a high temperature. Furthermore, it has become clear that this decomposition reaction can be suppressed by covering the ZnO buffer layer with an AlN buffer layer.

  Based on the above results, the method for manufacturing a gallium nitride-based compound semiconductor light-emitting device according to the present invention causes the substrate to be peeled from the compound semiconductor layer without losing the buffer layer in the compound semiconductor layer forming step. It is apparent that the light emitting device can be manufactured with high yield and high efficiency. It is also clear that the gallium nitride compound semiconductor light emitting device according to the present invention is excellent in light emission characteristics.

1 is a schematic cross-sectional view showing an example of a gallium nitride-based compound semiconductor light emitting device according to the present invention. It is a cross-sectional schematic diagram which shows an example of the laminated structure of the gallium nitride type compound semiconductor which concerns on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining an example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining the other example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is process drawing explaining the other example of the manufacturing method of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is a cross-sectional schematic diagram which shows the other example of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is a cross-sectional schematic diagram which shows the other example of the gallium nitride type compound semiconductor light-emitting device based on this invention. It is a cross-sectional schematic diagram which shows an example of the lamp | ramp comprised using the gallium nitride type compound semiconductor light-emitting device based on this invention. It is a figure explaining the Example of the laminated structure of the gallium nitride type compound semiconductor which concerns on this invention, and is a graph which shows the peak value of the X-ray measurement of a laminated structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 3, 50 ... Gallium nitride type compound semiconductor light emitting element 2, 2A ... Laminated structure of gallium nitride type compound semiconductor (semiconductor laminated structure) 4, 40, 54 ... Positive electrode, 5, 55 ... Reflective p-type electrode layer , 6, 56 ... p-type semiconductor layer, 7, 57 ... light emitting layer, 8, 58 ... n-type semiconductor layer, 9, 59 ... negative electrode, 11 ... semiconductor layer, 11a ... light extraction surface, 21 ... substrate, 22 ... ZnO Buffer layer, 22a ... surface (ZnO buffer layer), 22b ... side surface (ZnO buffer layer), 23, 53 ... AlN buffer layer, 27 ... underlayer, 41 ... metal plating layer (positive electrode), 42 ... seed layer (positive electrode)

Claims (37)

A buffer layer forming step of laminating a ZnO buffer layer and an AlN buffer layer in this order on a substrate;
Forming a semiconductor layer made of a gallium nitride compound on the AlN buffer layer; and
And a removing step of peeling off the substrate by removing the ZnO buffer layer.   The buffer layer forming step is characterized in that the ZnO buffer layer is formed using any one of a molecular beam epitaxy (MBE) method, a pulse laser deposition (PLD) method, and a sputtering method. Item 2. A method for producing a gallium nitride-based compound semiconductor light-emitting device according to Item 1.   3. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 2, wherein the buffer layer forming step forms the ZnO buffer layer using a sputtering method.   The buffer layer forming step is characterized in that the AlN buffer layer is formed using any one of a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, and a sputtering method. The manufacturing method of the gallium nitride type compound semiconductor light-emitting device in any one of Claims 1-3.   5. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 4, wherein the buffer layer forming step forms the AlN buffer layer using a sputtering method. 6. The nitriding according to claim 4, wherein the buffer layer forming step forms the AlN buffer layer at a temperature of 600 ° C. or less using nitrogen (N ₂ ) gas as a nitrogen source. A method for manufacturing a gallium compound semiconductor light emitting device.   In the buffer layer forming step, the AlN buffer layer is formed on the substrate so as to be larger than the ZnO buffer layer in plan view so that the AlN buffer layer covers the surface and side surfaces of the ZnO buffer layer. The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 1, wherein the gallium nitride-based compound semiconductor light-emitting element is formed.   8. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 1, wherein in the removing step, the ZnO buffer layer is dissolved and removed using an etching method. 9.   9. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 8, wherein in the removing step, the ZnO buffer layer is dissolved and removed by an etching method using HCl or oxalic acid.   10. The semiconductor layer forming step of forming a semiconductor layer by sequentially laminating an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the AlN buffer layer. The manufacturing method of the gallium nitride type compound semiconductor light-emitting device of any one of these.   11. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 10, wherein the semiconductor layer forming step further includes forming an underlayer between the AlN buffer layer and the n-type semiconductor layer.   12. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 11, wherein the underlayer and / or the n-type semiconductor layer is formed using a metal organic chemical vapor deposition (MOCVD) method.   13. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 11, wherein a total film thickness of the n-type semiconductor layer and the base layer is 15 μm or less.   13. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 11, wherein a total film thickness of the n-type semiconductor layer and the base layer is 10 μm or less.   13. The method of manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 11, wherein a total film thickness of the n-type semiconductor layer and the base layer is 4 μm or less.   Between the semiconductor layer forming step and the removing step, a support substrate bonding step for bonding a support substrate made of an oxide or nitride of Si is provided on the p-type semiconductor layer side of the semiconductor layer. The method for producing a gallium nitride-based compound semiconductor light-emitting element according to any one of claims 10 to 15, wherein:   After the removing step, a negative electrode is formed on the n-type semiconductor layer side of the semiconductor layer, and then a temporary attachment substrate is attached to the negative electrode, and then the support substrate is peeled off to remove the p-type of the semiconductor layer. 17. The method according to claim 16, further comprising an electrode forming step of exposing the semiconductor layer side, then forming a positive electrode on the exposed p-type semiconductor layer, and then peeling the temporary bonding substrate from the negative electrode. The manufacturing method of the gallium nitride type compound semiconductor light emitting element of description.   The support substrate bonding step of bonding a support substrate made of Si to the p-type semiconductor layer side of the semiconductor layer is provided between the semiconductor layer forming step and the removing step. The manufacturing method of the gallium nitride type compound semiconductor light-emitting device of any one of 10-10.   11. A plating step for forming a positive electrode made of metal plating on the p-type semiconductor layer side of the semiconductor layer between the semiconductor layer forming step and the removing step is provided. The method for manufacturing a gallium nitride-based compound semiconductor light-emitting element according to claim 15.   The gallium nitride-based compound semiconductor light emitting device according to claim 18, further comprising a negative electrode forming step of forming a negative electrode on the n-type semiconductor layer side of the semiconductor layer after the removing step. Device manufacturing method. A substrate,
A ZnO buffer layer and an AlN buffer layer sequentially stacked on the substrate;
A laminated structure of a gallium nitride compound semiconductor element, comprising: a semiconductor layer formed on the AlN buffer layer and made of a gallium nitride compound.   The laminated structure of a gallium nitride-based compound semiconductor device according to claim 21, wherein the substrate is made of any one of sapphire, silicon, SiC, and spinel.   23. The stacked structure of a gallium nitride-based compound semiconductor device according to claim 21, wherein the ZnO buffer layer is made of single-crystal ZnO.   The laminated structure of a gallium nitride-based compound semiconductor device according to any one of claims 21 to 23, wherein a surface of the ZnO buffer layer has a Zn polarity.   25. The stacked structure of a gallium nitride-based compound semiconductor device according to claim 21, wherein the ZnO buffer layer has a thickness in a range of 10 to 1000 nm.   The stacked structure of a gallium nitride-based compound semiconductor device according to any one of claims 21 to 25, wherein the AlN buffer layer is made of single crystal AlN.   27. The stacked structure of a gallium nitride-based compound semiconductor device according to any one of claims 21 to 26, wherein the AlN buffer layer is made of polycrystalline AlN having columnar crystals.   28. The laminated structure of a gallium nitride-based compound semiconductor element according to claim 21, wherein the thickness of the AlN buffer layer is in a range of 10 to 100 nm.   On the substrate, the AlN buffer layer is formed larger than the ZnO buffer layer in plan view, and the AlN buffer layer is formed to cover the surface and side surfaces of the ZnO buffer layer. The laminated structure of the gallium nitride-based compound semiconductor device according to any one of claims 21 to 28.   30. The gallium nitride compound according to claim 21, wherein the semiconductor layer is formed by sequentially laminating an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the AlN buffer layer. A stacked structure of semiconductor elements.   31. The stacked structure of a gallium nitride-based compound semiconductor device according to claim 30, wherein the semiconductor layer further includes an underlayer provided between the AlN buffer layer and the n-type semiconductor layer.   32. The stacked structure of a gallium nitride-based compound semiconductor device according to claim 31, wherein a total film thickness of the base layer and the n-type semiconductor layer is 15 μm or less.   32. The stacked structure of a gallium nitride-based compound semiconductor device according to claim 31, wherein a total film thickness of the base layer and the n-type semiconductor layer is 10 μm or less.   32. The multilayer structure of a gallium nitride-based compound semiconductor device according to claim 31, wherein a total film thickness of the base layer and the n-type semiconductor layer is 4 μm or less. A structure in which the AlN buffer layer is exposed by removing the ZnO buffer layer and the substrate provided in the stacked structure of the gallium nitride compound semiconductor device according to any one of claims 30 to 34. A laminated structure is used,
Furthermore, a negative electrode is provided on the n-type semiconductor layer exposed by removing at least a part of the AlN buffer layer, and a positive electrode is provided on the p-type semiconductor layer. Compound semiconductor light emitting device.   A gallium nitride-based compound semiconductor light-emitting element obtained by the manufacturing method according to any one of claims 1 to 20.   37. A lamp comprising the gallium nitride compound semiconductor light-emitting device according to claim 35 or 36.

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