KR20120073396A - Light emitting diode and method of fabricating the same - Google Patents

Abstract

PURPOSE: A light emitting diode and a manufacturing method thereof are provided to improve the extraction efficiency of light generated in an active layer by forming a rough surface on the upper side of an n type compound semiconductor layer. CONSTITUTION: A semiconductor laminate structure(30) is formed on a support substrate(60). The semiconductor laminate structure includes a p type compound semiconductor layer(29), an active layer(27), and an n type compound semiconductor layer(25). The n type compound semiconductor layer includes a plasma processing area(25a). An n-electrode pad is formed on the semiconductor laminate structure. An electrode extension unit(51a) is extended from the n-electrode pad. An upper insulation layer(47) is interposed between the n-electrode pad and the semiconductor laminate structure.

Description

LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME

The present invention relates to a light emitting diode and a method of manufacturing the same.

In general, nitrides of group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition type energy band structure. It is attracting much attention as a substance. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. Is grown through the process. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used. However, sapphire is an electrically insulator, thus limiting the light emitting diode structure. Accordingly, recently, epitaxial layers, such as nitride semiconductor layers, are grown on dissimilar substrates such as sapphire, bonding supporting substrates to the epitaxial layers, and then separating the dissimilar substrates using a laser lift-off technique. A technique for manufacturing a high efficiency light emitting diode having a structure has been developed.

In general, the vertical light emitting diode has a current distribution performance superior to that of a conventional horizontal light emitting diode with p-GaN located below and n-GaN located above, and thermal conductivity is higher than that of sapphire. By adopting a high support substrate, the heat dissipation performance is excellent. Furthermore, by anisotropically etching the surface of n-GaN by PEC (photon enhanced chemical) etching or the like to form a roughened surface, upward light extraction efficiency may be greatly improved.

In this case, in order to supply external power to the light emitting diode, an electrode pad is formed on the surface of the n-GaN. However, the n-GaN and the electrode pad are made of different materials, and thus, a contact resistance is generated between the n-GaN and the electrode pad, and the contact resistance causes the luminous efficiency of the light emitting diode to decrease.

It is an object of the present invention to provide a light emitting diode with improved contact resistance and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode having improved current dispersing performance and a method of manufacturing the same.

It is still another object of the present invention to provide a light emitting diode having improved light extraction efficiency and a method of manufacturing the same.

In order to achieve the above object, according to an aspect of the present invention, a conductive support substrate; A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; An n-electrode pad disposed on the semiconductor laminate structure; An electrode extension extending from the n-electrode pad; And an upper insulating layer interposed between the n-electrode pad and the semiconductor laminate, wherein at least the n-type compound semiconductor layer in contact with the electrode extension includes a plasma treatment region plasma-treated by an inert gas. A light emitting diode is provided.

The light emitting diode may further include a bonding metal interposed between the support substrate and the semiconductor laminate.

The support substrate may include a first metal layer including at least one of tungsten (W) or molybdenum (Mo); And a second metal layer having a higher coefficient of thermal expansion than the first metal layer, and having a symmetrical structure disposed on upper and lower surfaces of the first metal layer, wherein a bonding layer may be formed between the first metal layer and the second metal layer.

The second metal layer may include copper (Cu).

The bonding layer may include at least one of Ni, Ti, Cr, and Pt.

The light emitting diode may further include a lower bonding metal formed on a lower surface of the second metal layer symmetrically to the bonding metal interposed between the support substrate and the semiconductor laminate.

The light emitting diode may include a reflective metal layer disposed between the support substrate and the semiconductor stacked structure, having ohmic contact with the semiconductor stacked structure, and having a groove exposing the semiconductor stacked structure; An intermediate insulating layer disposed between the reflective metal layer and the support substrate and covering the groove and covering the reflective metal layer, the intermediate insulating layer having openings exposing the reflective metal layer; And a barrier metal layer disposed between the support substrate and the intermediate insulating layer and covering the reflective metal layer exposed to the openings of the intermediate insulating layer.

The n-electrode pad and the electrode extension may be positioned above the groove area.

The reflective metal layer is composed of a plurality of plates, the intermediate insulating layer covers the sides and edges of the plurality of plates, and the plurality of plates are respectively exposed by openings of the intermediate insulating layer. Can be.

The light emitting diode includes a plurality of n-electrode pads, and includes a plurality of electrode extensions respectively extending from the plurality of n-electrode pads, wherein the plurality of n-electrode pads and the plurality of electrode extensions are provided. It may be located above an area between a plurality of plates.

The semiconductor laminate structure may have a roughened surface, and the upper insulating layer may cover the roughened surface, and the upper insulating layer may form an uneven surface along the roughened surface.

The semiconductor stack structure may have a flat surface, and the n-electrode pad and the electrode extension may be located on the flat surface.

The electrode extension may contact a flat surface of the semiconductor laminate.

The roughened surface may be located below the electrode extension.

In order to achieve the above object, according to another aspect of the present invention, forming a semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer and an n-type compound semiconductor layer, the semiconductor layer so that the n-type compound semiconductor layer is exposed Forming a structure; Forming an upper insulating layer having an opening exposing a portion of the n-type compound semiconductor layer; And forming an n-electrode pad and an electrode extension extending from the n-electrode pad on the n-type compound semiconductor layer having the upper insulating layer, wherein the n-electrode pad is formed on the upper insulating layer. The extension part may be formed to contact the n-type compound semiconductor layer through the opening, wherein the n-type compound semiconductor layer in contact with at least the electrode extension part is plasma-treated using an inert gas to form the n-type compound semiconductor layer. A method of manufacturing a light emitting diode is provided, further comprising forming a plasma processing region in the compound semiconductor layer.

Forming a semiconductor laminate structure comprising the p-type compound semiconductor layer, the active layer and the n-type compound semiconductor layer, the step of forming to expose the n-type compound semiconductor layer is a p-type compound semiconductor layer, an active layer and a growth substrate; forming a semiconductor laminate including an n-type compound semiconductor layer; Attaching a conductive support substrate on the semiconductor laminate structure via a bonding metal; And removing the growth substrate to expose the semiconductor laminate structure, and exposing the n-type compound semiconductor layer.

The light emitting diode manufacturing method may further include forming a reflective metal layer having a groove exposing the semiconductor laminate structure on the semiconductor laminate structure before attaching the support substrate to the semiconductor laminate structure; Forming an intermediate insulating layer covering side and edge of the reflective metal layer, the intermediate insulating layer having an opening exposing the reflective metal layer; And forming a barrier metal layer connecting to the reflective metal layer through the opening of the intermediate insulating layer.

The light emitting diode manufacturing method may further include forming a mask pattern on the exposed semiconductor laminate structure after removing the growth substrate to expose the semiconductor laminate structure; And anisotropically etching the surface of the semiconductor laminate structure using the mask pattern as an etch mask to form a rough surface together with a flat surface, wherein the opening exposes a portion of the n-type compound semiconductor layer. The forming of the upper insulating layer may include forming an upper insulating layer covering the surface of the semiconductor laminate structure, and forming the upper insulating layer so that the opening exposes a portion of the flat surface. .

According to the present invention, there is an effect of providing a light emitting diode having improved contact resistance and a method of manufacturing the same.

Moreover, according to this invention, there exists an effect which provides the light emitting diode and its manufacturing method which the current dispersion performance improved.

In addition, according to the present invention, there is an effect of providing a light emitting diode and a method of manufacturing the light extraction efficiency is improved.

1 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention.
2 is a cross-sectional view taken along the cutting line AA of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
3 is a cross-sectional view taken along the line BB of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
4 is a cross-sectional view taken along the cutting line CC of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
5 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, each of which is a cross-sectional view corresponding to the cutting line AA of FIG. 1.
FIG. 12 is a graph illustrating a result of measuring Vf when plasma treatment is performed in some processes of manufacturing a light emitting diode according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention, and FIGS. 2 to 4 are cross-sectional views taken along the cutting lines A-A, B-B, and C-C of FIG. 1, respectively. In FIG. 1, the reflective metal layer 31 and the intermediate insulating layer 33 positioned under the semiconductor stacked structure 30 are indicated by dotted lines.

1 to 4, the light emitting diode includes a support substrate 60, a semiconductor laminate 30, a reflective metal layer 31, an intermediate insulating layer 33, a barrier metal layer 35, and an upper insulating layer 47. ), an n-electrode pad 51 and an electrode extension 51a. In addition, the light emitting diode may include a bonding metal 43.

The support substrate 60 is separated from the growth substrate for growing the compound semiconductor layers, and is a secondary substrate attached to the compound semiconductor layers that have been grown. The support substrate 60 may be a conductive substrate, for example, a metal substrate.

The support substrate 60 includes a first metal layer 64 positioned in the center of the support substrate 60 and second metal layers 62 and 66 symmetrically disposed above and below the first metal layer 64. do.

The first metal layer 64 may include, for example, at least one of tungsten (W) or molybdenum (Mo). The second metal layers 62 and 66 may have a higher thermal expansion coefficient than the first metal layer 64 and may include, for example, copper (Cu).

Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66. In addition, a bonding layer 61 is formed between the bonding metal 43 and the second metal layer 62. These bonding layers 61, 63, 65 may comprise at least one of Ni, Ti, Cr, and Pt. In addition, a lower bonding metal 68 may be formed on the lower surface of the second metal layer 66 formed on the lower surface of the first metal layer 64 through the bonding layer 67.

The lower bonding metal 68 is a structure symmetrical to the bonding metal 43 interposed between the support substrate 60 and the semiconductor stack 30, and may be made of the same material as the bonding metal 43. For example, it may be Au or Au-Sn (80 / 20wt%). The lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.

The support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 formed symmetrically on the top and bottom surfaces of the first metal layer 64. For example, tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and strength compared to, for example, copper (Cu) constituting the second metal layers 62 and 66. .

The thickness of the first metal layer 64 is thicker than the thickness of the second metal layers 62 and 66. Accordingly, forming the second metal layers 62 and 66 on the upper and lower surfaces of the first metal layer 64 is a process rather than having the opposite structure (the structure in which the first metal layer is formed on the upper and lower surfaces of the second metal layer). Even more preferred.

In addition, in order for the support substrate 60 to have a thermal expansion coefficient similar to that of the growth substrate and the semiconductor stack 30, the thickness of the first metal layer 64 and the thickness of the second metal layers 62 and 66 are appropriate. Can be adjusted.

The support substrate 60 may be manufactured separately from the semiconductor stack 30 and then bonded to the barrier metal layer 35 through the bonding metal 43. Alternatively, the support substrate 60 may be formed by plating on the barrier metal layer 35. As the plating method used when forming the support substrate 60, an electrolytic plating method for depositing a metal using a rectifier and an electroless plating method for depositing a metal using a reducing agent may be used. , Electron beam deposition, sputtering, chemical vapor deposition, etc. may be used.

The semiconductor laminate 30 is positioned on the support substrate 60 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25.

Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 60 side than the n-type compound semiconductor layer 25, similar to a general vertical light emitting diode.

The semiconductor stacked structure 30 may be located on a portion of the support substrate 60. That is, the support substrate 60 has a relatively larger area than the semiconductor stack 30, and the semiconductor stack 30 is located in an area surrounded by an edge of the support board 60.

The n-type compound semiconductor layer 25 includes a plasma processing region 25a. The plasma processing region 25a may be disposed at least under the electrode extension 51a to be described later to contact the electrode extension 51a. The plasma processing region 25a may be a region in which the plasma processing region 25a is plasma treated using an inert gas such as He or Ar. That is, the plasma treatment region 25a may be a region having a cation implantation effect by plasma treatment of the inert gas. The plasma processing region 25a serves to reduce the contact resistance between the electrode extension 51a and the n-type compound semiconductor layer 25. The light emitting diode has a current dispersion performance due to the decrease in the contact resistance. It is possible to improve the light extraction efficiency. In this case, although the plasma processing region 25a is shown to be provided only under the electrode extension part 51a, the present invention is not limited thereto and may be provided on the entire surface of the n-type compound semiconductor layer 25. have.

The n-type compound semiconductor layer 25, the active layer 27, and the p-type compound semiconductor layer 29 may be formed of a III-N series compound semiconductor, such as (Al, Ga, In) N semiconductor.

The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may be a single layer or multiple layers, respectively. For example, the n-type compound semiconductor layer 25 and / or the p-type compound semiconductor layer 29 may include a contact layer and a cladding layer, and may also include a superlattice layer.

In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. Since the n-type compound semiconductor layer 25 having a relatively low resistance is located opposite the support substrate 60, it is easy to form a roughened surface R on the top surface of the n-type compound semiconductor layer 25. The roughened surface R improves the extraction efficiency of light generated in the active layer 27.

The p-electrodes 31 and 35 may be positioned between the p-type compound semiconductor layer 29 and the support substrate 60 and may include a reflective metal layer 31 and a barrier metal layer 35.

The reflective metal layer 31 makes ohmic contact with the p-type compound semiconductor layer 29 between the semiconductor stacked structure 30 and the support substrate 41. The reflective metal layer 31 may include a reflective layer, for example Ag. The reflective metal layer 31 is located below the semiconductor stacked structure 30. As shown in FIG. 1, the reflective metal layer 31 may be formed of a plurality of plates, and grooves are formed between the plurality of plates. The semiconductor stacked structure 30 is exposed through the groove.

The intermediate insulating layer 33 is positioned between the semiconductor stacked structure 30 and the support substrate 60. The intermediate insulating layer 33 fills spaced spaces between the reflective metal layers 31. That is, the intermediate insulating layer 33 covers the side and edges of the reflective metal layer 31, for example, a plurality of plates, and has openings that expose the reflective metal layer 31. The intermediate insulating layer 33 may be formed of a single layer or multiple layers of a silicon oxide film or a silicon nitride film, and also repeatedly stacks insulating layers having different refractive indices, such as SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ . One distributed Bragg reflector.

The side surface of the reflective metal layer 31 may be prevented from being exposed to the outside by the intermediate insulating layer 33. The intermediate insulating layer 33 may also be located below the side surface of the semiconductor laminate 30, thus preventing leakage current through the side of the semiconductor laminate 30.

In addition, the intermediate insulating layer 33 may be disposed under the electrode pad extension part 51a, the plasma processing region 25a, and the n-electrode pad 51. Therefore, the intermediate insulating layer 33 is positioned at a position where the current supplied to the electrode extension part 51a passes through the semiconductor laminate structure 30 at the shortest distance, that is, the lower part of the electrode extension part 51a. The reflective metal layer 31 is positioned on the side of the intermediate insulating layer 33 so that a current applied through the electrode pad extension 51a or the reflective metal layer 31 is uniform throughout the semiconductor laminate structure 30. Will flow.

The barrier metal layer 35 covers the intermediate insulating layer 33 under the intermediate insulating layer 33 and is connected to the reflective metal layer 31 through the opening of the intermediate insulating layer 33. The barrier metal layer 35 protects the reflective metal layer 31 by preventing diffusion of a metal material, eg, Ag, of the reflective metal layer 31. The barrier metal layer 35 may include, for example, a Ni layer. The barrier metal layer 35 may be located on the front surface of the support substrate 41.

Meanwhile, the support substrate 60 may be bonded to the barrier metal layer 35 through a bonding metal 43. The bonding metal 43 may be formed using eutectic bonding with Au or Au-Sn (80 / 20wt%), for example.

Meanwhile, an upper surface of the semiconductor stacked structure 30, that is, the surface of the n-type compound semiconductor layer 25 may have a roughened surface R and a flat surface. As shown in Figs. 2 to 4, the n-electrode pad 51 and the electrode extension 51a are located on a flat surface. As shown in the drawing, the n-electrode pad 51 and the electrode extension part 51a are defined on a flat surface and may have a narrow width compared to the width of the flat surface.

Therefore, the n-electrode pad 51 and the electrode extension part 51a can be prevented from peeling off by the occurrence of an undercut, etc. in the semiconductor laminated structure 30, and reliability can be improved. In addition, the electrode extension part 51a may be provided on the plasma processing region 25a where the foreign matter on the surface is removed by the plasma treatment and the adhesion thereof is increased, thereby preventing the peeling of the electrode extension portion 51a, thereby increasing reliability.

On the other hand, the rough surface (R) may be located below the flat surface. That is, the roughened surface R is located below the n-electrode pad 51 and the electrode extension 51a.

On the other hand, the n-electrode pad 51 is positioned on the semiconductor stacked structure 30, and the electrode extension part 51a extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor stacked structure 30, and the electrode extensions 51a may extend from the n-electrode pads 51, respectively. . The electrode extensions 51a may be electrically connected to the semiconductor stacked structure 30 and may directly contact the n-type compound semiconductor layer 25.

The n-electrode pad 51 may also be located above the groove region of the reflective metal layer 31. That is, under the n-electrode pad 51, there is no reflective metal layer 31 in ohmic contact with the p-type compound semiconductor layer 29. Instead, the intermediate insulating layer 33 is positioned. In addition, the electrode extension part 51a is also positioned above the groove area of the reflective metal layer 31. As shown in FIG. 1, an electrode extension part 51a may be positioned on an area between the plates in the reflective metal layer 31 including a plurality of plates. Preferably, the width of the groove region of the reflective metal layer 31, for example, the region between the plurality of plates is wider than the width of the electrode extension 51a. Accordingly, it is possible to prevent the current from flowing intensively directly below the electrode extension part 51a.

Meanwhile, the upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor stacked structure 30. The upper insulating layer 47 prevents current from flowing directly from the n-electrode pad 51 to the semiconductor stack 30, particularly in which current is concentrated directly under the n-electrode pad 51. Can be prevented. In addition, the upper insulating layer 47 covers the roughened surface R.

In this case, the upper insulating layer 47 may have an uneven surface formed along the roughened surface R. The uneven surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated at the upper surface of the upper insulating layer 47 may be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover side surfaces of the semiconductor stack 30 to protect the semiconductor stack 30 from an external environment. In addition, the upper insulating layer 47 may have an opening that exposes the semiconductor stack 30, and the electrode extension 51a may be in the opening to contact the semiconductor stack 30. .

5 to 11 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention. Here, the cross-sectional views correspond to the cross-sectional views taken along the cut line A-A of FIG. 1.

Referring to FIG. 5, the semiconductor stacked structure 30 including the n-type compound semiconductor layer 25, the active layer 27, and the p-type compound semiconductor layer 29 may be formed on the growth substrate 21. have. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be another hetero substrate, for example, a silicon substrate. The n-type and p-type compound semiconductor layers 25 and 29 may be formed in a single layer or multiple layers, respectively. In addition, the active layer 27 may be formed in a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N-based compound semiconductor, and may be grown on the growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). Can be.

Meanwhile, before forming the compound semiconductor layers, a buffer layer (not shown) may be formed. The buffer layer is adopted to mitigate lattice mismatch between the sacrificial substrate 21 and the compound semiconductor layers, and may be a gallium nitride-based material layer such as gallium nitride or aluminum nitride.

In addition, before the compound semiconductor layers are formed, a compound semiconductor layer, for example, a u-GaN layer (not shown) may be formed on the buffer layer (not shown) or the growth substrate 21 without doping impurities. .

Referring to FIG. 6, a reflective metal layer 31 may be formed on the semiconductor stacked structure 30. The reflective metal layer 31 has a groove exposing the semiconductor stacked structure 30. For example, the reflective metal layer 31 may be formed of a plurality of plates, and grooves may be formed between the plurality of plates (see FIG. 1).

Subsequently, an intermediate insulating layer 33 may be formed to cover the reflective metal layer 31. The intermediate insulating layer 33 fills the groove in the reflective metal layer and covers the side and the edge of the reflective metal layer. In addition, the intermediate insulating layer 33 has openings that expose the reflective metal layer 31.

The intermediate insulating layer 33 may be formed of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices.

The barrier metal layer 35 may be formed on the intermediate insulating layer 33. The barrier metal layer 35 may contact the reflective metal layer 31 by filling an opening formed in the intermediate insulating layer 33.

Referring to FIG. 7, the support substrate 60 may be attached onto the barrier metal layer 35.

The support substrate 60 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through a bonding metal 43.

The support substrate 60 includes a first metal layer 64 positioned in the center of the support substrate 60 and second metal layers 62 and 66 symmetrically disposed above and below the first metal layer 64. . The first metal layer 64 may include, for example, tungsten (W) or molybdenum (Mo).

The second metal layers 62 and 66 may have a higher thermal expansion coefficient than the first metal layer 64 and may be, for example, copper (Cu). Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66. In addition, a bonding layer 61 is formed between the bonding metal 43 and the second metal layer 62. These bonding layers 61, 63, 65 may comprise Ni, Ti, Cr, or Pt. In addition, a lower bonding metal 68 may be formed on the second metal layer 66 through the bonding layer 67. The lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.

The support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 formed symmetrically on the top and bottom surfaces of the first metal layer 64. For example, tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and strength compared to, for example, copper (Cu) constituting the second metal layers 62 and 66.

The thickness of the first metal layer 64 is thicker than the thickness of the second metal layers 62 and 66. In order for the support substrate 60 to have a coefficient of thermal expansion similar to that of the growth substrate and the semiconductor stack 30, the thickness of the first metal layer 64 and the thickness of the second metal layers 62 and 66 are appropriate. Can be adjusted.

The thermal expansion coefficient between the growth substrate 21, the semiconductor laminate 30, and the support substrate 60 in the subsequent heat treatment or subsequent processes in accordance with the bonding of the support substrate 60 by the structure of the support substrate 60. It is possible to effectively alleviate the stress between processes due to the difference can suppress the damage and warpage of the compound semiconductor layer.

In order to bond the support substrate 60, a high temperature atmosphere is required, and pressure may be applied to facilitate the bonding. The pressure may be a process of applying pressure only during the bonding process and removing the pressure after the bonding through the movement of the plate applying pressure to the upper portion of the high temperature chamber.

Alternatively, the process of applying pressure acts in the form of a holder for fixing the support substrate 60 and the growth substrate 21 on both sides, and can be separated from the chamber in a high temperature atmosphere, thereby maintaining pressure even at room temperature after bonding. Form of process.

 A process of removing the growth substrate 21 after the bonding of the support substrate 60 may be a polishing process or a laser lift-off process, and a holder on which the growth substrate 21 is placed in order to alleviate warpage due to a difference in thermal expansion coefficient. Heating may be added to the degree that the warpage can be alleviated, and in the laser lift-off process, the support substrate 60 and the semiconductor laminate structure by the gas and the impact generated in the process of separating the growth substrate 21 are separated. In order to reduce breakage, the process may be performed in a state in which a holder for fixing the growth substrate 21 and the support substrate 60 is mounted.

Meanwhile, the support substrate 60 may be formed on the barrier metal layer 35 using, for example, a plating technique.

After the support substrate 60 is formed, the growth substrate 21 is removed to expose the n-type compound semiconductor layer 25 surface of the semiconductor laminate 30. The growth substrate 21 may be removed by separating the growth substrate 21 by irradiating a laser toward the growth substrate 21 through a laser lift-off (LLO) process. In this case, the laser is selected to have an energy smaller than the energy band gap of the growth substrate 21 and to have an energy larger than the energy band gap of the buffer layer.

Referring to FIG. 8, after the growth substrate 21 is removed, a compound semiconductor layer, for example, a u-GaN layer (not shown), which is not doped with impurities is formed on the n-type semiconductor layer 25. If provided, the process of removing the u-GaN layer can be carried out.

In this case, the process of removing the u-GaN layer may be made of an ICP etching apparatus, and as an etching gas, any etching gas capable of etching the u-GaN layer may be used, but HCl gas or BCl ₃ gas may be used. It is available.

In addition, a cleaning process may be performed to remove inorganic or organic impurities on the exposed n-type compound semiconductor layer 25.

Subsequently, a mask pattern 45 may be formed on the n-type compound semiconductor layer 25. The mask pattern 45 covers the region of the n-type compound semiconductor layer 25 corresponding to the groove of the reflective metal layer 31 and exposes other regions. In particular, the mask pattern 45 covers an area where the n-electrode pad 51 and the electrode extension part 51a will be formed in the future. The mask pattern 45 may be formed of a polymer such as a photoresist.

Subsequently, the surface R of the n-type compound semiconductor layer 25 is subjected to anisotropic etching, that is, PEC etching, using the mask pattern 45 as an etching mask. ). Thereafter, the mask pattern 45 may be removed. After removing the mask pattern 45, an organic material removing process of removing an organic material with an organic solvent may be performed to remove an organic material including a residue of the mask pattern 45. The surface of the n-type compound semiconductor layer 25 on which the mask 45 is positioned maintains a flat surface.

Meanwhile, a chip isolation region is formed by patterning the semiconductor stacked structure 30, and the intermediate insulating layer 33 is exposed. The chip segment may be formed before or after forming the roughened surface R. FIG.

Referring to FIG. 9, an upper insulating layer 47 may be formed on the n-type compound semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. FIG. The upper insulating layer 51 covers the flat surface on which the n-electrode pad 51 is to be formed.

The upper insulating layer 47 may also cover side surfaces of the semiconductor stacked structure 30 exposed to the chip division region. However, the upper insulating layer 47 has an opening 47a exposing a flat surface of the region where the electrode extension 51a is to be formed.

Referring to FIG. 10, the n-electrode pad 51 is formed on the upper insulating layer 47 and immediately before the electrode extension 51a is formed in the opening 47a. The surface of the n-type compound semiconductor layer 25 exposed through the opening 47a may be subjected to plasma treatment using an inert gas to form the plasma treatment region 25a.

In this case, the plasma processing region 25a may be formed using the upper insulating layer 47 as a mask, or may be formed after forming a separate mask pattern.

The plasma treatment can be performed using an RIE apparatus. That is, the upper insulating layer 47 is formed on the entire surface of the n-type compound semiconductor layer 25 on which the roughened surface R is formed, and then the electrode extension part 51a is formed using a mask pattern or the like. Since the RIE apparatus can be used to form the opening 47a for opening the formed position, the step of forming the opening 47a may be followed by the plasma treatment step. The plasma processing region 25a may be formed using any inert gas. However, in the exemplary embodiment of the present invention, the plasma processing region 25a may be formed using an RIE device in which the RF power is applied at 40 W using Ar gas.

Referring to FIG. 11, an n-electrode pad 51 is formed on the upper insulating layer 47, and an electrode extension 51a is formed in the opening 47a. In this case, the electrode extension portion 51a extends from the n-electrode pad 51 and is in electrical contact with the plasma processing region 25a of the semiconductor stack 30, in particular, the n-type compound semiconductor layer 25. To form.

Thereafter, the light emitting diode can be completed by dividing into individual chips along the chip isolation region (see FIG. 2).

Referring to FIG. 12, in the method of manufacturing a light emitting diode according to an embodiment of the present invention, after forming the upper insulating layer 47 having an opening 47a, the electrode extension part 51a is formed by performing a plasma treatment. Although the plasma processing region 25a is formed under the (), the present invention is not limited thereto.

That is, in the plasma treatment process of the surface of the n-type compound semiconductor layer 25 using the inert gas, the n-electrode pad 51 and the electrode extension part 51a are exposed after the n-type compound semiconductor layer 25 is exposed. It may be performed at any point in time before formation.

In this case, "Reference" illustrated in FIG. 12 is a light emitting diode manufactured without the plasma treatment in the light emitting diode manufacturing process described with reference to FIGS. 5 to 11 and measured Vf (forward voltage). Example 1 " removes an impurity-doped compound semiconductor layer, for example, a u-GaN layer (not shown) formed on the n-type compound semiconductor layer 25, and removes the plasma before PEC etching. And Vf was measured. In addition, "Example 2" forms the roughened surface R on the surface of the n-type compound semiconductor layer 25, that is, PEC etching, plasma treatment before forming the upper insulating layer 47, Vf is measured. In addition, in Example 3, the upper insulating layer 47 is formed on the n-type compound semiconductor layer 25, and immediately before the n-electrode pad 51 and the electrode extension part 51a are formed. Plasma treatment is performed and Vf is measured.

Therefore, after the n-type compound semiconductor layer 25 is exposed, a plasma treatment is performed using an inert gas until just before the n-electrode pad 51 and the electrode extension portion 51a are formed. 12, the plasma treatment using the inert gas immediately before forming the n-electrode pad 51 and the electrode extension 51a has the highest reduction effect of Vf. see. This may be because the cation implantation effect disappears by the plasma treatment as other processes are performed after the plasma treatment.

The present invention has been described above with reference to the above embodiments, but the present invention is not limited thereto. Those skilled in the art will appreciate that modifications and variations can be made without departing from the spirit and scope of the present invention and that such modifications and variations also fall within the present invention.

25: n-type compound semiconductor layer 25a: plasma treatment region
27 active layer 29 p-type compound semiconductor layer
30 semiconductor laminate structure 31 reflective metal layer
33: interlayer insulation layer 35: barrier metal layer
43: reinforcing metal 47: upper insulating layer
51 n-electrode pad 51a: electrode extension
60: support substrate

Claims (18)

Conductive support substrate;
A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
An n-electrode pad disposed on the semiconductor laminate structure;
An electrode extension extending from the n-electrode pad; And
An upper insulating layer interposed between the n-electrode pad and the semiconductor laminate structure,
At least the n-type compound semiconductor layer in contact with the electrode extension is provided with a plasma treatment region plasma treated with an inert gas.
The light emitting diode of claim 1, further comprising a bonding metal interposed between the support substrate and the semiconductor laminate.
The method of claim 2, wherein the support substrate
A first metal layer comprising at least one of tungsten (W) or molybdenum (Mo); And
It has a higher coefficient of thermal expansion than the first metal layer, and includes a second metal layer disposed in a symmetrical structure on the upper and lower surfaces of the first metal layer,
A light emitting diode, characterized in that a junction layer is formed between the first metal layer and the second metal layer.
The light emitting diode of claim 3, wherein the second metal layer comprises copper (Cu).
The light emitting diode of claim 3, wherein the bonding layer comprises at least one of Ni, Ti, Cr, and Pt.
The light emitting diode of claim 3, further comprising a lower bonding metal formed on a lower surface of the second metal layer symmetrically to the bonding metal interposed between the support substrate and the semiconductor laminate.
The semiconductor device of claim 2, further comprising: a reflective metal layer disposed between the support substrate and the semiconductor laminate structure and having ohmic contact with the semiconductor laminate structure, the groove having a semiconductor exposed structure;
An intermediate insulating layer disposed between the reflective metal layer and the support substrate and covering the groove and covering the reflective metal layer, the intermediate insulating layer having openings exposing the reflective metal layer; And
And a barrier metal layer disposed between the support substrate and the intermediate insulating layer and covering the reflective metal layer exposed to openings of the intermediate insulating layer.
The light emitting diode of claim 7, wherein the n-electrode pad and the electrode extension part are positioned above the groove area.
The method of claim 7, wherein the reflective metal layer is made of a plurality of plates, the intermediate insulating layer covers the sides and edges of the plurality of plates, the plurality of plates by the openings of the intermediate insulating layer LEDs each of which is exposed.
The method according to claim 9, wherein the light emitting diode is provided with a plurality of n-electrode pads, and includes a plurality of electrode extensions each extending from the plurality of n-electrode pads,
And the plurality of n-electrode pads and the plurality of electrode extensions are positioned over an area between the plurality of plates.
The method of claim 7, wherein the semiconductor laminate has a roughened surface,
The upper insulating layer covers the roughened surface,
The upper insulating layer is a light emitting diode to form an uneven surface along the rough surface.
The light emitting diode of claim 11, wherein the semiconductor stack structure has a flat surface, and the n-electrode pad and the electrode extension are located on the flat surface.
The light emitting diode of claim 12, wherein the electrode extension contacts a flat surface of the semiconductor laminate.
The light emitting diode of claim 11, wherein the roughened surface is positioned below the electrode extension.
forming a semiconductor laminate structure including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer, wherein the semiconductor laminate is formed such that the n-type compound semiconductor layer is exposed;
Forming an upper insulating layer having an opening exposing a portion of the n-type compound semiconductor layer; And
An n-electrode pad and an electrode extension extending from the n-electrode pad are formed on the n-type compound semiconductor layer having the upper insulating layer, wherein the n-electrode pad is formed on the upper insulating layer, and the electrode extends. And forming the portion to contact the n-type compound semiconductor layer through the opening,
And plasma treating a surface of the n-type compound semiconductor layer at least in contact with the electrode extension with an inert gas to form a plasma treatment region in the n-type compound semiconductor layer.
The method of claim 15, wherein the forming of the semiconductor laminate structure including the p-type compound semiconductor layer, the active layer and the n-type compound semiconductor layer, wherein the forming to expose the n-type compound semiconductor layer
Forming a semiconductor laminated structure including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer on the growth substrate;
Attaching a conductive support substrate on the semiconductor laminate structure via a bonding metal; And
Removing the growth substrate to expose the semiconductor laminate structure, but exposing the n-type compound semiconductor layer.
The method of claim 16, wherein prior to attaching the support substrate on the semiconductor laminate,
Forming a reflective metal layer having a groove exposing the semiconductor stacked structure on the semiconductor stacked structure;
Forming an intermediate insulating layer covering side and edge of the reflective metal layer, the intermediate insulating layer having an opening exposing the reflective metal layer; And
And forming a barrier metal layer connecting to the reflective metal layer through the opening of the intermediate insulating layer.
The method of claim 16, wherein after removing the growth substrate to expose the semiconductor laminate structure,
Forming a mask pattern on the exposed semiconductor laminate structure; And
Anisotropically etching the surface of the semiconductor laminate structure using the mask pattern as an etch mask to form a roughened surface together with a flat surface;
Forming an upper insulating layer having an opening to expose a portion of the n-type compound semiconductor layer may form an upper insulating layer covering a surface of the semiconductor laminate structure, wherein the opening may expose a portion of the flat surface. Forming the upper insulating layer to form a light emitting diode.

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