KR20120033294A - High efficiency light emitting diode and method of fabricating the same - Google Patents

Abstract

PURPOSE: A high efficiency light emitting diode and a manufacturing method thereof are provided to effectively alleviate stress between processes due to a thermal expansion coefficient mismatch between a support substrate and a semiconductor stacked structure, thereby suppressing damage and bending of a compound semiconductor layer. CONSTITUTION: A support substrate(60) is comprised by including a first metal layer(64) and second metal layers(62,66). A junction layer(61) is formed between a bonding metal(43) and the second metal layer. A lower bonding metal(68) is formed on the lower surface of the second metal layer. A semiconductor stacked structure(30) comprises a p-type compound semiconductor layer(29), an active layer(27), and an n-type compound semiconductor layer(25). P-type electrodes(31,35) are located between the p-type compound semiconductor layer and the support substrate.

Description

High-Efficiency Light-Emitting Diodes and Methods of Manufacturing Them {High EFFICIENCY LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a gallium nitride-based high efficiency light emitting diode and a method of manufacturing the same by removing the growth substrate by applying a substrate separation process.

In general, nitrides of group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition type energy band structure. It is attracting much attention as a substance. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. Is grown through the process. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used. However, sapphire is an electrically insulator, thus limiting the light emitting diode structure. Accordingly, recently, epitaxial layers, such as nitride semiconductor layers, are grown on dissimilar substrates such as sapphire, bonding supporting substrates to the epitaxial layers, and then separating the dissimilar substrates using a laser lift-off technique. A technique for manufacturing a high efficiency light emitting diode having a structure has been developed.

In general, a vertical light emitting diode has a current dissipation performance superior to that of a conventional horizontal light emitting diode due to a structure having a lower p-side and a heat dissipation by adopting a support substrate having a higher thermal conductivity than sapphire. The performance is excellent. Furthermore, by anisotropically etching the N-plane by PEC etching or the like to form a roughened surface, upward light extraction efficiency can be greatly improved.

However, since the total thickness (about 4 μm) of the epi layer is very thin, for example, compared to the light emitting area of 350 μm × 350 μm or 1 mm 2, there are many difficulties in current dispersion. In order to solve this problem, an electrode extension portion extending from the n-type electrode pad is adopted to facilitate current dispersion in the n-type layer, or an n-type is disposed by placing an insulating material at a p-type electrode position corresponding to the n-type electrode pad. The technique which prevents a current from flowing directly from an electrode pad to a p-type electrode is adopted. However, there is a limit to preventing current flow from concentrating below the n-type electrode pad, and furthermore, there is a limit to evenly distributing the current throughout the wide light emitting region.

1 to 5 show a method of manufacturing a conventional vertical light emitting device.

1 to 5, a conventional method of manufacturing a vertical light emitting device includes a compound semiconductor layer including a buffer layer, an undoped semiconductor layer, a first semiconductor layer, an active layer, and a second semiconductor layer on a growth substrate 11. 12) (FIG. 1), and the bonding layer 13 is formed thereon (FIG. 2). Subsequently, after bonding the support substrate 14 on the bonding layer 13 (FIG. 3), the buffer layer is decomposed by irradiating a laser onto the growth substrate 11 by a laser lift off (LLO) technique to decompose the growth substrate 11. Is separated (FIG. 4), and the electrode 15 is formed (FIG. 5).

However, when manufacturing a vertical light emitting device according to the conventional method, there is no layer for buffering shock waves generated between the substrate 11 and the compound semiconductor layer 12 during the laser lift off (LLO) process. Many physical damages such as cracks are generated.

Sapphire, silicon carbide, and the like are used as the growth substrate 11 for the compound semiconductor layer 12 that emits short wavelengths of green and blue which are generally used. However, the growth substrate 11 has a phenomenon such as warpage due to a difference in thermal expansion coefficient when the growth substrate 11 has a difference in thermal expansion coefficient from the upper compound semiconductor layers 12 and returns to room temperature after growth at high temperature.

This difference is generally not shown because the thickness of the growth substrate 11 is tens of times larger than that of the upper compound semiconductor layers 12, but the stress caused by the growth substrate 11 remains in the upper compound semiconductor layer 12.

The substrate used as the support substrate 14 uses a substrate having better electrical conductivity and thermal conductivity than the growth substrate 11, but the thermal expansion coefficient of the substrate is the thermal expansion coefficient of the growth substrate 11 and the compound semiconductor layer 12. Generally greater than the difference.

The bonding between the support substrate 14 and the compound semiconductor layers 12 grown on the growth substrate 11 proceeds at a temperature relatively lower than the growth temperature of the semiconductor layer (200 ° C. to 400 ° C.), but the coefficient of thermal expansion with the material. Due to the large difference, stress or warpage may be severe.

Bonding of the support substrate 14 is a process that proceeds at high temperature and high pressure, and heat is applied while the growth substrate 11 and the support substrate 14 are pressed at a high pressure. At this time, the growth substrate 11 and the compound semiconductor layer 12 do not form a flat state due to the difference in thermal expansion coefficient and lattice constant during growth, and part of the substrate has a concave or convex state. Due to this shape, when the compound semiconductor layer 12 and the support substrate 14 are bonded to each other, fine bubbles are formed inside and remain.

On the other hand, even when a substrate having a similar coefficient of thermal expansion to the compound semiconductor layer 12 is used as the support substrate 14, its materials and processes have many limitations.

The problem to be solved by the present invention is to provide a high-efficiency light emitting device and a method of manufacturing the light emitting efficiency is improved by solving the problems that may occur when bonding the support substrate and the compound semiconductor layer when manufacturing a vertical light emitting device.

Another object of the present invention is to provide a high efficiency light emitting device having improved light extraction efficiency and a method of manufacturing the same.

The problem to be solved by the present invention is to provide a high-efficiency light emitting diode with improved current dispersion performance.

According to one aspect of the invention, the conductive support substrate; A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; And a bonding metal interposed between the support substrate and the semiconductor laminate structure. The support substrate may include a first metal layer including at least one of tungsten (W) or molybdenum (Mo); A thermal expansion coefficient is higher than that of the first metal layer, and includes a second metal layer disposed symmetrically on the upper and lower surfaces of the first metal layer; There is provided a light emitting diode in which a bonding layer is formed between the first metal layer and the second metal layer.

The second metal layer may include copper (Cu).

The bonding layer may include at least one of Ni, Ti, Cr, and Pt.

The light emitting diode may further include a lower bonding metal formed on a lower surface of the second metal layer symmetrically to the bonding metal interposed between the support substrate and the semiconductor laminate.

The light emitting diode may include: a reflective metal layer positioned between the support substrate and the semiconductor stacked structure and having ohmic contact with the semiconductor stacked structure and exposing the semiconductor stacked structure; An intermediate insulating layer disposed between the reflective metal layer and the support substrate and covering the groove and covering the reflective metal layer, the intermediate insulating layer having openings exposing the reflective metal layer; A barrier metal layer disposed between the support substrate and the intermediate insulating layer and covering the reflective metal layer exposed to openings of the intermediate insulating layer; A first electrode pad positioned on the semiconductor stacked structure; An electrode extension extending from the first electrode pad; And an upper insulating layer interposed between the first electrode pad and the semiconductor stacked structure.

The first electrode pad and the electrode extension part may be positioned above the groove area.

The reflective metal layer may include a plurality of plates, the intermediate insulating layer may cover side and edges of the plurality of plates, and the plurality of plates may be exposed by openings of the intermediate insulating layer, respectively. .

The light emitting diode may include a plurality of first electrode pads; And a plurality of electrode extensions extending from the plurality of first electrode pads, respectively, wherein the plurality of first electrode pads and the electrode extensions may be positioned above an area between the plurality of plates.

The semiconductor laminate structure may have a roughened surface, and the upper insulating layer may cover the roughened surface, and the upper insulating layer may form an uneven surface along the roughened surface.

The semiconductor laminate structure may have a flat surface, and the first electrode pad and the electrode extension may be located on the flat surface.

The electrode extension may contact a flat surface of the semiconductor laminate.

The roughened surface may be located below the electrode extension.

According to another aspect of the present invention, a semiconductor laminate structure including a p-type compound semiconductor layer, an active layer and an n-type compound semiconductor layer is formed on a growth substrate, and a conductive support substrate is attached to the laminate structure via a bonding metal. The semiconductor substrate may be exposed by removing the growth substrate, wherein the support substrate may include a first metal layer including at least one of tungsten (W) or molybdenum (Mo); A thermal expansion coefficient higher than that of the first metal layer, the second metal layer being symmetrically disposed on upper and lower surfaces of the first metal layer; Provided is a light emitting diode manufacturing method in which a bonding layer is formed between the first metal layer and the second metal layer.

The second metal layer may include copper (Cu).

The bonding layer may include at least one of Ni, Ti, Cr, and Pt.

The light emitting diode may further include a lower bonding metal formed on a lower surface of the second metal layer symmetrically to a bonding metal interposed between the support substrate and the semiconductor laminate.

The light emitting diode manufacturing method may further include forming a reflective metal layer on the semiconductor laminate, prior to attaching the support substrate on the semiconductor laminate, wherein the reflective metal layer has a groove exposing the semiconductor laminate. An intermediate insulating layer covering the metal layer, wherein the intermediate insulating layer covers side and edges of the reflective metal layer and has an opening that exposes the reflective metal layer and is connected to the reflective metal layer through the opening of the intermediate insulating layer Forming a barrier metal layer, attaching a support substrate to the barrier metal layer, removing the growth substrate to expose the semiconductor laminate, and then forming a mask pattern on the exposed semiconductor laminate. Surface of the semiconductor laminate structure using Anisotropic etching forms a rough surface with the flat surface, and forms an upper insulating layer covering the surface of the semiconductor laminate structure, wherein the upper insulating layer has an opening that exposes a portion of the flat surface, and the upper insulating layer. A first electrode pad may be formed on the layer, and an electrode extension part extending from the first electrode pad may be formed, and the electrode extension part may be formed in an opening of the upper insulating layer.

The first electrode pad and the electrode extension part may be formed on the groove area of the reflective metal layer.

The reflective metal layer may be formed of a plurality of plates, the intermediate insulating layer may cover side and edges of the plurality of plates, and the plurality of plates may be exposed by openings of the intermediate insulating layer, respectively. .

A plurality of first electrode pads and a plurality of electrode extensions may be formed on an area between the plurality of plates, respectively.

The upper insulating layer may be formed along the roughened surface to have an uneven surface.

According to the present invention, the structure of the support substrate can effectively alleviate the stress between processes due to the difference in the coefficient of thermal expansion between the growth substrate, the semiconductor laminate structure, and the support substrate during the heat treatment or the subsequent process according to the bonding of the support substrate. It is possible to improve the luminous efficiency of the light emitting device by suppressing damage and warpage of the compound semiconductor layer.

According to the present invention, an upper insulating layer is interposed between the first electrode pad and the semiconductor laminate to provide a light emitting diode having improved current dispersion performance. Furthermore, the light extraction efficiency of the light emitting diode is improved by forming the upper insulating layer to have an uneven surface along the roughened surface of the semiconductor laminate structure. In addition, since the intermediate insulating layer covers the side and edge of the reflective metal layer, it is possible to prevent the reflective metal layer from deteriorating due to moisture or the like. Furthermore, since the electrode extension is located above the groove region of the reflective metal layer, it is possible to prevent the current from flowing under the electrode extension.

1 to 5 show a method of manufacturing a conventional vertical light emitting device.
6 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention.
7 is a cross-sectional view taken along the cutting line AA of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
8 is a cross-sectional view taken along the line BB of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
9 is a cross-sectional view taken along the cut line CC of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
10 to 14 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, each of which is a cross-sectional view corresponding to the cutting line AA of FIG. 6.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the same reference numerals denote the same components, and the width, length, thickness, etc. of the components may be exaggerated for convenience.

6 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention, and FIGS. 7 to 9 are cross-sectional views taken along the cutting lines A-A, B-B, and C-C of FIG. 6, respectively. In FIG. 6, the reflective metal layer 31 and the intermediate insulating layer 33 positioned under the semiconductor stacked structure 30 are indicated by dotted lines.

6 to 9, the light emitting diode includes a support substrate 60, a semiconductor stacked structure 30, a reflective metal layer 31, an intermediate insulating layer 33, a barrier metal layer 35, and an upper insulating layer 47. ), an n-electrode pad 51 and an electrode extension 51a. In addition, the light emitting diode may include a bonding metal 43.

The support substrate 60 is separated from the growth substrate for growing the compound semiconductor layers, and is a secondary substrate attached to the compound semiconductor layers that have already been grown. The support substrate 60 may be a conductive substrate, for example, a metal substrate.

The support substrate 60 includes a first metal layer 64 positioned in the center of the support substrate 60, and second metal layers 62 and 66 symmetrically disposed above and below the first metal layer 64. . The first metal layer 64 may include, for example, at least one of tungsten (W) or molybdenum (Mo). The second metal layers 62 and 66 may have a higher thermal expansion coefficient than the first metal layer 64 and may include, for example, copper (Cu). Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66. In addition, the bonding layer 61 is also formed between the bonding metal 43 and the second metal layer 62. These bonding layers 61, 63, 65 may comprise at least one of Ni, Ti, Cr, and Pt. In addition, a lower bonding metal 68 may be formed on the lower surface of the second metal layer 66 formed on the lower surface of the first metal layer 64 through the bonding layer 67. The lower bonding metal 68 is a structure symmetrical to the bonding metal 43 interposed between the supporting substrate 60 and the semiconductor stack 30, and may be made of the same material as the bonding metal 43, for example, Au or Au-Sn (80 / 20wt%). The lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.

The support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 formed symmetrically on the upper and lower surfaces of the first metal layer 64. For example, tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and strong strength as compared to, for example, copper (Cu) constituting the second metal layers 62 and 66. The thickness of the first metal layer 64 is formed thicker than the thickness of the second metal layers 62 and 66. Accordingly, forming the second metal layers 62 and 66 on the upper and lower surfaces of the first metal layer 64 may be performed in a step rather than having the opposite structure (the structure in which the first metal layer is formed on the upper and lower surfaces of the second metal layer). Even more preferred. In addition, in order for the support substrate 60 to have a coefficient of thermal expansion similar to that of the growth substrate and the semiconductor laminate 30, the thickness of the first metal layer 64 and the thickness of the second metal layers 62 and 66 are appropriately adjusted. Can be.

The support substrate 60 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43. Alternatively, the support substrate 60 may be formed by plating on the barrier metal layer 35. As the plating method used when forming the support substrate 60, an electrolytic plating method for depositing a metal using a rectifier and an electroless plating method for depositing a metal using a reducing agent may be used. , Electron beam deposition, sputtering, chemical vapor deposition, etc. may be used.

The semiconductor stacked structure 30 is disposed on the support substrate 60 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25. Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 60 side than the n-type compound semiconductor layer 25 similarly to the general vertical light emitting diode. The semiconductor stacked structure 30 may be located on a portion of the support substrate 60. That is, the support substrate 60 has a relatively large area compared to the semiconductor laminate structure 30, and the semiconductor laminate structure 30 is located in an area surrounded by the edge of the support substrate 60.

The n-type compound semiconductor layer 25, the active layer 27, and the p-type compound semiconductor layer 29 may be formed of a III-N series compound semiconductor, such as (Al, Ga, In) N semiconductor. The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may be a single layer or multiple layers, respectively. For example, the n-type compound semiconductor layer 25 and / or the p-type compound semiconductor layer 29 may include a contact layer and a cladding layer, and may also include a superlattice layer. In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. Since the n-type compound semiconductor layer 25 having a relatively small resistance is located on the opposite side of the support substrate 60, it is easy to form a roughened surface R on the upper surface of the n-type compound semiconductor layer 25, and is rough. The deep surface R improves the extraction efficiency of light generated in the active layer 27.

The p-electrodes 31 and 35 are positioned between the p-type compound semiconductor layer 29 and the support substrate 60 and may include a reflective metal layer 31 and a barrier metal layer 35. The reflective metal layer 31 makes ohmic contact with the p-type compound semiconductor layer 29 between the semiconductor laminate structure 30 and the support substrate 60. The reflective metal layer 31 may include a reflective layer, for example Ag. The reflective metal layer 31 is located below the semiconductor stacked structure 30. As shown in FIG. 6, the reflective metal layer 31 may be formed of a plurality of plates, and grooves are formed between the plurality of plates. The semiconductor stacked structure 30 is exposed through the groove.

An intermediate insulating layer 33 covers the reflective metal layer 31 between the reflective metal layer 31 and the support substrate 60. The intermediate insulating layer 33 covers the side and edges of the reflective metal layer 31, for example, the plurality of plates, and has openings that expose the reflective metal layer 31. The intermediate insulating layer 33 may be formed of a single layer or multiple layers of a silicon oxide film or a silicon nitride film, and insulating layers having different refractive indices, for example, SiO ₂ / TiO _2. Or a distributed Bragg reflector obtained by repeatedly stacking SiO ₂ / Nb ₂ O ₅ . The side surface of the reflective metal layer 31 may be prevented from being exposed to the outside by the intermediate insulating layer 33. The intermediate insulating layer 33 may also be located below the side surface of the semiconductor laminate 30, thus preventing leakage current through the side of the semiconductor laminate 30.

The barrier metal layer 35 covers the intermediate insulating layer 33 under the intermediate insulating layer 33 and is connected to the reflective metal layer 31 through the opening of the intermediate insulating layer 33. The barrier metal layer 35 protects the reflective metal layer 31 by preventing diffusion of a metal material, such as Ag, of the reflective metal layer 31. The barrier metal layer 35 may include, for example, a Ni layer. The barrier metal layer 35 may be located on the front surface of the support substrate 60.

Meanwhile, the support substrate 60 may be bonded to the barrier metal layer 35 through the bonding metal 43. The bonding metal 43 may be formed using eutectic bonding, for example, with Au or Au—Sn (80/20 wt%).

On the other hand, the upper surface of the semiconductor laminated structure 30, that is, the surface of the n-type compound semiconductor layer 25 may have a roughened surface (R) and a flat surface. As shown in Figs. 7 to 9, the n-electrode pad 51 and the electrode extension 51a are located on a flat surface. As shown in the drawing, the n-electrode pad 51 and the electrode extension part 51a are defined on a flat surface and may have a narrow width compared to the width of the flat surface. Therefore, peeling of an electrode pad or an electrode extension part by generation | occurrence | production of an undercut etc. in the semiconductor laminated structure 30 can be prevented, and reliability can be improved. On the other hand, the rough surface (R) may be located below the flat surface. That is, the roughened surface R is located below the electrode pad 51 and the electrode extension 51a.

On the other hand, the n-electrode pad 51 is located on the semiconductor stacked structure 30, and the electrode extension 51a extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor stacked structure 30, and electrode extensions 51a may extend from the n-electrode pads 51, respectively. The electrode extensions 51a may be electrically connected to the semiconductor stacked structure 30 and may directly contact the n-type compound semiconductor layer 25.

The n-electrode pad 51 may also be located above the groove region of the reflective metal layer 31. That is, under the n-electrode pad 51, there is no reflective metal layer 31 in ohmic contact with the p-type compound semiconductor layer 29. Instead, the intermediate insulating layer 33 is positioned. In addition, the electrode extension part 51a is also positioned above the groove area of the reflective metal layer 31. As illustrated in FIG. 6, an electrode extension part 51a may be positioned on an area between the plates in the reflective metal layer 31 including a plurality of plates. Preferably, the width of the groove region of the reflective metal layer 31, for example, the region between the plurality of plates is wider than the width of the electrode extension 51a. Accordingly, it is possible to prevent the current from flowing intensively directly below the electrode extension part 51a.

Meanwhile, an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor stacked structure 30. The upper insulating layer 47 prevents current from flowing directly from the n-electrode pad 51 to the semiconductor stacked structure 30, and in particular, prevents current from concentrating directly under the n-electrode pad 51. Can be. In addition, the upper insulating layer 47 covers the roughened surface R. In this case, the upper insulating layer 47 may have an uneven surface formed along the roughened surface R. The uneven surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated at the upper surface of the upper insulating layer 47 may be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover side surfaces of the semiconductor stack 30 to protect the semiconductor stack 30 from an external environment. In addition, the upper insulating layer 47 may have an opening exposing the semiconductor stack 30, and the electrode extension 51a may be located in the opening to contact the semiconductor stack 30.

10 to 14 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention. Here, the cross-sectional views correspond to the cross-sectional views taken along the cut line A-A of FIG. 6.

Referring to FIG. 10, a semiconductor stacked structure 30 including an n-type semiconductor layer 25, an active layer 27, and a p-type semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be another hetero substrate, for example, a silicon substrate. The n-type and p-type semiconductor layers 25 and 29 may be formed in a single layer or multiple layers, respectively. In addition, the active layer 27 may be formed in a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N-based compound semiconductor, and may be grown on the growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). Can be.

Meanwhile, before forming the compound semiconductor layers, a buffer layer (not shown) may be formed. The buffer layer is adopted to mitigate lattice mismatch between the growth substrate 21 and the compound semiconductor layers, and may be a gallium nitride-based material layer such as gallium nitride or aluminum nitride.

Referring to FIG. 11, a reflective metal layer 31 is formed on the semiconductor stacked structure 30. The reflective metal layer 31 has a groove exposing the semiconductor stacked structure 30. For example, the reflective metal layer 31 may be formed of a plurality of plates, and grooves may be formed between the plurality of plates (see FIG. 6).

Subsequently, an intermediate insulating layer 33 covering the reflective metal layer 31 is formed. The intermediate insulating layer 33 fills the groove in the reflective metal layer and covers the side and edge of the reflective metal layer. In addition, the intermediate insulating layer 33 has openings that expose the reflective metal layer 31. The intermediate insulating layer 33 may be formed of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices.

The barrier metal layer 35 is formed on the intermediate insulating layer 33. The barrier metal layer 35 may be connected to the reflective metal layer 31 by filling an opening formed in the intermediate insulating layer 33.

Referring to FIG. 12, a support substrate 60 is attached to the barrier metal layer 35. The support substrate 60 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43.

The support substrate 60 includes a first metal layer 64 positioned in the center of the support substrate 60, and second metal layers 62 and 66 symmetrically disposed below the first metal layer 64. The first metal layer 64 may include, for example, tungsten (W) or molybdenum (Mo). The second metal layers 62 and 66 may have a higher coefficient of thermal expansion than the first metal layer 64 and may be, for example, copper (Cu). Bonding layers 63 and 65 are formed between the first metal layer 64 and the second metal layers 62 and 66. In addition, the bonding layer 61 is also formed between the bonding metal 43 and the second metal layer 62. These bonding layers 61, 63, 65 may comprise Ni, Ti, Cr, or Pt. In addition, a lower bonding metal 68 may be formed on the second metal layer 66 through the bonding layer 67. The lower bonding metal 68 may be used to attach the support substrate 60 to an electronic circuit or a PCB substrate.

The support substrate 60 has a structure including the first metal layer 64 and the second metal layers 62 and 66 formed symmetrically on the upper and lower surfaces of the first metal layer 64. For example, tungsten (W) or molybdenum (Mo) constituting the first metal layer 64 has a relatively low coefficient of thermal expansion and strong strength as compared to, for example, copper (Cu) constituting the second metal layers 62 and 66. The thickness of the first metal layer 64 is formed thicker than the thickness of the second metal layers 62 and 66. In order for the support substrate 60 to have a coefficient of thermal expansion similar to that of the growth substrate and the semiconductor laminate 30, the thickness of the first metal layer 64 and the thickness of the second metal layers 62 and 66 may be appropriately adjusted. have.

Due to the structure of the support substrate 60, the thermal expansion coefficient difference between the growth substrate 21, the semiconductor laminate structure 30, and the support substrate 60 may be changed when the heat treatment is performed during or after the bonding of the support substrate 60. It is possible to effectively alleviate the stress between processes due to the damage and warpage of the compound semiconductor layer can be suppressed.

In order to bond the support substrate 60, a high temperature atmosphere is required, and pressure may be applied to facilitate the bonding. The pressure may be a process of applying pressure only during the bonding process and removing the pressure after the bonding through the movement of the plate applying pressure to the upper portion of the high temperature chamber.

Alternatively, the process of applying pressure acts in the form of a holder for fixing the support substrate 60 and the growth substrate 21 on both sides, and can be separated from the chamber in a high temperature atmosphere to maintain pressure even at room temperature after bonding. It may be a process of.

 The process of removing the growth substrate 21 after the bonding of the support substrate 60 may be a polishing process or a laser lift-off process, and bent to the holder on which the growth substrate 21 is placed in order to alleviate the warpage caused by the difference in thermal expansion coefficient. This heating may be alleviated. In addition, in the laser lift-off process, the support substrate 60 and the semiconductor laminate may be damaged by the gas and the impact generated during the separation of the growth substrate 21. In order to reduce, the process may be performed in a state in which a holder for fixing the growth substrate 21 and the support substrate 60 is mounted.

On the other hand, the support substrate 60 may be formed on the barrier metal layer 35 using, for example, a plating technique.

After the supporting substrate 60 is formed, the growth substrate 21 is removed to expose the n-type semiconductor layer 25 surface of the semiconductor laminate 30. The growth substrate 21 may be removed by separating the growth substrate 21 by irradiating a laser toward the growth substrate 21 through a laser lift-off (LLO) process. At this time, the laser is selected to have an energy smaller than the energy band gap of the growth substrate 21 and to have an energy larger than the energy band gap of the buffer layer.

Referring to FIG. 13, a mask pattern 45 is formed on the exposed n-type semiconductor layer 25. The mask pattern 45 covers an n-type semiconductor layer 25 region corresponding to the groove of the reflective metal layer 31 and exposes other regions. In particular, the mask pattern 45 covers an area where the n-electrode pad and the electrode extension are to be formed in the future. The mask pattern 45 may be formed of a polymer such as a photoresist.

Subsequently, the surface R of the n-type semiconductor layer 25 is formed by anisotropically etching the surface of the n-type semiconductor layer 25 using the mask as an etching mask. Thereafter, the mask 45 is removed. The surface of the n-type semiconductor layer 25 in which the mask 45 is positioned maintains a flat surface.

Meanwhile, a chip isolation region is formed by patterning the semiconductor stacked structure 30, and the intermediate insulating layer 33 is exposed. The chip segment may be formed before or after forming the roughened surface R. FIG.

Referring to FIG. 14, an upper insulating layer 47 is formed on the n-type semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. FIG. The upper insulating layer 47 covers the flat surface on which the n-electrode pad 51 is to be formed. The upper insulating layer 47 may also cover side surfaces of the semiconductor stacked structure 30 exposed to the chip division region. However, the upper insulating layer 47 has an opening 47a exposing a flat surface of the region where the electrode extension 51a is to be formed.

Subsequently, an n-electrode pad 51 is formed on the upper insulating layer 47, and an electrode extension part is formed in the opening 47a. The electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminate 30.

Then, the light emitting diode is completed by dividing into individual chips along the chip isolation region (see FIG. 7).

Claims (21)

Conductive support substrate;
A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; And
A bonding metal interposed between the support substrate and the semiconductor laminate structure;
The support substrate,
A first metal layer comprising at least one of tungsten (W) or molybdenum (Mo);
A coefficient of thermal expansion higher than that of the first metal layer, the second metal layer being disposed in a symmetrical structure on upper and lower surfaces of the first metal layer;
A bonding layer is formed between the first metal layer and the second metal layer,
The thickness of the first metal layer is a light emitting diode, characterized in that formed thicker than the thickness of the second metal layer.
The method according to claim 1,
The second metal layer is a light emitting diode comprising copper (Cu).
The method according to claim 1,
The bonding layer includes at least one of Ni, Ti, Cr, Pt.
The method according to claim 1,
And a lower bonding metal formed on a lower surface of the second metal layer symmetrically to the bonding metal interposed between the support substrate and the semiconductor stacked structure.
The method according to claim 1,
A reflective metal layer disposed between the support substrate and the semiconductor stack structure and having ohmic contact with the semiconductor stack structure and exposing the semiconductor stack structure;
An intermediate insulating layer disposed between the reflective metal layer and the support substrate and covering the groove and covering the reflective metal layer, the intermediate insulating layer having openings exposing the reflective metal layer;
A barrier metal layer disposed between the support substrate and the intermediate insulating layer and covering the reflective metal layer exposed to openings of the intermediate insulating layer;
A first electrode pad positioned on the semiconductor stacked structure;
An electrode extension extending from the first electrode pad; And
The light emitting diode further comprising an upper insulating layer interposed between the first electrode pad and the semiconductor stacked structure.
The method according to claim 5,
The first electrode pad and the electrode extension part are positioned above the groove area.
The method according to claim 5,
The reflective metal layer is formed of a plurality of plates, the intermediate insulating layer covers side and edges of the plurality of plates, and each of the plurality of plates is exposed by openings of the intermediate insulating layer. .
The method according to claim 7,
A plurality of first electrode pads; And
Comprising a plurality of electrode extensions each extending from the plurality of first electrode pads,
The plurality of first electrode pads and the electrode extensions are positioned over an area between the plurality of plates.
The method according to claim 5,
The semiconductor laminate structure has a roughened surface,
The upper insulating layer covers the roughened surface,
The upper insulating layer is a light emitting diode to form an uneven surface along the rough surface.
The method according to claim 9,
The semiconductor stacked structure has a flat surface, and the first electrode pad and the electrode extension are positioned on the flat surface.
The method according to claim 10,
And the electrode extension portion contacts a flat surface of the semiconductor laminate.
The method according to claim 9,
The roughened surface is a light emitting diode positioned below the electrode extension.
Forming a semiconductor laminate including a p-type compound semiconductor layer, an active layer and an n-type compound semiconductor layer on the growth substrate,
Attaching a conductive support substrate to the laminate structure via a bonding metal;
The growth substrate is removed to expose the semiconductor laminate structure,
The support substrate,
A first metal layer comprising at least one of tungsten (W) or molybdenum (Mo);
A coefficient of thermal expansion higher than that of the first metal layer, the second metal layer being symmetrically disposed on upper and lower surfaces of the first metal layer;
A bonding layer is formed between the first metal layer and the second metal layer,
The thickness of the first metal layer is greater than the thickness of the second metal layer is formed light emitting diode manufacturing method characterized in that.
The method according to claim 13,
The second metal layer is a light emitting diode manufacturing method containing copper (Cu).
The method according to claim 13,
The bonding layer comprises at least one of Ni, Ti, Cr, Pt.
The method according to claim 13,
And a lower bonding metal formed on a lower surface of the second metal layer symmetrically to a bonding metal interposed between the support substrate and the semiconductor stacked structure.
The method according to claim 13,
Prior to attaching the support substrate on the semiconductor laminate structure,
Forming a reflective metal layer on the semiconductor stacked structure, the reflective metal layer having a groove exposing the semiconductor stacked structure,
Forming an intermediate insulating layer covering the reflective metal layer, the intermediate insulating layer covering side and edges of the reflective metal layer and having an opening exposing the reflective metal layer;
Forming a barrier metal layer connecting to the reflective metal layer through the opening of the intermediate insulating layer;
Attaching a support substrate on the barrier metal layer,
After removing the growth substrate to expose the semiconductor laminate,
Forming a mask pattern on the exposed semiconductor laminate structure,
Anisotropically etching the surface of the semiconductor laminate structure using the mask pattern as an etch mask to form a rough surface together with a flat surface,
An upper insulating layer covering a surface of the semiconductor laminate structure, wherein the upper insulating layer has an opening exposing a portion of the flat surface;
Forming a first electrode pad on the upper insulating layer, and forming an electrode extension extending from the first electrode pad, wherein the electrode extension is formed in the opening of the upper insulating layer.
18. The method of claim 17,
The first electrode pad and the electrode extension part are formed on the groove area of the reflective metal layer.
18. The method of claim 17,
The reflective metal layer is formed of a plurality of plates, the intermediate insulating layer covers side and edges of the plurality of plates, and the plurality of plates are exposed through openings of the intermediate insulating layer, respectively. Manufacturing method.
The method of claim 19,
And a plurality of first electrode pads and a plurality of electrode extensions are respectively formed on an area between the plurality of plates.
18. The method of claim 17,
And the upper insulating layer is formed along the roughened surface to have an uneven surface.

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