KR20090098939A - Semiconductor device test system and test handler - Google Patents

Abstract

A system for testing semiconductor device and a test handler extending the test function of head main body into the interface block is provided to prevent the developing that causes the test error by removing the heat generated in the interface block, especially the testing board. An interface block(310) applied to the improved system for testing semiconductor device comprises an interface board(311), a testing board(312) and a head connection board(313). The interface board has a circuit board(311a), a plurality of test sockets(311b) and an interface board connector(311c). The testing board comprises a circuit board(312a), a first testing board connector(312b), an interface board connector(311c) and a second testing board connector(312d). A head connection board(313) comprises a circuit board(313a), a head connection board connector(313b) and a testing board second connector. The head connection board is electrically connected to head main body with a connecting cable(CC).

Description

Semiconductor Device Test System and Test Handler {SEMICONDUCTOR DEVICE TEST SYSTEM AND TEST HANDLER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test system, a test handler, and the like, and more particularly, to a technology in which a testing board for testing a semiconductor device is provided at an interface block of a test head for testing a semiconductor device.

In general, a semiconductor device test system includes a test control device, a test head for testing a semiconductor device under control of the test control device, and supplying a plurality of semiconductor devices to the test head such that the plurality of semiconductor devices are electrically connected to the test head. It consists of a test handler that supports testing of semiconductor devices together and a support device (called 'mani plate' in the industry) that supports the test head to keep the test head stably coupled to the test handler. .

1 and 2 are conceptual plan and side views illustrating a state in which the test handler 100 and the test head 200 are coupled to each other, and with reference thereto, the test handler 100, the test head 200, and the test handler ( 100) and the coupling state of the test head 200 will be described in more detail.

The test handler 100 includes a loading device 110, a test chamber 120, an unloading device 130, and the like, as referenced in the plan view of FIG. 1.

The loading device 110 loads the semiconductor device into the carrier board CB at the loading position LP.

The test chamber 120 accommodates the carrier board CB transferred after the loading is completed by the loading device 110, and then a semiconductor device loaded on the received carrier board CB is electrically connected to the test head 200. Test can be performed while connected.

The unloading device 130 classifies and unloads the semiconductor devices loaded on the carrier board CB transferred from the test chamber 120 to the unloading position UP, according to test grades.

The test handler 100 as described above is already known through the Republic of Korea Patent Registration No. 10-0709114 (name of the invention: the test handler) and so on, a detailed description thereof will be omitted.

In addition, the test head 200, as referred to in Figures 1 and 2, the interface block 210, also known as 'high-fix board' or 'interface board' in the industry and the head body 220, etc. It is configured to include.

The interface block 210 has a plurality of test sockets 211 which are each in electrical contact with a plurality of semiconductor devices supplied from the test handler 100. This interface block 210, when the test handler 100 and the test head 200 is coupled, as shown in Figs. 1 and 2, a part of the interface block 210 into the test chamber 120 of the test handler 100 It is inserted.

The head body 220 gives an electrical signal to the semiconductor device through the test socket 211 of the interface block 210 under the control of a test control device (not shown), and then through the interface block 210 from the semiconductor device. The semiconductor device is tested by reading the coming electrical signal.

For reference, reference numeral C of FIG. 1 is a circulation path of the carrier board CB, and reference numeral SA of FIG. 2 is a support device for supporting the test head 200.

On the other hand, as the demand for semiconductor devices increases, performance is improved to increase the number of semiconductor devices that can be tested at one time, that is, to a test handler capable of supplying a larger number of semiconductor devices to a test head at a time. Improved technology has begun to emerge.

Therefore, when a test handler supplies a larger number of semiconductor devices to a test head at a time, the capacity of the test head needs to be expanded and performance improved so that the test head can test more semiconductor devices per hour.

However, the capacity expansion and performance improvement of the head body is not easy, so the capacity and performance of the head body cannot keep up with the capacity and performance of the test handler, and the development cost for capacity expansion and performance improvement of the head body is high. to be.

Of course, it is possible to increase the capacity of the test head by branching a channel for applying an electrical signal to the semiconductor device, but the overall test time is inevitably increased because performance is not comparable.

In addition, even if the capacity of the test head is expanded and the performance is improved, all of the existing test heads must be replaced with the improved test heads, which not only wastes resources but also requires huge replacement costs.

Therefore, in order to overcome the above problems, in recent years, the electrical signal from the semiconductor device is read out by the replaceable interface block instead of the head body, and the performance of the head block is improved by making the interface block equivalent to the test handler. A technology that can improve the performance of a semiconductor device test system has been proposed.

It is an object of the present invention to provide a newly proposed technique as described above, that is, a technique capable of removing heat generated in an interface block in a semiconductor device test system improved to extend a test function of a head body to an interface block side. It is done.

The semiconductor device test system according to the present invention for achieving the above object, the test head is provided for testing the semiconductor device under the control of the test control device; A test handler coupled to the test head to supply a plurality of semiconductor devices to the test head so that the plurality of semiconductor devices are electrically connected to the test head so that the plurality of semiconductor devices can be tested together; A support device for supporting the test head to maintain the test head stably coupled to the test handler; And a temperature controller for adjusting the temperature of the test head. The test head may include an interface board having a plurality of test sockets in electrical contact with a plurality of semiconductor devices supplied from the test handler, and reading the electrical signals from the interface board. An interface block including a testing board performing a test; And a head body which sends a control signal necessary for a test made in the interface block to the testing board. It includes, The temperature control device is characterized in that to remove the heat generated from the testing board of the interface block.

The interface block further includes a head connection board for electrically connecting the testing board to the head body side, wherein the temperature control device is to supply temperature control air (Air) between the testing board and the head connection board. More specific features.

The temperature control device, an air supply device for supplying air between the testing board and the head connection board; And an air suction device for forcibly drawing out the air between the testing board and the head connection board to the outside.

The air supply by the air supply device is another feature that is made at a plurality of positions.

The temperature control device is another feature that is provided in the test handler.

The temperature control device is another feature that is provided in the test head.

The temperature control device is another feature that is provided in the support device.

In addition, the test handler for testing a semiconductor device according to the present invention for achieving the above object, the loading device for loading the semiconductor device into the carrier board in the loading position; A test chamber accommodating a carrier board conveyed after the loading is completed by the loading apparatus, and then allowing a test to be performed while a semiconductor device loaded on the accommodated carrier board is electrically connected to a test head; An unloading device for unloading the semiconductor devices loaded on the carrier board transferred from the test chamber to the unloading position by classifying them by test grade; And a thermostat provided to remove heat generated from the test head. Characterized in that it comprises a.

The temperature control device is characterized in that it is provided to remove the heat generated from the testing board provided in the interface block of the test head.

In addition, the test head for testing a semiconductor device according to the present invention for achieving the above object, has a plurality of test sockets in electrical contact with each of a plurality of semiconductor devices supplied from a test handler, for a plurality of semiconductor devices An interface block for performing a test; And a head body which sends a control signal necessary for a test made in the interface block to the testing board. The interface block includes: an interface board having a plurality of test sockets in electrical contact with a plurality of semiconductor elements supplied from the test handler; A testing board for performing a test on a plurality of semiconductor devices by reading electrical signals from the interface board; A hermetic board provided opposite the interface board with the testing board therebetween; And an airtight frame configured as an airtight space between the testing board and the hermetic board. And at least one inlet through which air for removing heat generated from the testing board is introduced into the sealed space and at least one outlet through which air on the sealed space is discharged. Characterized in that formed.

The interface block is provided in the sealed space, and further includes a duct for injecting air flowing into the at least one inlet to the testing board side.

The hermetic board is another one of the head connection boards for electrically connecting the testing board to the head body side.

The at least one outlet is formed in the sealed board, the interface block is configured to form an outlet space on the opposite side of the sealed space with the sealed board therebetween, the housing is formed with an outlet outlet for the air on the outlet space It is characterized by another including a further.

The at least one inlet is further characterized in that formed in the closed board.

According to the present invention, the semiconductor device can be accurately tested by removing the interface block, especially the heat generated from the test board, in the improved semiconductor device test system, thereby preventing a test error from occurring due to the distortion of electrical characteristics due to the heat. It is effective.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described in more detail, for the sake of brevity of description the description overlapping with the background.

<Description of the test block's interface block>

The interface block 310 applied to the improved semiconductor device test system includes an interface board 311, a testing board 312, a head connection board 313, and the like, as referred to in the exploded view of FIG. 3. .

The interface board 311 has a plurality of test sockets 311b electrically connected to a plurality of semiconductor elements supplied from a test handler on one side of the circuit board 311a, and the other side of the circuit board 311a. On the surface has an interface board side connector 311c for electrically connecting with the testing board 312.

The testing board 312 has a first testing board side connector 312b for electrically connecting with the interface board side connector 311c on one side of the circuit board 312a and the interface board 311 on the other side. And a second test board-side connector 312d for electrically connecting the test unit 312c for performing the test of the semiconductor device by reading an electrical signal from the semiconductor device through the reference numeral) and the head connection board 313.

The head connection board 313 has a head connection board side connector 313b for electrically connecting to the testing board side second connector 312d on one side of the circuit board 313a and has a connection cable to the other side side. (CC) is electrically connected to the head body.

4 illustrates a state in which the interface block 310 is coupled as described above. Referring to FIG. 4, the interface block 310 is sealed between the testing board 312 and the head connection board 313 in the coupled state. It can be seen that it further includes a closed frame 314 that can form the space (S). That is, the head connecting board 313 and the sealing frame 314 form a sealed space on the opposite side of the interface board 311 with the testing board 312 in between, the head connecting board 313 is in view of this role Can be defined as a closed board. The sealed frame 314 is formed on the inlet 314a and the sealed space S, through which air for removing heat generated from the testing board 312, in particular, the test unit 312c, enters the sealed space S. It has an outlet 314b through which air is discharged.

5 is an exploded view of the interface block 510 according to the application of the interface block 310 of FIG. 3, and FIG. 6 is a coupling diagram of the interface block 510 of FIG. 5.

According to the interface block 510 shown in FIGS. 5 and 6, the interface board 511 and the testing board 512 are electrically connected to the interface board 511 and the testing board 512 instead of having a connector. In order to connect to each other by providing a separate GFG connector 515 having a contact terminal (T) on both sides, using a separate coupling means bolt 513 interface board 511 and the testing board 512 Take the configuration to combine. In this configuration, the gap between the interface board 511 and the testing board 512 can be minimized, thereby reducing the overall length of the interface block 510.

<Description of Semiconductor Device Test System>

In the semiconductor device test system according to the present invention, the above-described interface blocks 310 and 510 are applied. However, when the interface blocks 310 and 510 of FIG. 3 or 5 are applied, electrical signals may be distorted by heat generated by the electrical resistance in the test boards 312 and 512 such that an appropriate test for the semiconductor device may not be performed. do.

Therefore, the semiconductor device test system according to the present invention further includes a temperature control device 700 as referred to in FIG.

The temperature control device 700 includes a fan casing 710, a fan 720, a fan driving device 730, a gas supply device 740, an air supply pipe 750, an air suction pipe 760, and the like.

The fan casing 710 has an air outlet 711 formed at one side thereof and an air inlet 712 formed at the other side thereof.

The fan 720 is provided inside the fan casing 710 and discharges the air sucked through the air inlet 712 by the driving through the air outlet 711.

The fan driver 730 is provided to drive the fan 720 and may be provided as a motor.

The gas supply device 740 supplies a low temperature gas (GAS) to increase the efficiency of heat removal generated.

The air supply pipe 750 connects the air outlet 711 of the fan casing 710 and the inlet 314a of the hermetic frame 314 to interface air discharged through the air outlet 711 of the fan casing 710. It can be introduced into the closed space (S) of (310).

The air suction pipe 760 connects the air inlet 712 of the fan casing 710 with the outlet 314b of the airtight frame 314, and the air discharged from the airtight space S through the air outlet 314b receives air inlet ( 712 through the fan casing 710.

According to the semiconductor device test system to which the temperature control device 700 is applied as described above, heat generated from the testing board 312 due to the test of the semiconductor device is continuously removed by air circulating without accumulating on the testing board 312. Will be.

Of course, in order to prevent distortion of electrical characteristics due to heat, it may be sufficient to maintain the temperature of the testing board 312 at room temperature. That is, although the temperature control device 700 shown in FIG. 7 is implemented to circulate the air, as shown in FIG. 8, the air inlet 812 of the fan casing 810 sucks outside air and closes the sealed frame. Through the outlet 814b of 814, the air acyclic type that implements to discharge the air on the closed space (S) to the outside may be preferably considered. Therefore, the gas supply device 740 and the air suction pipe 760 presented as one configuration of the temperature control device 700 of FIG. 7 are not essential configurations and thus may be omitted.

And the temperature control device 700 as described above is provided in the test handler 900 as shown in Figure 9 or is provided in the test head 1000 or the support device 1100 as shown in Figures 10 and 11 Preferably, since the interface block 310 is inserted into the test chamber side of the test handler, the test block is preferably provided in the test handler.

<First application>

According to FIG. 4, although the inlet 314a and the outlet 314b are formed in the hermetically sealed frame 314, as shown in FIG. 12, the inlet 1214a and the outlet 1214b are connected to the head connection board. It may be formed on the 1213. Of course, it is also possible to form one of the inlet or outlet in the hermetic frame and the other one selectively in the head connection board. For reference, when the inlet is formed in the head connection board, the air flowing into the sealed space is ejected to the testing board, thereby preventing the air from being bypassed from the inlet to the outlet, thereby increasing the cooling efficiency of the test board. It becomes possible.

<Second application>

During the low temperature test, cold air from the test socket causes condensation on the electrical wiring on the test socket side, which may cause a test error. In order to prevent such a phenomenon, a drying device for forcibly spraying dry air has been provided.

Accordingly, in the semiconductor device test system according to the present invention, as shown in FIG. 13, the space between the interface board 1311 and the testing board 1312 is formed as a sealed space V by the sealed frame 1315. It may be desirable to further configure the drying apparatus 1300 for injecting dry air into the closed space (V).

<Third application>

FIG. 14 includes a duct 1416 having a plurality of injection holes 1416a formed in a test space 1412 in a sealed space S, and air flowing through the inlet 1414a is injected into the duct 1416. It is implemented to remove the heat of the testing board 1412 by direct injection through the 1416a to the testing board 1412 side. Such a method may increase the efficiency of heat removal and may be considered more desirable. One or more of these ducts 1416 may be provided in the form of a bar.

<4th application>

Fig. 15 is a schematic diagram of major portions of a semiconductor device test system according to a fourth application of the present invention.

As referred to in FIG. 15, according to the semiconductor device test system according to the present application, the temperature control device forcibly forces air in the sealed space S and the air supply device 1510 for supplying air into the sealed space S. FIG. It can be seen that it is composed of a suction device 1520 for drawing out (the arrow in Fig. 15 is the direction of movement of air).

In order to configure a separate suction device 1520 in the temperature control device, the interface block 1500 of the test head has an outlet space F opposite the closed space S with the head connection board 1513 interposed therebetween. It further has a housing 1515 to be constructed.

The head connection board 1513 has two inlets 1513a formed to face each other, a plurality of outlets 1513b are formed at the center portion thereof, and the housing 1515 is sealed through several outlets 1513b. An outlet 1515a through which air discharged from the space S into the outlet space F is sucked out by the suction device 1520 is formed.

For reference, although two inlets 1513a are formed in the head connection board 1513 on the schematic diagram of FIG. 15, two or more inlets may be formed according to the implementation. The reason why the inlet is configured so that the air supplied from the air supply device can be supplied to the airtight space at a plurality of locations is maximized the cooling efficiency of the testing board by distributing the air evenly to the various locations in the closed space. To do so.

According to this fourth application, the air introduced into the sealed space S at a plurality of positions cools the testing board 1511, in particular, the test unit 1511a, and then, at the center portion of the head connection board 1513. It is discharged to the outlet space (F) through the discharge port (1513b) formed. Then, the air in the outlet space F is forced out to the outside through the outlet port 1515a by the operation of the suction device 1520 (see the arrow in FIG. 15 for the moving direction of the air).

For reference, since the connection cable (CC) is densely contained in the outlet space (F), there is a problem that the movement of air is obstructed or vortices may not occur to smoothly discharge the air. The problem is solved by forcing the movement of air.

According to this fourth application, since the air is not circulated, there is an advantage that the problem that the temperature of the cooling air rises with the continuous circulation of the air does not occur.

On the other hand, in this application example, depending on the conditions required for cooling, the air cooled by the low-temperature gas is supplied by supplying air at room temperature or by configuring the gas supply device described above in the description of the semiconductor device test system. You can also supply.

As described above, the detailed description of the present invention has been made by the embodiments with reference to the accompanying drawings. However, since the above-described embodiments have only been described with reference to the preferred examples of the present invention, the present invention is limited to the above embodiments. It should not be understood to be limited, and the scope of the present invention should be understood as the following claims and equivalent concepts.

1 is a conceptual plan view of a main part of a general semiconductor device test system.

FIG. 2 is a conceptual side view of an essential part of the semiconductor device test system of FIG. 1.

3 is an exploded view of an interface block applied to a semiconductor device test system according to the present invention.

4 is a coupling diagram of the interface block of FIG. 3.

5 is an exploded view of an interface block to which the interface block of FIG. 3 is applied.

6 is a coupling diagram of the interface block of FIG. 4.

7 is a schematic diagram of a feature portion of a semiconductor device test system according to the present invention to which a temperature control device is applied.

FIG. 8 is a reference diagram for explaining the application of the feature region of FIG. 7. FIG.

9 to 11 are reference views for explaining the arrangement method of the temperature control device of FIG.

12 to 15 are reference diagrams for explaining various applications of a semiconductor device test system according to the present invention.

* Description of the code for the main parts of the drawings *

310: interface block

311: Interface board

312: testing board

313: head connection board

314: Hermetically sealed frame

700: temperature controller

Claims (14)

A test head provided to test the semiconductor device according to the control of the test control device; A test handler coupled to the test head to supply a plurality of semiconductor devices to the test head so that the plurality of semiconductor devices are electrically connected to the test head so that the plurality of semiconductor devices can be tested together; A support device for supporting the test head to maintain the test head stably coupled to the test handler; And A thermostat for adjusting the temperature of the test head; Including, The test head, An interface board having a plurality of test sockets in electrical contact with a plurality of semiconductor elements supplied from the test handler, and a testing board for testing a plurality of semiconductor devices by reading electrical signals from the interface board. An interface block; And A head body for sending a control signal for a test made in the interface block to the testing board; Including; The temperature control device is characterized in that to remove the heat generated from the testing board of the interface block Semiconductor device test system. The method of claim 1, The interface block further includes a head connecting board for electrically connecting the testing board to the head body side, The temperature control device is characterized in that for supplying a temperature control air (Air) between the testing board and the head connection board Semiconductor device test system. The method of claim 2, The temperature control device, An air supply device for supplying air between the testing board and the head connection board; And And an air suction device for forcibly drawing out the air between the testing board and the head connection board to the outside. Semiconductor device test system. The method of claim 3, The air supply by the air supply device is characterized in that made in a plurality of positions Semiconductor device test system. The method of claim 1, The temperature control device is characterized in that provided in the test handler Semiconductor device test system. The method of claim 1, The temperature control device is characterized in that provided in the test head Semiconductor device test system. The method of claim 1, The temperature control device is characterized in that provided in the support device Semiconductor device test system. A loading device for loading a semiconductor device into a carrier board at a loading position; A test chamber accommodating a carrier board conveyed after the loading is completed by the loading apparatus, and then allowing a test to be performed while a semiconductor device loaded on the accommodated carrier board is electrically connected to a test head; An unloading device for unloading the semiconductor devices loaded on the carrier board transferred from the test chamber to the unloading position by classifying them by test grade; And A thermostat provided to remove heat generated from the test head; Characterized in that it comprises Test handler for testing semiconductor devices. The method of claim 8, The temperature control device is provided to remove heat generated from the testing board provided in the interface block of the test head. Test handler for testing semiconductor devices. An interface block having a plurality of test sockets in electrical contact with a plurality of semiconductor elements supplied from a test handler, and performing a test on the plurality of semiconductor elements; And A head body for sending a control signal for a test made in the interface block to the testing board; Including; The interface block, An interface board having a plurality of test sockets in electrical contact with a plurality of semiconductor elements supplied from the test handler; A testing board for performing a test on a plurality of semiconductor devices by reading electrical signals from the interface board; An airtight board provided on the opposite side of the interface board with the testing board therebetween; And A hermetic frame configured to form a hermetic space between the testing board and the hermetic board; Including, At least one inlet through which air for removing heat generated from the testing board is introduced into the hermetic space, and at least one outlet through which air on the closed space is discharged is selectively formed in the closed board or the closed frame, respectively. By Test head for testing semiconductor devices. The method of claim 10, The interface block is provided in the sealed space, characterized in that it further comprises a duct for injecting air flowing into the at least one inlet to the testing board side Test head for testing semiconductor devices. The method of claim 10, The airtight board is a head connection board for electrically connecting the testing board to the head body side. Test head for testing semiconductor devices. The method of claim 10, The at least one outlet is formed in the closed board, The interface block constitutes an outlet space on the opposite side of the sealed space with the sealed board interposed therebetween, and further comprising a housing having an outlet port through which air on the outlet space flows. Test head for testing semiconductor devices. The method of claim 10, The at least one inlet is characterized in that formed in the closed board Test head for testing semiconductor devices.

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