KR20090088272A - Stack package - Google Patents

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Publication number
KR20090088272A
KR20090088272A KR1020080013702A KR20080013702A KR20090088272A KR 20090088272 A KR20090088272 A KR 20090088272A KR 1020080013702 A KR1020080013702 A KR 1020080013702A KR 20080013702 A KR20080013702 A KR 20080013702A KR 20090088272 A KR20090088272 A KR 20090088272A
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South Korea
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semiconductor chip
substrate
bonding wire
stack package
cavity
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KR1020080013702A
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Korean (ko)
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정영범
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주식회사 하이닉스반도체
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Priority to KR1020080013702A priority Critical patent/KR20090088272A/en
Publication of KR20090088272A publication Critical patent/KR20090088272A/en

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A stack package is provided to prevent degradation of an electrical performance by electrically connecting a bonding wire coated by an insulation material to a substrate. A cavity(C) is included in a center of a substrate(102). A first semiconductor chip(106) is attached on the cavity with a face down type. A first bonding wire(116) passes through the cavity, and connects the first semiconductor chip to the substrate. At least two or more second semiconductor chips(110,112,114) are attached on the first semiconductor chip with a face up type. A second bonding wire(118) connects the second semiconductor chip to the substrate. A surface of the second bonding wire is coated by an insulation material. The second semiconductor chip is formed with a center pad type or an edge pad type.

Description

스택 패키지{STACK PACKAGE}Stack Package {STACK PACKAGE}

본 발명은 스택 패키지에 관한 것으로, 보다 자세하게는, 본딩와이어의 표면에 절연성 물질이 코팅된 본딩와이어를 이용하여 반도체 칩들 간을 스택한 스택 패키지에 관한 것이다. The present invention relates to a stack package, and more particularly, to a stack package stacked between semiconductor chips using a bonding wire coated with an insulating material on the surface of the bonding wire.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전되고 있다. 예컨데, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다. In the semiconductor industry, packaging technology for integrated circuits is continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고성능화가 요구됨에 따라, 고용량의 반도체 모듈을 제공하기 위한 다양한 기술들이 연구 개발되고 있다. In addition, as miniaturization of electric and electronic products and high performance is required, various technologies for providing a high capacity semiconductor module have been researched and developed.

고용량의 반도체 모듈을 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다. As a method for providing a high capacity semiconductor module, there is a high integration of a memory chip, which can be realized by integrating a larger number of cells in a limited space of a semiconductor chip.

그러나, 이와 같은 메모리 칩의 고집적화는 정밀한 미세 선폭을 요구하는 등, 고난도의 기술과 많은 개발 시간을 필요로 한다. 따라서, 고용량의 반도체 모듈을 제공하기 위한 다른 방법으로서 스택(Stack) 기술이 제안되었다. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width. Therefore, a stack technology has been proposed as another method for providing a high capacity semiconductor module.

상기와 같은 스택기술은 스택된 2개의 칩을 하나의 패키지 내에 내장시키는 방법과 패키징된 2개의 단품의 패키지를 스택하는 방법이 있다. 그러나, 상기와 같이 2개의 단품의 패키지를 스택하는 방법은 전기·전자 제품의 소형화되는 추세와 더불어 그에 따른 반도체 패키지의 높이의 한계가 있다.Such a stacking technique includes a method of embedding two stacked chips in one package and stacking two packaged packages. However, the method of stacking two single packages as described above has a limit of height of the semiconductor package with the trend of miniaturization of electrical and electronic products.

따라서, 하나의 패키지의 2∼3개의 반도체 칩들을 탑재시키는 스택 패키지(Stack Package) 및 멀티 칩 패키지(Multi Chip Package)에 대한 연구가 최근 들어 활발하게 진행되고 있다. Therefore, research on a stack package and a multi chip package in which two or three semiconductor chips of one package are mounted has been actively conducted in recent years.

한편, 일반적으로 센터(Center)패드 형의 반도체 칩을 이용한 상기와 같은 스택 패키지는, 하부 및 상부 반도체 칩을 각각 페이스-다운(Face-Down) 및 페이스-업(Face-Up) 타입으로 배치하여 2단으로 스택하거나, 또는, 상기와 같은 센터패드형의 본딩패드를 재배선(Redistribution Layer : RDL)을 이용하여 에지(Edge)패드형으로 변형하고, 상기 변형된 에지패드형의 반도체 칩들 간을 3단 이상으로 스택하는 방식으로 구현하고 있다.On the other hand, such a stack package using a center pad-type semiconductor chip in general, by placing the lower and upper semiconductor chips in the face-down and face-up type, respectively Stacking in two stages or transforming the center pad-type bonding pad to the edge pad type using redistribution layer (RDL), and between the modified edge pad-type semiconductor chips It is implemented by stacking more than 3 levels.

그러나, 자세하게 도시하고 설명하지는 않았지만, 전술한 바와 같은 종래의 스택 패키지는 페이스-다운 또는 페이스-업 타입으로만 반도체 칩 간이 배치되기 때문에, 반도체 칩들을 2층 이상으로 스택하기에는 한계가 발생하게 된다.However, although not shown and described in detail, the conventional stack package as described above is disposed between the semiconductor chips only in the face-down or face-up type, so that there is a limit to stacking the semiconductor chips in two or more layers.

또한, 상부 반도체 칩을 기판과 전기적으로 연결하기 위해 긴(Long) 와이어본딩을 해야하므로, 상기 긴 와이어본딩의 휨(Warpage)을 방지하기 위해 코팅 물질 을 와이어에 주사함에 따른 전체 패키지의 공정 시간과 공정 비용이 증가하게 되며, 더욱이, 상기와 같이 긴 와이어를 본딩함에 따라 패키지를 몰딩하기 위한 몰딩 공정시, 와이어 스위핑(Wire Sweeping), 또는, 와이어들간 및 와이어와 반도체 칩 간에 접촉이 발생될 수 있으며, 이는 반도체 소자의 전기적 누설로 이어져 결국, 제품의 품질 저하를 야기한다. In addition, since long wire bonding is required to electrically connect the upper semiconductor chip with the substrate, the process time of the entire package by scanning the coating material into the wire to prevent warpage of the long wire bonding. The process cost increases, and moreover, in the molding process for molding a package by bonding the long wire as described above, wire sweeping or contact between wires and between the wire and the semiconductor chip may occur. This leads to electrical leakage of the semiconductor device, which in turn leads to a deterioration of the product.

한편, 재배선을 이용하여 반도체 칩들 간을 스택할 경우에도, 상기와 같은 재배선을 적용할 경우, 초기 장비에 대한 설치 비용이 증가하게 된다.Meanwhile, even when stacking semiconductor chips using redistribution, when the redistribution is applied, the installation cost for the initial equipment increases.

본 발명은 반도체 칩들을 다층 스택하면서도 전체 패키지의 공정 시간 및 공정 비용의 증가를 방지한 스택 패키지를 제공한다.The present invention provides a stack package that prevents an increase in processing time and process cost of an entire package while stacking semiconductor chips in multiple layers.

또한, 본 발명은 전기적 성능의 저하 방지 및 와이어 스위핑, 또는, 와이어들간 및 와이어와 반도체 칩 간의 접촉을 방지하여 반도체 소자의 전기적 누설에 따른 제품의 품질 저하를 방지한 스택 패키지를 제공한다.In addition, the present invention provides a stack package that prevents degradation of electrical performance and wire sweeping, or prevents contact between wires and wires and a semiconductor chip, thereby preventing deterioration of a product due to electrical leakage of a semiconductor device.

게다가, 본 발명은 재배선을 적용하지 않고 스택 패키지를 형성하여 초기 장비에 대한 설치 비용의 증가를 방지한 스택 패키지를 제공한다.In addition, the present invention provides a stack package that prevents an increase in installation costs for initial equipment by forming a stack package without applying redistribution.

본 발명에 따른 스택 패키지는, 중앙에 캐버티를 구비한 기판; 상기 캐버티 상에 페이스-다운(Face-down) 타입으로 부착된 제1반도체 칩; 상기 캐버티를 관통하여 상기 제1반도체 칩과 상기 기판 간을 전기적으로 연결하는 제1본딩와이어; 상 기 제1반도체 칩 상에 페이스-업(Face-Up) 타입으로 부착된 적어도 둘 이상의 제2반도체 칩; 상기 제2반도체 칩과 기판 간을 전기적으로 연결하며, 표면이 절연성 물질로 코팅된 제2본딩와이어; 및 상기 제1 및 제2반도체 칩과 제2본딩와이어를 포함한 기판의 상면과, 상기 제1본딩와이어를 포함한 기판 캐버티 부분을 밀봉하는 봉지제;를 포함한다.A stack package according to the present invention includes a substrate having a cavity in the center; A first semiconductor chip attached to the cavity in a face-down type; A first bonding wire penetrating the cavity to electrically connect the first semiconductor chip and the substrate; At least two second semiconductor chips attached to the first semiconductor chip in a face-up type; A second bonding wire electrically connecting between the second semiconductor chip and the substrate and having a surface coated with an insulating material; And an encapsulant sealing an upper surface of the substrate including the first and second semiconductor chips and the second bonding wire and a portion of the substrate cavity including the first bonding wire.

상기 제2반도체 칩은 센터패드 또는 에지패드형인 것을 특징으로 한다.The second semiconductor chip may be a center pad or an edge pad type.

상기 제1본딩와이어는 전도성 와이어 또는 절연성 물질이 코팅된 전도성 와이어로 이루어진 것을 특징으로 한다.The first bonding wire is made of a conductive wire or a conductive wire coated with an insulating material.

상기 제1반도체 칩과 기판 사이, 상기 제1반도체 칩과 제2반도체 칩 사이 및 상기 제2반도체 칩들 사이에 각각 개재된 WBL(Wafer Backside Lamination) 테이프 또는 스페이서를 더 포함한다.And a wafer backside lamination (WBL) tape or spacer interposed between the first semiconductor chip and the substrate, between the first semiconductor chip and the second semiconductor chip, and between the second semiconductor chips.

상기 기판의 타면에 부착된 외부 접속 단자를 더 포함한다.It further includes an external connection terminal attached to the other surface of the substrate.

본 발명은 스택 패키지 형성시, 캐버티를 구비한 기판 상에 제1반도체 칩을 페이스-다운 타입으로 부착하여 기판과 연결하고, 상기 제1반도체 칩 상에 적어도 둘 이상의 제2반도체 칩들을 페이스-업 타입으로 부착하며, 이때, 상기 제2반도체 칩들과 기판 간은 본딩와이어의 표면이 절연성 물질로 코팅된 본딩와이어를 본딩하여 형성함으로써, 반도체 칩들을 2층 이상으로 용이하게 스택할 수 있다.According to the present invention, when a stack package is formed, a face-down type attaches a first semiconductor chip to a substrate on a substrate having a cavity, and connects at least two or more second semiconductor chips onto the first semiconductor chip. In this case, the second semiconductor chips and the substrate may be bonded to each other by forming a bonding wire having a surface of a bonding wire coated with an insulating material, thereby easily stacking the semiconductor chips into two or more layers.

또한, 본 발명은 상기와 같이 표면이 절연성 물질로 코팅된 본딩와이어를 이용하여 스택 패키지를 형성함으로써, 상부 반도체 칩을 기판과 전기적으로 연결하 기 위해 긴 와이어본딩의 휨을 방지하기 위한 코팅 물질의 주사에 따른 전체 패키지의 공정 시간과 공정 비용의 증가를 방지할 수 있다.In addition, the present invention forms a stack package using a bonding wire coated with an insulating material as described above, thereby scanning the coating material to prevent bending of long wire bonding to electrically connect the upper semiconductor chip with the substrate. It is possible to prevent the increase of the process time and the process cost of the entire package.

게다가, 본 발명은 종래의 긴 와이어를 본딩함에 따라 패키지를 몰딩하기 위한 몰딩 공정시, 와이어 스위핑, 또는, 와이어들간 및 와이어와 반도체 칩 간에 접촉의 발생을 방지할 수 있으며, 이로 인한 반도체 소자의 전기적 누설로 인한 제품의 품질 저하를 방지할 수 있다.In addition, the present invention can prevent the occurrence of wire sweeping or contact between the wires and between the wire and the semiconductor chip during the molding process for molding the package by bonding the conventional long wire, thereby resulting in electrical It is possible to prevent deterioration of the product due to leakage.

아울러, 본 발명은 상기와 같이 표면이 절연성 물질로 코팅된 본딩와이어만을 이용하여 기판과 전기적으로 연결함으로써, 종래와 같이 재배선을 이용하지 않아도 됨에 따른, 전기적 성능의 저하를 방지할 수 있다.In addition, the present invention can be electrically connected to the substrate using only the bonding wire coated with an insulating material as described above, it is possible to prevent the deterioration of the electrical performance due to the need not to use the rewiring as in the prior art.

이하에서는, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

자세하게, 도 1은 본 발명의 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.In detail, FIG. 1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

도시된 바와 같이 본 발명의 실시예에 따른 스택 패키지(100)는, 기판(102) 상에 제1반도체 칩(106) 및 적어도 둘 이상의 반도체 칩(110, 112, 114)들이 각각 페이스-다운(Face-Down) 및 페이스-업(Face-Up) 타입으로 스택된 구조를 갖는다.As shown, the stack package 100 according to an embodiment of the present invention may include a first semiconductor chip 106 and at least two or more semiconductor chips 110, 112, and 114 on the substrate 102. It has a stacked structure with Face-Down and Face-Up types.

상기 기판(102)은 중앙에 캐버티(C)를 구비하고, 상기 캐버티(C)에 인접한 부분에 전극단자(도시안됨)를 구비하여, 상기 제1반도체 칩(106)과 상기 기판(102) 캐버티(C)에 인접한 전극단자 간이 상기 캐버티(C)를 관통하도록 연결된 제1본딩와 이어(116)에 의해 전기적으로 연결된 구조를 갖는다.The substrate 102 has a cavity C at the center and an electrode terminal (not shown) at a portion adjacent to the cavity C, so that the first semiconductor chip 106 and the substrate 102 are provided. The electrode terminal adjacent to the cavity C has a structure electrically connected by the first bonding wire 116 connected to pass through the cavity C.

여기서, 상기 제1반도체 칩(106)은 센터패드 또는 에지패드 타입으로 형성될 수 있으며, 상기 제1본딩와이어(116)는 전도성 와이어 또는 절연성 물질이 코팅된 전도성 와이어로 이루어진다.Here, the first semiconductor chip 106 may be formed as a center pad or an edge pad type, and the first bonding wire 116 is made of a conductive wire or a conductive wire coated with an insulating material.

상기 적어도 둘 이상의 반도체 칩들(110, 112, 114)과, 예컨대, 적어도 2개 내지 3개의 반도체 칩(110, 112, 114)들과 상기 기판(102) 상면의 전극단자 간은 각각 적어도 둘 이상의 제2본딩와이어(118, 120, 122)에 의해 전기적으로 연결된다.At least two semiconductor chips 110, 112, and 114, for example, at least two to three semiconductor chips 110, 112, and 114, and an electrode terminal on the upper surface of the substrate 102 may each be at least two or more materials. It is electrically connected by two bonding wires 118, 120, and 122.

이때, 상기 적어도 둘 이상의 제2본딩와이어(118, 120, 122)는 일반적으로 사용되는 본딩와이어의 표면에 절연성 물질이 코팅된 형태로 이루어진다.In this case, the at least two second bonding wires 118, 120, and 122 are formed in a form in which an insulating material is coated on a surface of a bonding wire which is generally used.

상기 제1반도체 칩(106)과 적어도 둘 이상의 제2반도체 칩들(110, 112, 114) 그리고, 상기 적어도 둘 이상의 제2반도체 칩들(110, 112, 114) 간 사이에는 WBL 테이프(104) 또는 스페이서가 개재되어, 상기 제1 및 제2반도체 칩들(106, 110, 112, 114) 간을 접착시켜줌과 아울러, 상기 각각의 제2반도체 칩들(110, 112, 114)과 연결된 제2본딩와이어(118, 120, 122)의 형태를 일정 부분 지탱해준다.WBL tape 104 or spacer between the first semiconductor chip 106 and at least two or more second semiconductor chips 110, 112, and 114 and the at least two or more second semiconductor chips 110, 112, and 114. Interposed between the first and second semiconductor chips 106, 110, 112, and 114, and a second bonding wire 118 connected to the respective second semiconductor chips 110, 112, and 114. , 120, 122) to some extent.

게다가, 상기 제1 및 제2반도체 칩들(106, 110, 112, 114)과 적어도 둘 이상의 제2본딩와이어(118, 120, 122)를 포함한 기판(102)의 상면과, 상기 제1와이어(116)를 포함하는 기판(102)의 캐버티(C) 부분이 상기 제1 및 제2반도체 칩들(106, 110, 112, 114)을 외부의 스트레스로부터 보호하기 위해 EMC(Epoxy Molding Compound)와 같은 봉지제(124)로 밀봉된다.In addition, an upper surface of the substrate 102 including the first and second semiconductor chips 106, 110, 112, and 114 and at least two second bonding wires 118, 120, and 122, and the first wire 116. A cavity (C) portion of the substrate (102) comprising an encapsulation, such as an epoxy molding compound (EMC), to protect the first and second semiconductor chips 106, 110, 112, and 114 from external stress. Sealed with agent 124.

상기 기판(102) 타면의 볼 랜드(도시안됨)에는 실장수단으로서 솔더 볼과 같은 다수의 외부 접속 단자(126)가 형성된다.On the ball land (not shown) of the other surface of the substrate 102, a plurality of external connection terminals 126 such as solder balls are formed as mounting means.

전술한 바와 같이 본 발명에 따른 스택 패키지는, 캐버티를 구비한 기판 상에 제1반도체 칩을 페이스-다운 타입으로 부착하여 기판과 연결하고, 상기 제1반도체 칩 상에 적어도 둘 이상의 제2반도체 칩들을 페이스-업 타입으로 부착하며, 이때, 상기 제2반도체 칩들과 기판 간은 표면이 절연성 물질로 감싸진 본딩와이어를 연결하여 형성함으로써, 페이스-다운 또는 페이스-업 타입으로만 반도체 칩 간이 배치시키는 종래의 스택 패키지와 달리, 상기와 같이 표면이 절연성 물질로 코팅된 본딩와이어를 연결하여 반도체 칩 들간을 스택함으로써, 반도체 칩들을 2층 이상으로 스택할 수 있다.As described above, the stack package according to the present invention attaches a first semiconductor chip in a face-down type on a substrate having a cavity and connects the substrate to the substrate, and at least two or more second semiconductors on the first semiconductor chip. The chips are attached to each other in a face-up type, wherein the second semiconductor chips and the substrate are formed by connecting bonding wires whose surfaces are covered with an insulating material, so that the semiconductor chips are simply placed in the face-down or face-up type. Unlike a conventional stack package, the semiconductor chips may be stacked in two or more layers by connecting bonding wires coated with an insulating material as described above to stack semiconductor chips.

또한, 상기와 같이 표면이 절연성 물질로 코팅된 본딩와이어를 이용하여 스택 패키지를 형성함으로써, 상부 반도체 칩을 기판과 전기적으로 연결하기 위해 긴 와이어본딩의 휨을 방지하기 위한 코팅 물질의 주사에 따른 전체 패키지의 공정 시간과 공정 비용의 증가를 방지할 수 있다.In addition, by forming a stack package using a bonding wire coated with an insulating material as described above, the entire package according to the scan of the coating material to prevent the bending of the long wire bonding to electrically connect the upper semiconductor chip with the substrate It can prevent the increase of process time and process cost.

게다가, 긴 와이어를 본딩함에 따라 패키지를 몰딩하기 위한 몰딩 공정시, 와이어 스위핑, 또는, 와이어들간 및 와이어와 반도체 칩 간에 접촉의 발생을 방지할 수 있으며, 이로 인한 반도체 소자의 전기적 누설로 인한 제품의 품질 저하를 방지할 수 있다.In addition, the bonding of long wires can prevent the occurrence of wire sweeping or contact between the wires and between the wires and the semiconductor chip during the molding process for molding the package, thereby preventing the occurrence of the product due to electrical leakage of the semiconductor device. The quality deterioration can be prevented.

아울러, 상기와 같이 표면이 절연성 물질로 코팅된 본딩와이어만을 이용하여 기판과 전기적으로 연결함으로써, 종래와 같이 재배선을 이용하지 않아도 됨에 따 른, 전기적 성능의 저하를 방지할 수 있다.In addition, by electrically connecting to the substrate using only the bonding wire coated with an insulating material as described above, it is possible to prevent the deterioration of the electrical performance due to the need not to use the rewiring as in the prior art.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 실시예에 따른 스택 패키지를 설명하기 위해 도시한 단면도.1 is a cross-sectional view illustrating a stack package according to an embodiment of the present invention.

Claims (5)

중앙에 캐버티를 구비한 기판;A substrate having a cavity in the center; 상기 캐버티 상에 페이스-다운(Face-down) 타입으로 부착된 제1반도체 칩;A first semiconductor chip attached to the cavity in a face-down type; 상기 캐버티를 관통하여 상기 제1반도체 칩과 상기 기판 간을 전기적으로 연결하는 제1본딩와이어;A first bonding wire penetrating the cavity to electrically connect the first semiconductor chip and the substrate; 상기 제1반도체 칩 상에 페이스-업(Face-Up) 타입으로 부착된 적어도 둘 이상의 제2반도체 칩;At least two second semiconductor chips attached to the first semiconductor chip in a face-up type; 상기 제2반도체 칩과 기판 간을 전기적으로 연결하며, 표면이 절연성 물질로 코팅된 제2본딩와이어; 및A second bonding wire electrically connecting between the second semiconductor chip and the substrate and having a surface coated with an insulating material; And 상기 제1 및 제2반도체 칩과 제2본딩와이어를 포함한 기판의 상면과, 상기 제1본딩와이어를 포함한 기판 캐버티 부분을 밀봉하는 봉지제;An encapsulant sealing an upper surface of the substrate including the first and second semiconductor chips and the second bonding wire and a portion of the substrate cavity including the first bonding wire; 를 포함하는 것을 특징으로 하는 스택 패키지.Stack package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제2반도체 칩은 센터패드 또는 에지패드형인 것을 특징으로 하는 스택 패키지.The second semiconductor chip is a stack package, characterized in that the center pad or edge pad type. 제 1 항에 있어서,The method of claim 1, 상기 제1본딩와이어는 전도성 와이어 또는 절연성 물질이 코팅된 전도성 와 이어로 이루어진 것을 특징으로 하는 스택 패키지.The first bonding wire is a stack package, characterized in that consisting of a conductive wire or a conductive wire coated with an insulating material. 제 1 항에 있어서,The method of claim 1, 상기 제1반도체 칩과 기판 사이, 상기 제1반도체 칩과 제2반도체 칩 사이 및 상기 제2반도체 칩들 사이에 각각 개재된 WBL(Wafer Backside Lamination) 테이프 또는 스페이서를 더 포함하는 것을 특징으로 하는 스택 패키지.The stack package further comprises a wafer backside lamination (WBL) tape or spacer interposed between the first semiconductor chip and the substrate, between the first semiconductor chip and the second semiconductor chip, and between the second semiconductor chip. . 제 1 항에 있어서,The method of claim 1, 상기 기판의 타면에 부착된 외부 접속 단자를 더 포함하는 것을 특징으로 하는 스택 패키지.The stack package further comprises an external connection terminal attached to the other surface of the substrate.
KR1020080013702A 2008-02-14 2008-02-14 Stack package KR20090088272A (en)

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