KR20090043156A - Method of forming contact plug in semiconductor device - Google Patents

Method of forming contact plug in semiconductor device Download PDF

Info

Publication number
KR20090043156A
KR20090043156A KR1020070108859A KR20070108859A KR20090043156A KR 20090043156 A KR20090043156 A KR 20090043156A KR 1020070108859 A KR1020070108859 A KR 1020070108859A KR 20070108859 A KR20070108859 A KR 20070108859A KR 20090043156 A KR20090043156 A KR 20090043156A
Authority
KR
South Korea
Prior art keywords
forming
etching process
contact plug
conductive film
gas
Prior art date
Application number
KR1020070108859A
Other languages
Korean (ko)
Inventor
김석기
이창구
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070108859A priority Critical patent/KR20090043156A/en
Publication of KR20090043156A publication Critical patent/KR20090043156A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

The present invention relates to a method for forming a contact plug of a semiconductor device, the method comprising: forming an insulating layer on a semiconductor substrate, forming a contact hole in the insulating layer, and forming a contact hole on the insulating layer including the contact hole. Forming a first conductive film, performing a first etching process on the first conductive film to remove the seam formed on the surface of the first conductive film, and allowing the first conductive film to remain under the contact hole. Performing a second etching process on the first conductive film and forming a contact plug by forming a second conductive film in the contact hole on the first conductive film, thereby increasing the resistance of the contact plug. Can be solved.

Contact Plug, Lateral Etch, Etchback, Shim

Description

Method of forming contact plug in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device for forming a contact plug of a NAND flash device.

In general, a semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device. Volatile memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are fast memory inputs and outputs but lose their stored data when their power supplies are interrupted. In contrast, nonvolatile memory devices are memory devices that retain their stored data even when their power supplies are interrupted.

Flash memory devices are a type of nonvolatile memory device that can be programmed and erased (EPROM), and in particular, these programs can be electrically erased (EEPROM). It is a highly integrated memory device developed by combining the advantages of Electrically Erasable Programmable Read Only Memory. Here, the program refers to an operation of writing data to a memory cell, and the erasing means an operation of erasing data written to the memory cell.

Such flash memory devices are classified into NOR flash memory and NAND flash memory devices according to cell structure and operating conditions. In the NOR flash memory device, a drain of each memory cell transistor is connected to a bit line. Therefore, since it is possible to program and erase an arbitrary address and to operate at a high speed, it is mainly used for an application requiring high speed operation. On the other hand, in the NAND flash memory device, a plurality of memory cell transistors are connected in series to form one string, and one string is connected between the bit line and the common source line. Therefore, since the number of drain contact plugs is relatively small, it is easy to increase the degree of integration, and thus it is mainly used in applications requiring high capacity data storage.

In such NAND flash memory devices, a plurality of word lines are formed between a source select line and a drain select line (hereinafter, referred to as a select line). The select line and the word line are formed by stacking a tunnel insulating film, a floating gate, a dielectric film, and a control gate, and the select line is electrically connected to the floating gate and the control gate. In addition, a junction region is formed between each select line and the word line. The junction region formed between the source select line is a source region, and the junction region formed between the drain select line is a drain region.

Meanwhile, in order to form a contact plug connected to the junction region between the select lines, a spacer and a self alignment contact (SAC) nitride film are formed on the sides of the select line and the word line to protect the sides of the select line and the word line. Is formed. An insulating layer is formed on the selection line and the word line, and a contact hole is formed in the insulating layer so that the junction region formed between the selection lines is exposed. The contact hole is filled with a conductive material to form a contact plug electrically connected to the junction region.

However, as the flash memory devices are increasingly integrated and miniaturized, the space between the select lines in which the source contact plug and the drain contact plug are formed is narrowing. Accordingly, since the source contact plug and the drain contact plug must be formed at a high density in a narrow space, a technology for forming a fine contact plug becomes more important.

According to an embodiment of the present invention, after filling a contact plug with a conductive film, a first etching process may be performed on the conductive film to remove a core formed on the upper surface of the conductive film, and a second etching process may be performed to leave the conductive film under the contact plug. By forming a portion, impurities do not remain inside the contact plug.

A method of forming a contact plug of a semiconductor device according to the present invention may include forming an insulating layer on a semiconductor substrate, forming a contact hole in the insulating layer, and forming a first contact layer on the insulating layer including the contact hole. Forming a conductive film, performing a first etching process on the first conductive film to remove the seam formed on the surface of the first conductive film, and forming the conductive film so that the first conductive film remains under the contact hole. Performing a second etching process on the first conductive film and forming a contact plug by forming a second conductive film in the contact hole on the first conductive film.

The first etching process may be performed by lateral etching. The first etching process may be performed using a plasma source of ECR (Electron Cyclotron Resonance) type. The first etching process may be performed as an etching gas in which SF 6 gas and CHF 3 gas are mixed at 9: 1. The first etching process may further include an O 2 gas in the etching gas. The etching gas may be supplied at a flow rate of 10 to 100 sccm, and the O 2 gas may be supplied at a flow rate of 1 to 10 sccm. The first etching process may be performed at a bottom power of 50 to 400 W and a pressure of 3 to 50 mT. After the first etching process, the first conductive layer may be 300 to 400 Å on the insulating layer. The second etching process may be performed by etch back. The second etching process may be performed using a plasma source of ECR (Electron Cyclotron Resonance) type. The second etching process may be performed using an etching gas obtained by mixing HBr gas and Cl 2 gas. The etching gas may be supplied at a flow rate of 10 to 100 sccm. In the second etching process, the bottom power may be 30 to 200 W, and the pressure may be 3 to 50 mT. The first etching process and the second etching process may be performed in-situ. The first conductive layer may be formed of polysilicon. The second conductive film may be formed of tungsten. The method may further include forming spacers on the sidewalls of the contact hole before forming the second conductive layer.

According to the method for forming a contact plug of a semiconductor device of the present invention, the problem of increasing the resistance of the contact plug can be solved. As a result, no program fail is generated, and thus a more reliable semiconductor device can be manufactured.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application. In addition, when an arbitrary film is described as being formed on another film or on a semiconductor substrate, the arbitrary film may be formed in direct contact with the other film or the semiconductor substrate, or may be formed with a third film interposed therebetween. . In addition, the thickness or size of each layer shown in the drawings may be exaggerated for convenience and clarity of description.

1A to 1G are cross-sectional views illustrating a device for forming a contact plug of a semiconductor device according to the present invention.

Referring to FIG. 1A, an insulating layer 106 is formed on a semiconductor substrate 102 on which various elements, such as a gate (not shown) or a junction region 104 such as a source region or a drain region, are formed through a conventional process. . The insulating layer 106 is preferably formed of an oxide film. Meanwhile, a buffer film (not shown) may be further formed between the semiconductor substrate 102 and the insulating layer 106 to prevent the semiconductor substrate 102 from being damaged in a subsequent contact hole etching process.

Then, a hard mask pattern (not shown) is formed on the insulating layer 106 so that the region corresponding to the junction region 104 formed in the semiconductor substrate 102 is opened. Next, a contact hole is formed in the insulating layer 106 by an etching process using a hard mask pattern (not shown). The junction area 104 is exposed under the contact hole.

Thereafter, after removing the hard mask pattern (not shown), the first conductive layer 108 is formed on the insulating layer 106 including the contact hole. The first conductive film 108 is preferably formed of polysilicon, which is a material that is easy to fill the contact hole. In this case, a seam A may be formed on the surface of the first conductive layer 108 due to the step of the insulating layer 106 due to the contact hole.

Referring to FIG. 1B, a first etching process may be performed on the upper portion of the first conductive layer 108. The first etching process is a lateral etch for removing the shim A (see FIG. 1A) formed on the surface of the first conductive layer 108. As a result, the shim A (see FIG. 1A) formed on the surface of the first conductive layer 108 may be removed and planarized. Meanwhile, after the first etching process, the first conductive layer 108 may remain in the range of 300 to 400 상 에 on the insulating layer 106.

The first etching process may be performed using a plasma source of ECR (Electron Cyclotron Resonance) type. At this time, the etching gas in which the SF 6 gas and the CHF 3 gas are mixed at 9: 1 is supplied at a flow rate of 10 to 100 sccm, and the O 2 gas is supplied at a flow rate of 1 to 10 sccm. The bottom power (bottom power) is 50 ~ 400W and the pressure is 3 ~ 50mT.

Referring to FIG. 1C, a second etching process is performed on the first conductive layer 108 (see FIG. 1B). The second etching process may be performed by an etch back process on the first conductive layer 108 (see FIG. 1B) so that the first conductive layer 108 (see FIG. 1B) remains only under the contact hole C. FIG. To carry out. As a result, a first contact plug 108a is formed below the contact hole C to form a lower portion of the contact plug according to the present invention. The second etching process may be performed in-situ with the aforementioned first etching process.

The second etching process may be performed with an ECR type plasma source. At this time, the etching gas mixed with HBr gas and Cl 2 gas is supplied at a flow rate of 10 to 100 sccm. The bottom power is 30 ~ 200W and the pressure is 3 ~ 50mT.

Referring to FIG. 1D, the spacer material layer 110 is formed on the insulating layer 106 including the contact hole C. The spacer material layer 110 may be formed of a nitride film.

Referring to FIG. 1E, anisotropic etching is performed on the spacer material layer 110 (FIG. 1D) so that the spacer material layer 110 (FIG. 1D) remains only on the sidewalls of the contact hole C. The spacer 110a is formed.

Referring to FIG. 1F, a second conductive film 112 is formed on the insulating layer 106 including the first contact plug 108a. The second conductive film 112 is preferably formed of a metal material having low resistance, for example, tungsten.

Referring to FIG. 1G, the second contact layer 112 (see FIG. 1F) formed on the insulating layer 106 may be subjected to a planarization process such as a chemical mechanical polishing (CMP) method, thereby forming a first contact plug ( A second contact plug 112a is formed in the contact hole on 108a. As a result, a contact plug including the first contact plug 108a and the second contact plug 112a is formed.

FIG. 2 is a SEM photograph showing a plan view of a semiconductor device formed up to a first contact plug 108a according to the present invention, and FIG. 3 is a view showing a first contact plug 108a and a second contact plug 112a according to the present invention. SEM photograph showing a cross-sectional view of a semiconductor device

2 and 3, since a seam or the like is not formed on the first contact plug 108a and no by-products remain, the interface B between the first contact plug 108a and the second contact plug 112a. No impurities are present. Therefore, the resistance of the interface B of the first contact plug 108a and the second contact plug 112a is increased so that the resistance of the contact plug as a whole does not occur.

Meanwhile, when the first conductive layer 108 is left under the contact hole, the first and second etching processes may be divided into the first etching process and the second etching process as in the embodiment of the present invention. . However, when the etching process is performed at once with the etch back while the shim is formed on the upper portion of the first conductive layer 108, the upper surface of the first contact plug formed under the contact hole is etched to the same degree with respect to all surfaces of the polysilicon. The shape of the shim is kept intact. Therefore, in the subsequent process, when the nitride film is formed on the first contact plug and the anisotropic etching is performed to form the spacer on the sidewall of the contact hole, the nitride film remains inside the shim formed on the upper surface of the first contact plug. The remaining nitride film is interposed between the first contact plug and the second contact plug to increase the resistance of the contact plug.

In addition, prior to the etch back process, polymechanical polishing is generally performed on polysilicon. In this case, dishing occurs in the polysilicon, so that by-products generated during chemical mechanical polishing may remain in the shim. These by-products can also cause the resistance of the contact plug to increase.

However, according to the method for forming a contact plug of the semiconductor device of the present invention, since the lateral etching is first performed on the first conductive film 108, the seam formed on the surface of the first conductive film 108 is removed first, and then the process is performed. In addition, the upper surface of the first contact plug 108a may be flat to prevent a problem of residues occurring in the shim. In addition, since the chemical mechanical polishing process is not performed, dishing does not occur so that a byproduct may remain. Therefore, the problem that the resistance of the contact plug increases because impurities are not interposed between the first contact plug 108a and the second contact plug 110a.

1A to 1G are cross-sectional views illustrating a device for forming a contact plug of a semiconductor device according to the present invention.

2 is a SEM photograph showing a plan view of a semiconductor device having a first contact plug according to the present invention.

3 is a SEM photograph showing a cross section of a semiconductor device in which a contact plug is formed according to the present invention.

<Description of the symbols for the main parts of the drawings>

102 semiconductor substrate 104 junction region

106: insulating layer 108: first conductive film

108a: first contact plug 110: spacer material layer

110a: spacer 112: second conductive film

112a: second contact plug

Claims (17)

Forming an insulating layer on the semiconductor substrate; Forming a contact hole in the insulating layer; Forming a first conductive film on the insulating layer including the contact hole; Performing a first etching process on the first conductive film to remove seams formed on the surface of the first conductive film; Performing a second etching process on the first conductive layer so that the first conductive layer remains under the contact hole; And And forming a contact plug by forming a second conductive film in the contact hole on the first conductive film. The method of claim 1, The method of claim 1, wherein the first etching process is performed by lateral etching. The method of claim 1, The method of claim 1, wherein the first etching process is performed using a plasma source of ECR (Electron Cyclotron Resonance) type. The method of claim 1, The method of claim 1, wherein the first etching process is performed using an etching gas obtained by mixing SF 6 gas and CHF 3 gas in a 9: 1 ratio. The method of claim 4, wherein The method of claim 1, wherein the first etching process further comprises O 2 gas in the etching gas. The method of claim 5, And the etching gas is supplied at a flow rate of 10 to 100 sccm and the O 2 gas is supplied at a flow rate of 1 to 10 sccm. The method of claim 1, The method of claim 1, wherein the first etching process is performed at a bottom power of 50 to 400 W and a pressure of 3 to 50 mT. The method of claim 1, The method of claim 1, wherein the first conductive layer is 300 to 400 Å on the insulating layer after the first etching process. The method of claim 1, The second etching process is a method of forming a contact plug of the semiconductor device to be etched back (etch back). The method of claim 1, The second etching process is a method of forming a contact plug of a semiconductor device is performed using a plasma source of the ECR (Electron Cyclotron Resonance) type. The method of claim 1, The second etching process is a contact plug forming method of a semiconductor device performed by the etching gas of the mixture of HBr gas and Cl 2 gas. The method of claim 11, The method of claim 1, wherein the etching gas is supplied at a flow rate of 10 to 100 sccm. The method of claim 1, The method of forming a contact plug of a semiconductor device according to the second etching process, the bottom power is 30 to 200W, the pressure is 3 to 50mT. The method of claim 1, The method of claim 1, wherein the first etching process and the second etching process are performed in-situ. The method of claim 1, The first conductive film is formed of polysilicon contact plug forming method of a semiconductor device. The method of claim 1, And the second conductive film is formed of tungsten. The method of claim 1, And forming a spacer on the sidewalls of the contact hole before forming the second conductive layer.
KR1020070108859A 2007-10-29 2007-10-29 Method of forming contact plug in semiconductor device KR20090043156A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070108859A KR20090043156A (en) 2007-10-29 2007-10-29 Method of forming contact plug in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070108859A KR20090043156A (en) 2007-10-29 2007-10-29 Method of forming contact plug in semiconductor device

Publications (1)

Publication Number Publication Date
KR20090043156A true KR20090043156A (en) 2009-05-06

Family

ID=40854038

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070108859A KR20090043156A (en) 2007-10-29 2007-10-29 Method of forming contact plug in semiconductor device

Country Status (1)

Country Link
KR (1) KR20090043156A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101159723B1 (en) * 2010-10-04 2012-06-28 에스케이하이닉스 주식회사 Contact in semiconductor device and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101159723B1 (en) * 2010-10-04 2012-06-28 에스케이하이닉스 주식회사 Contact in semiconductor device and method for forming the same

Similar Documents

Publication Publication Date Title
US7727893B2 (en) Method of forming a dielectric layer pattern and method of manufacturing a non-volatile memory device using the same
US7851350B2 (en) Semiconductor device and method of forming contact plug of semiconductor device
US7303958B2 (en) Semiconductor device and method of manufacturing the same
JP2007036173A (en) Flash memory device and manufacturing method of the same
KR100953050B1 (en) Nonvolatile memory device and method of manufacturing the same
US20070148864A1 (en) Method of manufacturing flash memory device
JP2006019570A (en) Nonvolatile semiconductor storage device and manufacturing method thereof
US20080211037A1 (en) Semiconductor Device and Method of Forming Isolation Layer Thereof
KR20090043156A (en) Method of forming contact plug in semiconductor device
US20080102618A1 (en) Method of manufacturing semiconductor device
US20060113610A1 (en) Nonvolatile memory device and method for manufacturing the same
KR20080040214A (en) Method for manufacturing gate electrode of semiconductor memory device
KR100932315B1 (en) Metal wiring formation method of semiconductor device
KR100880332B1 (en) Method of manufacturing contact plug of semiconductor device
KR100799860B1 (en) Flash memory device method for the same
US10304848B2 (en) Flash memory structure with reduced dimension of gate structure
KR20090052068A (en) Method of forming contact plug in semiconductor device
KR20100012208A (en) Method of forming non-volatile memory device
KR100714273B1 (en) butting contact forming method for semiconductor memory device
KR100875058B1 (en) Method of forming contact hole in a semiconductor device
KR100978179B1 (en) Non-volatile memory device and method of fabricating the same
KR20080063891A (en) Method for manufacturing storagenode contact in semiconductor device
KR100822600B1 (en) Method of forming metal line in semiconductor device
KR100880227B1 (en) Method manufactruing of flash memory device
KR100799056B1 (en) Method for fabricating a semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination