KR20080095650A - Method of manufacturing a memory device - Google Patents

Abstract

A method for manufacturing a memory device is provided to prevent a bit line from being exposed by forming a nitride layer, which is a protective layer, and an insulating layer thickly. A method for manufacturing a memory device includes the step of forming an etch stopping layer(216) and a conductive layer(204) on a semiconductor substrate(200) in which the landing plug is formed between gates; the step of forming a hard mask layer(206) and the protective layer on the conductive layer with materials which have different etching selectivity from each other; the step of forming a bit line by patterning the protective layer, a metal layer, the hard mask layer, and the conductive layer; the step of filling the gap between the bit lines with an insulating layer; the step of forming a storage node contact hole which expose a landing plug(214) by etching the insulating layer and the etch stopping layer.

Description

Method of manufacturing a memory device

1 is a plan view illustrating a region in which a bit line and a storage node contact plug are formed in a DRAM.

2A to 2G are cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment of the present invention, and show cross-sections cut along lines X-X and Y-Y of FIG. 1, respectively.

<Description of the symbols for the main parts of the drawings>

200 semiconductor substrate 202 gate insulating film

204: First conductive film 206: First hard mask film

208: SAC nitride film 208a: spacer

210: source and drain junction 212: first insulating film

214: landing plug 216: etch stop film

218: barrier metal film 220: third conductive film

222: second hard mask film 222a: first silicon nitride film

222b: second silicon nitride film 224: protective film

226: adhesive layer 228: spacer

230: third insulating film 232: storage node contact hole

234: storage node contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of manufacturing a memory device for preventing short between a bit line and a storage node contact (SNC) plug and improving reliability of the device. It is about.

In the manufacturing process of a DRAM memory device, a word line or a bit line around a contact hole is protected during a storage node contact hole forming process of etching an insulating layer of a portion to expose a conductive layer (for example, a landing plug) formed thereunder. A portion of the passivation layer is etched together to cause the storage node contact plug formed in the contact hole to be shorted with the word line or the bit line. In order to solve this problem, there is a method of setting a high etching selectivity between the passivation layer and the insulating layer on the word line or the bit line or forming a thick passivation layer.

However, as the design rule becomes smaller, a problem may occur because the lower region of the contact hole is not opened during the storage node contact hole forming process. In addition, the area where the contact hole lower region is opened is small, thereby increasing resistance, thereby degrading device characteristics. To improve this, the storage node contact holes are formed using an etch mask having a line shape instead of a hole shape when forming the storage node contact holes.

When the DRAM device design rule is 60 nm or less, a method of forming a storage node contact (SNC) using an etch mask having a line shape is emerging. Since it is easier to pattern the storage node contact (SNC) with a line-type etch mask than to pattern the hole-type etch mask, an exposure process for forming the storage node contact (SNC) is performed using a KrF illumination system rather than an ArF illumination system. Not only can it be used, but also the area where the lower region is opened can be secured more widely, thus eliminating unnecessary processes, that is, the process of performing the storage node contact (SNC) forming process once more to open the lower region more widely. The manufacturing cost can be lowered.

However, when the storage node contact SNC is formed using a line-type etching mask, the passivation layer on the bit line is exposed as it is. Therefore, when the insulating film etching process is performed, the protective film on the bit line is etched together with the insulating film, thereby causing a problem of exposing the bit line. In order to improve this problem, when the nitride film as the protective film is formed thick, the thickness of the insulating film therebetween is also increased. As a result, the etching process becomes difficult because the depth of the storage node contact hole to be formed in the insulating layer is deep, and it is difficult to form the storage node contact plug because voids are formed inside the contact hole.

According to the present invention, a protective film is formed on a hard mask used as an etch mask during a patterning process for a bit line, so that the protective film protects the hard mask during a subsequent etching process for forming a storage node contact (SNC) hole. Therefore, even if the hard mask is formed thin, the bit line can be prevented from being exposed. In addition, as the hard mask is thinned, the aspect ratio of the storage node contact holes formed between the bit lines can be lowered, thereby facilitating the etching process for the storage node contact holes and voiding the storage node contact plugs inside the storage node contact holes. void).

In the method of manufacturing a memory device according to an embodiment of the present invention, an etch stop layer and a conductive layer are formed on a semiconductor substrate on which a landing plug is formed between gates. The hard mask layer and the passivation layer are formed of a material having different etching selectivity on the conductive layer. The protective film, the metal film, the hard mask film, and the conductive film are patterned to form bit lines. Fill between the bit lines with an insulating film. The insulating layer and the etch stop layer are etched to form a storage node contact hole exposing the landing plug.

In the above, a barrier metal film is further formed between the etch stop film and the conductive film. The hard mask film is formed in a structure in which the first silicon nitride film and the second silicon nitride film are stacked. In the first silicon nitride film forming process, the silicon (Si) to nitride film (N) ratio is 2: 4 to 3: 5. In the second silicon nitride film forming process, the silicon (Si) to nitride film (N) ratio is set to 3.1: 4 to 4: 4. In the second silicon nitride film forming process, the silicon (Si) to nitride film (N) ratio is 3: 4.1 to 3: 5.

After forming the protective film, a heat treatment step is performed to further form an adhesive layer on the interface between the hard mask film and the protective film. The heat treatment step is carried out at a temperature of 300 ℃ to 1000 ℃. The heat treatment step is carried out in a hydrogen or nitrogen atmosphere. When the silicon (Si) to nitride film (N) ratio is 2: 4 to 3: 5, the adhesive layer is made of a tungsten silicide film. When the silicon (Si) to nitride film (N) ratio is 3.1: 4 to 4: 4, the adhesive layer is made of a tungsten nitride film. After forming the bit lines, spacers are further formed on the sidewalls of the bit lines. The storage node contact holes are formed as line-type etching masks. The etching mask is formed in a direction crossing the bit line.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a region in which a bit line and a storage node contact plug are formed in a DRAM.

A plurality of gate electrodes, for example, word lines W / L are disposed in one direction, and a plurality of bit lines B / L are disposed in a direction crossing the word lines W / L. The word line W / L and the bit line B / L are electrically isolated by the first insulating film. The bit lines B / L are arranged to be connected to the drain region (not shown), and the storage node contact plugs SNC are arranged to be connected to the source region (not shown).

2A to 2G are cross-sectional views illustrating a method of manufacturing a memory device according to an embodiment of the present invention, and show cross-sections cut along lines X-X and Y-Y of FIG. 1, respectively.

Referring to FIG. 2A, a device isolation layer (not shown) is formed on a semiconductor substrate 200 on which a plurality of devices for forming a semiconductor device are formed to define an active region and a device isolation region.

Thereafter, the gate insulating layer 202, the first conductive layer 204, and the first hard mask layer 206 are formed on the semiconductor substrate 200, and then the first hard mask layer 206 and the first hard mask layer 206 are formed by an etching process. The conductive film 204 and the gate insulating film 202 are patterned to form a gate stacked with the gate insulating film 202, the first conductive film 204, and the first hard mask film 206. In detail, the first hard mask layer 206, the first conductive layer 204, and the gate insulating layer 202 are patterned in the form of the word line (W / L) of FIG. 1.

Then, after forming a Self Align Contact (SAC) nitride film 208 on the semiconductor substrate 200 including the gate, an ion implantation process using an ion implantation mask (not shown) is performed between the gates to form a source and drain junction ( 210).

Then, a first insulating film 212 is formed on the SAC nitride film 208 to fill the gaps between the gates. After the first insulating layer 212 is formed, a chemical mechanical polishing (CMP) process is performed until the upper portion of the first hard mask layer 206 is exposed. As a result, the first insulating layer 212 remains only between the gates. Subsequently, the first insulating layer 212 and the SAC nitride layer 208 are etched on the source and drain junctions 210 to form contact holes for opening the source and drain junctions 210. In this case, the SAC nitride film 208 remains on the gate sidewall in the form of a spacer 208a.

Thereafter, the second conductive layer is formed to fill the contact hole, and then the landing plug 214 is formed by performing a chemical mechanical polishing (CMP) process.

Referring to FIG. 2B, an etch stop layer 216, a barrier metal layer 218, and a third conductive layer 220 for a bit line are formed on the semiconductor substrate 200 on which the landing plug 214 is formed. In this case, the third conductive film 220 is preferably formed of a tungsten (W) film. A second hard mask layer 222 is formed on the third conductive layer 220. In this case, the second hard mask layer 222 is formed to have a structure in which the first silicon nitride layer 222a and the second silicon nitride layer 222b are stacked. Here, the silicon (Si) to nitride (N) ratio is 2: 4 to 3: 5 in the first silicon nitride film 222a forming process, and the silicon is the first method in the second silicon nitride film 222b forming process. The (Si) to nitride film (N) ratio is formed at 3.1: 4 to 4: 4, or the silicon (Si) to nitride film (N) ratio is formed at 3: 4.1 to 3: 5 by the second method. The second hard mask layer 222 is formed on the first silicon nitride layer 222a to form the second silicon nitride layer 222b in a stacked structure. The tungsten layer may be formed during the tungsten layer formation process and the heat treatment process. This is to prevent the first silicon nitride film 222a from reacting.

Next, a passivation layer 224 is formed on the second hard mask layer 222 to protect the second hard mask layer 222. In this case, the passivation layer 224 is formed of a material having a different etching selectivity from the second hard mask layer 222, specifically, a metal material, and preferably formed of tungsten.

Referring to FIG. 2C, when the passivation layer 224 is formed of a metal material, adhesion to the second hard mask layer 222 may be weak, so that the passivation layer 224 may be separated in a subsequent process. Therefore, in order to improve adhesion between the protective film 224 and the second hard mask film 222, an adhesive layer 226 is formed at an interface between the protective film 224 and the second hard mask film 222. The adhesive layer 226 may be formed by a heat treatment process. At this time, the heat treatment step is carried out in a temperature of 300 ℃ to 1000 ℃ and hydrogen or nitrogen atmosphere. When the silicon (Si) to nitride (N) ratio of the second silicon nitride film 222b is 3.1: 4 to 4: 4, the silicon of the second silicon nitride film 222b and the tungsten of the protective film 224 react by the heat treatment process. An adhesive layer 226 made of a tungsten silicide layer is formed at an interface between the second silicon nitride layer 222b and the passivation layer 224. In addition, when the silicon (Si) to nitride (N) ratio of the second silicon nitride film 222b is 3: 4.1 to 3: 5, the nitrogen component of the second silicon nitride film 222b is formed by the heat treatment process and the tungsten of the protective film 224 is removed. In response, the adhesive layer 226 made of a tungsten nitride film is formed at the interface between the second silicon nitride film 222b and the passivation film 224. Here, during the heat treatment process, the metal component of the protective layer 224 reacts with silicon or nitrogen of the second silicon nitride layer 222b so that the thickness of the first silicon nitride layer 222a, which is the second hard mask layer 222, is not reduced. I can keep it. An adhesive layer 226 formed of a tungsten silicide film or a tungsten nitride film is formed at the interface of the second silicon nitride film 222b and the protective film 224, thereby improving adhesion between the second hard mask film 222 and the protective film 224. Due to this, the protective film 224 may be prevented from being lost.

Referring to FIG. 2D, a plug formed in the drain by patterning the passivation layer 224, the adhesive layer 226, the second hard mask layer 222, the third conductive layer 220, and the barrier metal layer 218 by an etching process may be used. Form the bit lines to be connected.

Then, a second insulating film is formed on the semiconductor substrate 200 including the bit line. At this time, the second insulating film is formed of a nitride film. The second insulating layer is etched by the etching process to form the spacers 228 on the sidewalls of the bit lines.

Referring to FIG. 2E, the third insulating film 230 is formed to fill the bit lines to insulate the bit lines, and then a chemical mechanical polishing (CMP) process is performed until the upper portion of the passivation layer 224 is exposed. 3 planarize the insulating film 230. In this case, during the planarization process, the protective layer 224 serves as an etch stop layer, so that the etching stops on the protective layer 224. As a result, the second hard mask layer 222 may be prevented from being damaged.

Referring to FIG. 2F, the third insulating layer 230 and the etch stop layer 216 are etched to form a storage node contact hole (SNC) 232 exposing an upper portion of the landing plug 214. In this case, all of the passivation layer 224 is removed during the formation of the storage node contact hole (SNC) 232, and the adhesive layer 226 is partially removed. The storage node contact hole S232 232 is formed in a line shape.

Referring to FIG. 2G, after the second silicon nitride layer 222b is removed from the adhesive layer 226 and the second hard mask layer 222, a fourth conductive layer is formed to fill the storage node contact hole (SNC) 232. The substrate is then planarized by an etchback or chemical mechanical polishing (CMP) process to form a storage node contact plug 234 to contact a storage node (not shown) formed in a subsequent process to form a storage node contact structure.

Thereafter, the capacitor and the remaining wiring forming process in contact with the storage node contact proceed according to a conventional process.

As described above, the second hard mask layer 222 is formed in a stacked structure of the first silicon nitride layer 222a and the second silicon nitride layer 222b so that the tungsten layer and the second silicon nitride layer as the protective layer 224 during the heat treatment process ( By allowing the silicon or nitride film of 222b to react, the thickness of the first silicon nitride film 222a may be maintained as it is.

In addition, by forming a tungsten silicide film or a tungsten nitride film as an adhesive layer 226 at the interface between the second silicon nitride film 222b and the passivation film 224, the adhesion between the second silicon nitride film 222b and the passivation film 224 is improved. Due to this, the protective film 224 may be prevented from being lost. As a result, a short circuit between the bit line and the storage node contact plug 234 may be prevented, and the reliability of the device may be improved to increase the yield.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the effects of the present invention are as follows.

First, a thickness of the first silicon nitride film is formed by forming a second hard mask film having a stacked structure of the first silicon nitride film and the second silicon nitride film so that the tungsten of the protective film and the silicon or nitrogen component of the second silicon nitride film react by a heat treatment process. You can keep it as it is.

Second, by forming a tungsten silicide film or a tungsten nitride film as an adhesive layer at the interface between the second silicon nitride film and the protective film, the adhesion between the second silicon nitride film and the protective film can be improved, thereby preventing the protective film from being lost due to the subsequent process.

Third, by preventing the loss of the passivation layer, it is possible to prevent a short circuit between the bit line and the storage node contact (SNC) plug, and to improve the reliability of the device to increase the yield.

Claims (14)

Forming an etch stop layer and a conductive layer on the semiconductor substrate having a landing plug formed between the gates; Forming a hard mask layer and a passivation layer on the conductive layer using materials having different etching selectivities; Patterning the passivation layer, the metal layer, the hard mask layer, and the conductive layer to form a bit line; Filling an insulating film between the bit lines; And Forming a storage node contact hole to expose the landing plug by etching the insulating layer and the etch stop layer. The method of claim 1, And forming a barrier metal layer between the etch stop layer and the conductive layer. The method of claim 1, The hard mask layer may have a structure in which a first silicon nitride layer and a second silicon nitride layer are stacked. The method of claim 3, And a silicon (Si) to nitride (N) ratio of 2: 4 to 3: 5 during the first silicon nitride film forming process. The method of claim 3, And a silicon (Si) to nitride (N) ratio of 3.1: 4 to 4: 4 in the second silicon nitride film forming process.  The method of claim 3, The method of manufacturing a memory device in which the ratio of silicon (Si) to nitride (N) is 3: 4.1 to 3: 5 during the second silicon nitride film forming process.  The method of claim 1, After forming the protective film A method of manufacturing a memory device, by performing a heat treatment process to form an adhesive layer at the interface between the hard mask film and the protective film. The method of claim 7, wherein The heat treatment process is carried out at a temperature of 300 ℃ to 1000 ℃ manufacturing method of a memory device. The method of claim 7, wherein The heat treatment step is a method of manufacturing a memory device carried out in a hydrogen or nitrogen atmosphere. The method according to claim 4 or 7, When the silicon (Si) to nitride (N) ratio is 2: 4 to 3: 5, the adhesive layer is a tungsten silicide film. The method according to claim 5 or 7, If the silicon (Si) to nitride (N) ratio is 3.1: 4 to 4: 4, the adhesive layer is a tungsten nitride film. The method of claim 1, And forming a spacer on sidewalls of the bit line after forming the bit line. The method of claim 1, The storage node contact hole may be formed as a line-type etching mask. The method of claim 13, The etching mask is formed in a direction crossing the bit line.

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