KR20080058341A - 낮은 밀러 용량 및 향상된 구동 전류를 위한 단일 게이트상의 다중 저유전율 및 고유전율 게이트 산화막 - Google Patents
낮은 밀러 용량 및 향상된 구동 전류를 위한 단일 게이트상의 다중 저유전율 및 고유전율 게이트 산화막 Download PDFInfo
- Publication number
- KR20080058341A KR20080058341A KR1020087006660A KR20087006660A KR20080058341A KR 20080058341 A KR20080058341 A KR 20080058341A KR 1020087006660 A KR1020087006660 A KR 1020087006660A KR 20087006660 A KR20087006660 A KR 20087006660A KR 20080058341 A KR20080058341 A KR 20080058341A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- gate
- dielectric constant
- gate oxide
- containing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/162,778 | 2005-09-22 | ||
| US11/162,778 US20070063277A1 (en) | 2005-09-22 | 2005-09-22 | Multiple low and high k gate oxides on single gate for lower miller capacitance and improved drive current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20080058341A true KR20080058341A (ko) | 2008-06-25 |
Family
ID=37883219
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087006660A Ceased KR20080058341A (ko) | 2005-09-22 | 2006-09-22 | 낮은 밀러 용량 및 향상된 구동 전류를 위한 단일 게이트상의 다중 저유전율 및 고유전율 게이트 산화막 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20070063277A1 (https=) |
| EP (1) | EP1927128A4 (https=) |
| JP (1) | JP2009509359A (https=) |
| KR (1) | KR20080058341A (https=) |
| CN (1) | CN101268543A (https=) |
| TW (1) | TW200713456A (https=) |
| WO (1) | WO2007038237A2 (https=) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7326655B2 (en) * | 2005-09-29 | 2008-02-05 | Tokyo Electron Limited | Method of forming an oxide layer |
| US8187486B1 (en) | 2007-12-13 | 2012-05-29 | Novellus Systems, Inc. | Modulating etch selectivity and etch rate of silicon nitride thin films |
| US8410554B2 (en) * | 2008-03-26 | 2013-04-02 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
| US8420460B2 (en) * | 2008-03-26 | 2013-04-16 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of SOI circuits |
| US7964467B2 (en) * | 2008-03-26 | 2011-06-21 | International Business Machines Corporation | Method, structure and design structure for customizing history effects of soi circuits |
| JP4902888B2 (ja) * | 2009-07-17 | 2012-03-21 | パナソニック株式会社 | 半導体装置およびその製造方法 |
| US9257325B2 (en) * | 2009-09-18 | 2016-02-09 | GlobalFoundries, Inc. | Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices |
| US8436404B2 (en) * | 2009-12-30 | 2013-05-07 | Intel Corporation | Self-aligned contacts |
| DE102010042229B4 (de) * | 2010-10-08 | 2012-10-25 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zum Steigern der Integrität eines Gatestapels mit großem ε durch Erzeugen einer gesteuerten Unterhöhlung auf der Grundlage einer Nasschemie und mit den Verfahren hergestellter Transistor |
| US8896030B2 (en) | 2012-09-07 | 2014-11-25 | Intel Corporation | Integrated circuits with selective gate electrode recess |
| US9064948B2 (en) | 2012-10-22 | 2015-06-23 | Globalfoundries Inc. | Methods of forming a semiconductor device with low-k spacers and the resulting device |
| JP5973665B2 (ja) * | 2013-06-13 | 2016-08-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | Sgtを有する半導体装置とその製造方法 |
| US9385214B2 (en) * | 2013-07-17 | 2016-07-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a selectively adjustable gate structure |
| US9431268B2 (en) | 2015-01-05 | 2016-08-30 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
| US9425041B2 (en) | 2015-01-06 | 2016-08-23 | Lam Research Corporation | Isotropic atomic layer etch for silicon oxides using no activation |
| WO2019226341A1 (en) | 2018-05-25 | 2019-11-28 | Lam Research Corporation | Thermal atomic layer etch with rapid temperature cycling |
| US11637022B2 (en) | 2018-07-09 | 2023-04-25 | Lam Research Corporation | Electron excitation atomic layer etch |
| DE102020117171A1 (de) * | 2020-06-30 | 2021-12-30 | Infineon Technologies Dresden GmbH & Co. KG | Lateral-transistor mit selbstausrichtendem body-implantat |
| WO2022169509A1 (en) | 2021-02-03 | 2022-08-11 | Lam Research Corporation | Etch selectivity control in atomic layer etching |
| CN117613005B (zh) * | 2024-01-23 | 2024-04-26 | 中国科学院长春光学精密机械与物理研究所 | 一种混合型cmos器件及其制作方法 |
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| JP3266433B2 (ja) * | 1994-12-22 | 2002-03-18 | 三菱電機株式会社 | 半導体装置の製造方法 |
| JPH113990A (ja) * | 1996-04-22 | 1999-01-06 | Sony Corp | 半導体装置およびその製造方法 |
| KR100268933B1 (ko) * | 1997-12-27 | 2000-10-16 | 김영환 | 반도체 소자의 구조 및 제조 방법 |
| US6140167A (en) * | 1998-08-18 | 2000-10-31 | Advanced Micro Devices, Inc. | High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation |
| US6492695B2 (en) * | 1999-02-16 | 2002-12-10 | Koninklijke Philips Electronics N.V. | Semiconductor arrangement with transistor gate insulator |
| US6103559A (en) * | 1999-03-30 | 2000-08-15 | Amd, Inc. (Advanced Micro Devices) | Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication |
| US6194748B1 (en) * | 1999-05-03 | 2001-02-27 | Advanced Micro Devices, Inc. | MOSFET with suppressed gate-edge fringing field effect |
| US6630712B2 (en) * | 1999-08-11 | 2003-10-07 | Advanced Micro Devices, Inc. | Transistor with dynamic source/drain extensions |
| JP3450758B2 (ja) * | 1999-09-29 | 2003-09-29 | 株式会社東芝 | 電界効果トランジスタの製造方法 |
| JP2001284360A (ja) * | 2000-03-31 | 2001-10-12 | Hitachi Ltd | 半導体装置 |
| US6777275B1 (en) * | 2000-11-15 | 2004-08-17 | Advanced Micro Devices, Inc. | Single anneal for dopant activation and silicide formation |
| US6509612B2 (en) * | 2001-05-04 | 2003-01-21 | International Business Machines Corporation | High dielectric constant materials as gate dielectrics (insulators) |
| US6720630B2 (en) * | 2001-05-30 | 2004-04-13 | International Business Machines Corporation | Structure and method for MOSFET with metallic gate electrode |
| US6586289B1 (en) * | 2001-06-15 | 2003-07-01 | International Business Machines Corporation | Anti-spacer structure for improved gate activation |
| US6531365B2 (en) * | 2001-06-22 | 2003-03-11 | International Business Machines Corporation | Anti-spacer structure for self-aligned independent gate implantation |
| US6544874B2 (en) * | 2001-08-13 | 2003-04-08 | International Business Machines Corporation | Method for forming junction on insulator (JOI) structure |
| US6642147B2 (en) * | 2001-08-23 | 2003-11-04 | International Business Machines Corporation | Method of making thermally stable planarizing films |
| US6656798B2 (en) * | 2001-09-28 | 2003-12-02 | Infineon Technologies, Ag | Gate processing method with reduced gate oxide corner and edge thinning |
| US6514808B1 (en) * | 2001-11-30 | 2003-02-04 | Motorola, Inc. | Transistor having a high K dielectric and short gate length and method therefor |
| US6562713B1 (en) * | 2002-02-19 | 2003-05-13 | International Business Machines Corporation | Method of protecting semiconductor areas while exposing a gate |
| US6709926B2 (en) * | 2002-05-31 | 2004-03-23 | International Business Machines Corporation | High performance logic and high density embedded dram with borderless contact and antispacer |
| US6777298B2 (en) * | 2002-06-14 | 2004-08-17 | International Business Machines Corporation | Elevated source drain disposable spacer CMOS |
| US6657244B1 (en) * | 2002-06-28 | 2003-12-02 | International Business Machines Corporation | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation |
| US6803315B2 (en) * | 2002-08-05 | 2004-10-12 | International Business Machines Corporation | Method for blocking implants from the gate of an electronic device via planarizing films |
| JP4080816B2 (ja) * | 2002-08-13 | 2008-04-23 | 株式会社東芝 | 電界効果トランジスタの製造方法 |
| US6686637B1 (en) * | 2002-11-21 | 2004-02-03 | International Business Machines Corporation | Gate structure with independently tailored vertical doping profile |
| JP2004207517A (ja) * | 2002-12-25 | 2004-07-22 | Semiconductor Leading Edge Technologies Inc | 半導体装置及び半導体装置の製造方法 |
| US6780694B2 (en) * | 2003-01-08 | 2004-08-24 | International Business Machines Corporation | MOS transistor |
| US6806534B2 (en) * | 2003-01-14 | 2004-10-19 | International Business Machines Corporation | Damascene method for improved MOS transistor |
| US6930060B2 (en) * | 2003-06-18 | 2005-08-16 | International Business Machines Corporation | Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric |
| US6967137B2 (en) * | 2003-07-07 | 2005-11-22 | International Business Machines Corporation | Forming collar structures in deep trench capacitors with thermally stable filler material |
| US6812105B1 (en) * | 2003-07-16 | 2004-11-02 | International Business Machines Corporation | Ultra-thin channel device with raised source and drain and solid source extension doping |
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| US7144767B2 (en) * | 2003-09-23 | 2006-12-05 | International Business Machines Corporation | NFETs using gate induced stress modulation |
| US6933577B2 (en) * | 2003-10-24 | 2005-08-23 | International Business Machines Corporation | High performance FET with laterally thin extension |
| US7026247B2 (en) * | 2003-10-28 | 2006-04-11 | International Business Machines Corporation | Nanocircuit and self-correcting etching method for fabricating same |
| DE10351030B4 (de) * | 2003-10-31 | 2008-05-29 | Qimonda Ag | Speicherzelle, DRAM und Verfahren zur Herstellung einer Transistorstruktur in einem Halbleitersubstrat |
| US7122849B2 (en) * | 2003-11-14 | 2006-10-17 | International Business Machines Corporation | Stressed semiconductor device structures having granular semiconductor material |
| US7247534B2 (en) * | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
| US6989322B2 (en) * | 2003-11-25 | 2006-01-24 | International Business Machines Corporation | Method of forming ultra-thin silicidation-stop extensions in mosfet devices |
| US7160771B2 (en) * | 2003-11-28 | 2007-01-09 | International Business Machines Corporation | Forming gate oxides having multiple thicknesses |
| US7705345B2 (en) * | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
| US7161203B2 (en) * | 2004-06-04 | 2007-01-09 | Micron Technology, Inc. | Gated field effect device comprising gate dielectric having different K regions |
| JP2007019177A (ja) * | 2005-07-06 | 2007-01-25 | Toshiba Corp | 半導体装置 |
-
2005
- 2005-09-22 US US11/162,778 patent/US20070063277A1/en not_active Abandoned
-
2006
- 2006-09-20 TW TW095134869A patent/TW200713456A/zh unknown
- 2006-09-22 JP JP2008532402A patent/JP2009509359A/ja active Pending
- 2006-09-22 CN CNA2006800342746A patent/CN101268543A/zh active Pending
- 2006-09-22 KR KR1020087006660A patent/KR20080058341A/ko not_active Ceased
- 2006-09-22 EP EP06804017A patent/EP1927128A4/en not_active Withdrawn
- 2006-09-22 WO PCT/US2006/036916 patent/WO2007038237A2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007038237A3 (en) | 2007-07-26 |
| US20070063277A1 (en) | 2007-03-22 |
| JP2009509359A (ja) | 2009-03-05 |
| EP1927128A2 (en) | 2008-06-04 |
| CN101268543A (zh) | 2008-09-17 |
| TW200713456A (en) | 2007-04-01 |
| EP1927128A4 (en) | 2009-01-28 |
| WO2007038237A2 (en) | 2007-04-05 |
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Legal Events
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| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
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St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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| A201 | Request for examination | ||
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
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| PE0902 | Notice of grounds for rejection |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
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| P22-X000 | Classification modified |
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