KR20080038101A - Method for manufacturing fine pattern of a semiconductor device - Google Patents

Abstract

A method for forming a fine pattern of a semiconductor device is provided to overcome the limit of a wavelength by performing an exposure process in two times when a patterning is performed. A nitride layer(102), a first hard mask layer, and a second hard mask layer are sequentially formed on an upper portion of a silicon substrate(100). The second hard mask layer is etched to form a hard mask layer pattern. A first photoresist pattern whose predetermined region is overlapped with the hard mask layer is formed on an upper portion of the hard mask layer pattern. The first hard mask layer and the nitride layer are etched by using the first photoresist pattern and the hard mask layer pattern. When the hard mask layer pattern is formed, a first anti-reflective layer is formed on an upper portion of the second hard mask layer. A second photoresist pattern is formed on an upper portion of the first anti-reflective layer. The first anti-reflective layer and the second hard mask layer are etched by using the second photo resist pattern as an etch mask.

Description

Method for manufacturing fine pattern of a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine pattern of a semiconductor device, and more particularly, to a semiconductor device that can solve an overlay problem caused by double patterning by performing effective double overlap patterning in a complex region such as core / ferry of a semiconductor device. It relates to a method of forming a fine pattern.

In general, in a photo-lithography process of a semiconductor wafer manufacturing process, an exposure operation for recognizing a circuit shape on a wafer is performed using a plurality of masks.

This exposure process matches the pattern formed on the mask with the pattern on the surface of the wafer and then partially transmits ultraviolet light to the photoresist deposited on the wafer using a member that selectively transmits or blocks the light on the reticle. The process of selectively exposing the photosensitive film of the said site | part is said.

Such an exposure apparatus uses an alignment key formed on a scribe lane of a mask when the wafer is loaded on a wafer stage in order to accurately expose the pattern formed on the mask to the wafer. You will go through the process.

1A is a reticle layout diagram in a core region in a method of forming a fine pattern of a conventional semiconductor device. FIG. 1B is a diagram illustrating a simulation result in which a defect occurs when patterning through the layout of FIG. 1A.

Here, FIG. 1B illustrates a simulation result when the layout of FIG. 1A is exposed to a dry device having a NA (Numerical Aperture: numerical aperture) of “1” or less. FIG. 1B shows a risk of a bridge between patterns. There is this.

That is, as shown in FIG. 1C, when preparing for the best focus, even when a slight defocus of about 0.05 μm occurs, patterning is not properly performed.

This aspect is aggravated as more integrated devices are developed. Accordingly, this problem could be solved by introducing an emulsion (Immersion) equipment that can increase the NA.

Conventional exposure process through ultraviolet (UV) has reached the limit of the pitch (Pitch) that can be exposed due to the limitation of the wavelength. In order to overcome the limitations of the exposure wavelength, a process of changing the refractive index value, such as emulsion lithography, has been disclosed. However, such a process has a disadvantage in that a lot of new investment costs are required because the price of the newly added new exposure equipment is expensive.

In order to solve this problem, there is a method of overcoming the limitation of the wavelength by dividing the layout into two types so that the pitch of the pattern exposed at once is doubled and patterning the double. This double patterning method is a method that can be used to form a small pattern to overcome the resolution limit. That is, the double patterning method has been disclosed that can be easily exposed by doubling the pitch of the pattern exposed at once by dividing the regular cell (Cell) twice.

2A is a first reticle layout diagram for double patterning in a method of forming a fine pattern of a conventional semiconductor device. 2B is a second reticle layout diagram for double patterning in the conventional method of forming a fine pattern of a semiconductor device. In addition, FIG. 2C illustrates a layout diagram in which the first and second reticles overlap when double patterning in a method of forming a fine pattern of a conventional semiconductor device.

In the case of the conventional double patterning method, as shown in FIGS. 2A and 2B, an exposure process is performed by utilizing a layout schematic diagram which is obtained by dividing the drawing of FIG. 1A as it is. Here, in the case of double patterning, an overlay between the first exposed pattern and the second exposed pattern is important.

However, this method has a problem in that the overlay margin is insufficient because it is suitable for a simple structure. In addition, the conventional double patterning method has a problem in that an overlap between the first patterning and the second patterning occurs.

That is, when the patterns are separated separately as in the cell, there is a process margin. However, when the patterns are connected to each other, such as a core / ferry region, the process margin is insufficient. Accordingly, there is a problem in that the two patterns are not connected when the overlay is separated when divided into the first patterning and the second patterning as shown in FIG. 2C.

If the overlap between each patterning is not done properly, the pattern is clustered in one direction, which results in a pattern different from the original pattern before the layout is divided. If the pattern is separated like a cell, it may be crowded to one side, but in the case of a complex pattern such as core / ferry, a double patterning method is applied to the core / ferry because the overlapped pattern is different from the original pattern. There is a problem.

The present invention was created to solve the above problems, and overcomes the limitation of the wavelength due to the increase of the pitch by dividing the layout at the time of patterning in complex areas such as core / ferry and connecting the patterns by performing overlap exposure. At the same time, it is intended to solve the overlay problem that occurs during double patterning.

The method of forming a fine pattern of a semiconductor device of the present invention comprises the steps of sequentially forming a nitride layer, a first hard mask layer and a second hard mask layer on the silicon substrate; Etching the second hard mask layer to form a hard mask layer pattern; Forming a first photoresist pattern on the hard mask layer pattern to overlap the hard mask layer pattern and a predetermined region; And etching the first hard mask layer and the nitride layer using the first photoresist pattern and the hard mask layer pattern.

The method of forming a fine pattern of a semiconductor device of the present invention comprises the steps of sequentially forming a nitride layer and the first to fifth hard mask layer on the silicon substrate; Etching the fifth hard mask layer to form a hard mask layer pattern; Forming a first photoresist pattern on the hard mask layer pattern to overlap the hard mask layer pattern and a predetermined region; And etching the first to fourth hard mask layers using the first photoresist pattern and the hard mask layer pattern.

As described above, the present invention overcomes the wavelength limitation and effectively performs exposure by doubling the pitch exposed at one time by dividing the regular cells in a complex pattern such as a core / ferry region and performing two exposures during patterning. To be able. Accordingly, it provides an effect that can solve the overlay problem that occurs during double patterning.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3A is a first reticle layout diagram for double overlap patterning in a method of forming a fine pattern of a semiconductor device according to the present invention. 3B is a second reticle layout diagram for double overlap patterning in a method of forming a fine pattern of a semiconductor device according to the present invention.

The present invention does not divide the reticle layout in the core region as shown in FIG. 1A as it is, but instead extends the pattern portions to be connected to overlap the pattern portions to be connected when exposing the first mask and the second mask. That is, as shown in Figures 3a, 3b, it can be seen that the reticle layout diagram of the present invention is longer than when compared to the conventional Figures 2a, 2b at the bottom of the pattern.

3C is a layout diagram of overlapping first and second reticles during double overlap patterning in a method of forming a fine pattern of a semiconductor device according to the present invention. 3D illustrates a patterning simulation result through the first reticle layout of FIG. 3A, and FIG. 3E illustrates a patterning simulation result through the second reticle layout of FIG. 3B.

3F is a diagram showing final patterning simulation results after first and second patterning. In this case, since there is a process margin as much as the overlapping area even if the overlay is removed, it is possible to effectively divide and pattern a complicated pattern such as a core / ferry area.

4A to 4H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

First, referring to FIG. 4A, a nitride layer 102 for etching silicon is formed on the silicon substrate 100. In addition, an amorphous carbon (A-C) layer 104 is formed on the nitride layer 102. Further, a SiON layer (silicon oxynitride film 106), a poly layer 108, a SiON layer 110, and a poly layer 112 are sequentially formed on the amorphous carbon layer 104.

Here, the SiON layer 110 serves as a barrier between the poly layers 108 and 112. In addition, the SiON layer 106 is used as a hard mask having a high selectivity when etching the amorphous carbon layer 104 formed on the substrate.

Thereafter, as shown in FIG. 4B, a bottom anti-reflective coating layer (BARC) 114 is formed on the poly layer 112. Then, the photoresist 116 pattern is formed on the lower oil-based anti-tip film 114 through the first reticle.

Here, the pattern A on the left side in which the photoresist 116 is narrowly formed shows a pattern that does not overlap, and the pattern B on the right side in which the photoresist 116 is widely formed represents a pattern in which it overlaps.

Subsequently, as shown in FIG. 4C, the poly layer 112 is etched using the photoresist 116 pattern as an etch mask to form the poly layer 112 pattern, and the lower oil-based prevention film 114 is removed.

Next, as shown in FIG. 4D, a lower oil barrier film 118 is formed on the front surface of the structure, and a photoresist 120 pattern is formed on the lower oil barrier film 118 through a second reticle.

Thereafter, as shown in FIG. 4E, the SiON layer 110 is etched using the photoresist 120 and the poly layer 112 as an etch mask. In this case, the pattern on the left side where the first and second reticle layouts do not overlap as shown in (A) is formed with the SiON layer 110 pattern of the upper layer, but the first and second reticle layouts overlap as shown in (B). The pattern on the right side is left without the SiON layer 110 pattern formed on the upper layer.

Subsequently, as shown in FIG. 4F, when the poly layer 108 of the lower layer is etched, the (B) region in which the SiON layer 110 remains on the upper layer is not etched, but the (A) region without the SiON layer 110 is etched. Is etched.

Subsequently, when the amorphous carbon layer 104 and the SiON layer 106 in the region (A) are etched, the finally obtained pattern is as shown in FIG. 4G. In addition, when the nitride layer 102, the amorphous carbon layer 104, and the SiON layer 106 in the region (A) are etched, the finally obtained pattern is shown in FIG. 4H.

In the present invention, in forming a complex pattern such as a core / ferry region, the overlapping portions of the layout are overlapped and exposed at the first and second patterning to double the pitch to overcome the limitations of the wavelength, as well as to solve the complex structure pattern. It can be formed effectively without an overlay problem. Accordingly, the present invention can effectively form a microstructure pattern by overcoming the limitation of the exposure wavelength through double overlap patterning.

1A is a reticle layout diagram in a core region in a method of forming a fine pattern of a conventional semiconductor device.

1B and 1C are diagrams for explaining simulation results in which defects are generated during patterning through the layout of FIG. 1A.

2A is a first reticle layout diagram for double patterning in a method of forming a fine pattern of a conventional semiconductor device.

FIG. 2B is a second reticle layout diagram for double patterning in a method of forming a fine pattern of a conventional semiconductor device. FIG.

FIG. 2C is a layout diagram of overlapping first and second reticles during double patterning in a method of forming a fine pattern of a conventional semiconductor device. FIG.

3A is a first reticle layout diagram for double overlap patterning in a method of forming a fine pattern of a semiconductor device according to the present invention.

3B is a second reticle layout diagram for double overlap patterning in a method for forming a fine pattern of a semiconductor device according to the present invention;

Figure 3c is a layout of the first and second reticle is overlapped during double overlap patterning in the method of forming a fine pattern of a semiconductor device according to the present invention.

3D is a diagram illustrating a patterning simulation result through the layout of FIG. 3A.

3E is a diagram illustrating a patterning simulation result through the layout of FIG. 3B.

3F shows the results of the final patterning simulation after the first and second patterning.

4A to 4H are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.

Claims (10)

Sequentially forming a nitride layer, a first hard mask layer, and a second hard mask layer on the silicon substrate; Etching the second hard mask layer to form a hard mask layer pattern; Forming a first photoresist pattern on the hard mask layer pattern to overlap the hard mask layer pattern and a predetermined region; And And etching the first hard mask layer and the nitride layer by using the first photoresist pattern and the hard mask layer pattern. The method of claim 1, wherein the hard mask layer pattern forming step Forming a first anti-reflection film on the second hard mask layer; Forming a second photoresist pattern on the first anti-reflection film; And And etching the first anti-reflection film and the second hard mask layer by using the second photoresist pattern as an etching mask. The method of claim 1, And forming a first photoresist pattern on the second anti-reflection film, after forming a second anti-reflection film on the hard mask layer pattern. The method of claim 2, wherein the first anti-reflection film or the second anti-reflection film is a bottom anti-reflective coating layer (BARC). Sequentially forming a nitride layer and first to fifth hard mask layers on the silicon substrate; Etching the fifth hard mask layer to form a hard mask layer pattern; Forming a first photoresist pattern on the hard mask layer pattern to overlap the hard mask layer pattern and a predetermined region; And And etching the first to fourth hard mask layers by using the first photoresist pattern and the hard mask layer pattern. The method of claim 5, The first hard mask layer is an amorphous carbon layer, characterized in that the method for forming a fine pattern of a semiconductor device. The method of claim 5, And the second and fourth hard mask layers are SiON layers. The method of claim 5, And the third and fifth hard mask layers are poly layers. The method of claim 5, The first and the second hard mask layer is a method of forming a fine pattern of a semiconductor device, characterized in that the etching selectivity is a different layer. The method of claim 5, And the hard mask layer pattern and the first photoresist pattern are formed in a core region or a ferry region of the semiconductor device.

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