KR20080029267A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20080029267A
KR20080029267A KR1020060095091A KR20060095091A KR20080029267A KR 20080029267 A KR20080029267 A KR 20080029267A KR 1020060095091 A KR1020060095091 A KR 1020060095091A KR 20060095091 A KR20060095091 A KR 20060095091A KR 20080029267 A KR20080029267 A KR 20080029267A
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cell
insulating film
gate
spacer
film
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KR1020060095091A
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Korean (ko)
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김나현
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주식회사 하이닉스반도체
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Publication of KR20080029267A publication Critical patent/KR20080029267A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A method for manufacturing a semiconductor device is provided to improve a burying property of an interlayer dielectric by increasing a distance between gates in a cell region. A semiconductor substrate is divided into a cell region(C) and a peripheral region(P). Plural gates(22) are formed on the respective regions. The gate includes a gate insulation film(22a), a gate conductive film(22b), and a gate hard mask film(22c). A buffer oxide film(23), a gate spacer first insulation film(24), a gate spacer second insulation film(25), and a cell spacer first insulation film(26) are separated on the substrate. The first insulation film is deposited using a nitride film. The gate spacer second insulation film is deposited using a TEOS(Tetra Ethyl Ortho Silicate) film. The cell spacer first insulation film is deposited using a nitride film. A COR(Cell Open Recess) etching process is performed on the substrate, on which the cell spacer first insulation film is formed, such that the cell spacer first insulation film and the gate spacer second insulation film are removed from the cell region.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device} Method of manufacturing semiconductor device

도 1는 종래의 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A through 2E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21: 반도체기판 22: 게이트21: semiconductor substrate 22: gate

22a: 게이트산화막 22b: 게이트 도전막22a: gate oxide film 22b: gate conductive film

22c: 게이트 하드마스크막 23: 버퍼산화막22c: gate hard mask film 23: buffer oxide film

24: 게이트 스페이서용 제1절연막24: first insulating film for the gate spacer

25: 게이트 스페이서용 제2절연막25: second insulating film for the gate spacer

26: 셀 스페이서용 제1절연막26: first insulating film for the cell spacer

27: 층간절연막 28: 콘택홀27: interlayer insulating film 28: contact hole

29: 셀 스페이서용 제2절연막29: second insulating film for the cell spacer

L/P: 랜딩플러그L / P: Landing Plug

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 층간절연막의 매립 불량에 따른 랜딩플러그 낫 오픈(not-open) 현상을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of preventing a landing plug not-open phenomenon due to a poor filling of an interlayer insulating film.

반도체 소자의 고집적화가 진행됨에 따라, 작은 셀 면적, 또는, 작은 칩 면적 내에 더 많은 패턴을 구현하기 위한 다양한 방법들이 제안되고 있다. 한 예로서, 짧은 파장의 광원을 이용함으로써, 패턴의 임계 치수를 감소시키고 있고, 이에 따라, 작은 셀 면적, 또는, 칩 면적 내에 더 많은 수의 패턴을 집적시키고 있다. As high integration of semiconductor devices proceeds, various methods for realizing more patterns within a small cell area or a small chip area have been proposed. As an example, the use of short wavelength light sources reduces the critical dimensions of the pattern, thereby integrating a larger number of patterns within a small cell area, or chip area.

한편, 고집적 반도체 소자를 구현함에 있어서는 패턴의 임계 치수를 낮추는 것도 중요하지만, 상·하 패턴들간의 안정적인 콘택을 확보하는 것도 필수적이다. 이것은 패턴의 미세화가 달성되더라도, 하부 패턴과 상부 패턴간의 안정적인 콘택이 이루어지지 않거나, 또는, 그들간의 콘택 저항이 증가되면, 소자의 신뢰성 및 고속 구동을 얻지 못하기 때문이다. On the other hand, it is important to lower the critical dimension of the pattern in the implementation of a highly integrated semiconductor device, but it is also essential to ensure a stable contact between the upper and lower patterns. This is because even if the miniaturization of the pattern is achieved, if a stable contact between the lower pattern and the upper pattern is not made, or if the contact resistance therebetween is increased, reliability and high speed driving of the device are not obtained.

이에 따라, 최근의 반도체 제조 공정에서는 하부 패턴과 상부 패턴간의 안정적인 콘택을 확보하기 위해서 자기정렬콘택(Self Aligned Contact; 이하, SAC) 공정이 적용되고 있다. Accordingly, in recent semiconductor manufacturing processes, a self aligned contact (SAC) process is applied to secure stable contact between the lower pattern and the upper pattern.

이하에서는 도 1를 참조해서 종래의 SAC 공정을 포함하는 반도체 소자의 제조방법을 설명하도록 한다. Hereinafter, a method of manufacturing a semiconductor device including a conventional SAC process will be described with reference to FIG. 1.

도 1를 참조하면, 셀지역 및 주변지역으로 구획된 반도체기판(1) 상에 게이트 절연막(2)과 게이트 도전막(3) 및 게이트 하드마스크막(4)을 적층된 게이트(G)를 형성한 후, 상기 게이트(G)를 포함한 기판 전면 상에 버퍼산화막(5)과 게이트 스페이서용 제1절연막(6)과 제2절연막(7)을 차례로 형성한다. Referring to FIG. 1, a gate G on which a gate insulating film 2, a gate conductive film 3, and a gate hard mask film 4 are stacked is formed on a semiconductor substrate 1 partitioned into a cell region and a peripheral region. After that, the buffer oxide film 5, the first insulating film 6 for the gate spacer and the second insulating film 7 are sequentially formed on the entire surface of the substrate including the gate G.

그런다음, 상기 게이트 스페이서용 제2절연막(7)을 포함한 기판 전면에 대해 COR(Cell Open Recess) 식각 공정을 수행하여 상기 셀지역에 형성된 게이트 스페이서용 제2절연막을 제거한다. Next, a COR open etching process is performed on the entire surface of the substrate including the second insulating layer 7 for the gate spacer to remove the second insulating layer for the gate spacer formed in the cell region.

여기서, 상기 COR 식각 공정은 후속 랜딩플러그의 형성영역인 콘택홀을 형성하기 위한 층간절연막 식각시, 상기 층간절연막의 식각을 용이하게 하기 위함이다.Here, the COR etching process is to facilitate the etching of the interlayer insulating layer during the etching of the interlayer insulating layer for forming the contact hole, which is a formation region of the subsequent landing plug.

다음으로, 상기 기판 전면 상에 셀 스페이서용 질화막(8)을 형성한 후, 상기 셀 스페이서용 질화막(8)이 형성된 기판 전면 상에 상기 게이트들간의 전기적 분리를 위한 층간절연막(ILD)을 형성한다. Next, after the nitride film 8 for cell spacers is formed on the entire surface of the substrate, an interlayer insulating film ILD is formed on the entire surface of the substrate on which the nitride film 8 for cell spacers is formed. .

이어서, 상기 셀지역의 층간절연막(ILD)을 식각하여 기판 표면을 노출시키는 콘택홀(C/H)을 형성한다. Subsequently, the interlayer insulating layer ILD in the cell region is etched to form a contact hole C / H exposing the substrate surface.

이후, 도시하지는 않았으나, 상기 콘택홀 내에 도전막을 매립하여 랜딩플러그(Landing Plug)를 형성한 후, 이어서 공지된 일련의 후속공정을 차례로 진행하여 반도체 소자를 제조한다. Subsequently, although not shown, a landing plug is formed by filling a conductive film in the contact hole, and then a series of known subsequent steps are sequentially performed to manufacture a semiconductor device.

한편, 점차적으로 소자의 패턴이 미세화가 되어가면서, 게이트간의 폭 또한 감소 되고, 이에 대응하여 게이트와 랜딩플러그용 물질간의 절연시켜주는 스페이서의 두께는 점차 두꺼워지고 있는 추세이다.On the other hand, as the pattern of the device is gradually miniaturized, the width between gates is also reduced, and correspondingly, the thickness of the spacer that insulates the gate and the material for the landing plug is gradually increasing.

이처럼, 상기 스페이서의 두께가 점점 두꺼워지게 되면 상기 게이트간의 폭은 그 만큼 감소하게 되면서 상기 게이트간을 절연시키는 층간절연막 형성시 막 내에 보이드(void)가 발생하게 되는데, 이러한 보이드는 상기 층간절연막 식각 공정 시, 도 1에 도시된 바와 같이, 상기 층간절연막이 미 개방되는 낫-오픈(not-open) 현상을 유발시킨다.As such, when the thickness of the spacer becomes thicker, the width between the gates decreases by that amount, and voids are generated in the film when the interlayer insulating film is formed to insulate the gates, and the voids are etched in the interlayer insulating film. As shown in FIG. 1, a not-open phenomenon is caused in which the interlayer insulating film is not opened.

결과적으로, 이러한 문제점들은 콘택 저항을 증가시켜 소자의 페일(fail) 발생을 유발시키고 있다.As a result, these problems increase the contact resistance, causing the device to fail.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로써, 층간절연막의 매립특성을 향상시켜 낫-오픈 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the sickle-open phenomenon by improving the buried characteristics of the interlayer insulating film.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 셀지역 및 주변지역으로 구획되고, 상기 각 지역에 게이트가 구비된 반도체기판 상에 버퍼산화막과 게이트 스페이서용 제1절연막 및 게이트 스페이서용 제2절연막, 그리고, 셀 스페이서용 제1절연막을 차례로 형성하는 단계; 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 제거하는 단계; 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막이 제거된 기판 전면 상에 게이트를 덮도록 층간절연막을 형성하는 단계; 상기 셀지역의 층간절연막을 식각하여 기판 표면을 노출시키는 콘택홀을 형성하는 단계; 상기 셀지역의 게이트 스페이서용 제1절연막이 형성된 게이트 양측벽에 셀 스페이서용 제2절연막을 형성하는 단계; 및 상기 콘택홀 내에 랜딩플러그를 형성하는 단계;를 포함하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention is divided into a cell region and a peripheral region, the buffer oxide film and the first insulating film for the gate spacer and the second insulating film for the gate spacer on a semiconductor substrate provided with a gate in each region; And sequentially forming a first insulating film for the cell spacer; Removing the first insulating film for the cell spacer and the second insulating film for the gate spacer in the cell region; Forming an interlayer insulating film on the entire surface of the substrate from which the first insulating film for the cell spacer and the second insulating film for the gate spacer of the cell region are removed; Forming a contact hole exposing the surface of the substrate by etching the interlayer insulating film in the cell region; Forming a second insulating film for cell spacers on both side walls of the gate where the first insulating film for gate spacers in the cell region is formed; And forming a landing plug in the contact hole.

여기서, 상기 게이트 스페이서용 제1절연막은 질화막으로, 게이트 스페이서용 제2절연막은 TEOS막으로 형성하는 것을 특징으로 한다.The first insulating film for the gate spacer may be formed of a nitride film, and the second insulating film for the gate spacer may be formed of a TEOS film.

상기 셀 스페이서용 제1절연막은 질화막으로, 셀 스페이서용 제2절연막은 질화막으로 형성하는 것을 특징으로 한다.The first insulating film for the cell spacer may be formed of a nitride film, and the second insulating film for the cell spacer may be formed of a nitride film.

상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 제거하는 단계는, 상기 셀 스페이서용 제1절연막 상에 셀지역을 노출시키는 감광막패턴을 형성하는 단계; 상기 감광막패턴을 식각마스크로 이용해서 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 선택적으로 제거하는 단계; 및 상기 감광막패턴을 제거하는 단계;로 구성되는 것을 특징으로 한다.Removing the first insulating film for the cell spacer and the second insulating film for the gate spacer of the cell region may include forming a photoresist pattern exposing the cell region on the first insulating film for the cell spacer; Selectively removing the first insulating film for the cell spacer and the second insulating film for the gate spacer using the photoresist pattern as an etching mask; And removing the photosensitive film pattern.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 주변지역의 게이트에만 셀 스페이서용 절연막을 형성하고 나서, 층간절연막을 형성한 후, 층간절연막을 식각하여 콘택홀을 형성한다. 그런다음, 상기 셀지역의 게이트에 선택적으로 셀 스페이서용 절연막을 형성하는 것을 특징으로 한다.First, the technical principle of the present invention will be described. In the present invention, the insulating film for the cell spacer is formed only in the gate of the peripheral region, the interlayer insulating film is formed, and the interlayer insulating film is etched to form the contact hole. Then, an insulating film for a cell spacer is selectively formed on the gate of the cell region.

이렇게 하면, 상기 셀지역에 셀 스페이서용 절연막이 형성되지 않은 상태로 상기 층간절연막이 형성하게 됨으로, 상기 셀지역의 넓어진 게이트간의 폭으로 인해 상기 층간절연막의 매립 특성을 향상시킬 수 있게 된다.In this case, since the interlayer insulating film is formed without the insulating film for cell spacers formed in the cell region, the buried characteristics of the interlayer insulating film can be improved due to the wider inter-gate width of the cell region.

따라서, 셀지역의 콘택홀을 형성하기 위한 층간절연막 식각시 폴리머의 방출 이 용이함에 따라 상기 층간절연막의 낫-오픈 현상을 방지할 수 있게 되어 콘택 저항의 안정화를 이룰 수 있다. Accordingly, when the interlayer insulating layer is etched to form the contact hole in the cell region, the polymer may be easily released, thereby preventing the sickle-open phenomenon of the interlayer insulating layer, thereby achieving stabilization of the contact resistance.

자세하게는, 도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기로 한다.2A to 2E will be described a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 셀지역(C) 및 주변지역(P)이 구획되고, 상기 각 지역에 게이트 절연막(22a), 게이트 도전막(22b) 및 게이트 하드마스크막(22c)으로 이루어진 수 개의 게이트(22)가 형성된 반도체 기판(21)을 마련한다.Referring to FIG. 2A, a cell region C and a peripheral region P are partitioned, and a plurality of gates including a gate insulating film 22a, a gate conductive film 22b, and a gate hard mask film 22c are formed in each region. The semiconductor substrate 21 in which the 22 was formed is provided.

그런다음, 상기 게이트(22)를 포함한 기판 전면 상에 버퍼산화막(23)과 게이트 스페이서용 제1절연막(24)과 게이트 스페이서용 제2절연막(25), 그리고, 셀 스페이서용 제1절연막(26)을 증착한다.Next, the buffer oxide film 23, the first insulating film 24 for the gate spacer 24, the second insulating film 25 for the gate spacer 25, and the first insulating film 26 for the cell spacer are formed on the entire surface of the substrate including the gate 22. E).

이때, 상기 게이트 스페이서용 제1절연막(24)은 질화막으로, 상기 게이트 스페이서용 제2절연막(25)은 TEOS(Tetra Ethyl Ortho Silicste)막으로, 상기 셀 스페이서용 제1절연막(26)을 질화막을 이용하여 증착한다. In this case, the first insulating film 24 for the gate spacer is a nitride film, the second insulating film 25 for the gate spacer is a TEOS (Tetra Ethyl Ortho Silicste) film, and the first insulating film 26 for the cell spacer is formed of a nitride film. Vapor deposition.

도 2b를 참조하면, 상기 셀 스페이서용 제1절연막(26)이 형성된 기판 결과물에 대해 COR(Cell Open Recess) 식각 공정을 수행하여 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 제거한다.Referring to FIG. 2B, a cell open recess (COR) etching process is performed on a substrate product on which the first insulating layer 26 for cell spacers is formed, and the first insulating layer for cell spacers and the second insulating layer for gate spacers in the cell region. Remove it.

자세하게는, 상기 셀 스페이서용 제1절연막(26) 상에 셀지역을 노출시키는 감광막패턴(미도시)을 형성한 후, 상기 감광막패턴을 식각마스크로 이용해서 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 선택적으로 제거한다.In detail, after forming a photoresist pattern (not shown) exposing a cell region on the first insulating layer 26 for cell spacers, the photoresist layer pattern is used as an etching mask and the first insulating layer for cell spacers in the cell region is formed. The second insulating film for the gate spacer is selectively removed.

여기서, 본 발명은 상기 COR 식각 공정 전에 상기 셀지역 및 주변지역에 셀 스페이서용 제1절연막을 형성한 후, 상기 COR 식각 공정시 상기 셀지역의 셀 스페이서용 제1절연막을 선택적으로 제거하여 상기 셀지역의 게이트간의 폭을 넓힌다.Here, the present invention forms a first insulating film for the cell spacer in the cell region and the surrounding area before the COR etching process, and selectively removes the first insulating film for the cell spacer of the cell region during the COR etching process to the cell Increase the width between gates in the area.

이와 같이, 상기 셀지역의 셀 스페이서용 제1절연막이 제거됨에 따라 상기 셀지역의 게이트간의 폭이 넓어지게 되면서 후속의 게이트간을 매립시키는 층간절연막의 매립 특성을 향상시킬 수 있다.As such, as the first insulating film for the cell spacer of the cell region is removed, the width between the gates of the cell region becomes wider, and thus the embedding characteristic of the interlayer insulating film filling the subsequent gates may be improved.

도 2c를 참조하면, 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막이 제거된 기판 전면 상에 게이트를 덮도록 BPSG(Boron Phosphorous Silicate Glass)막을 이용하여 층간절연막(27)을 형성한다.Referring to FIG. 2C, an interlayer insulating layer 27 is formed by using a BPSG (Boron Phosphorous Silicate Glass) film to cover the gate on the entire surface of the substrate from which the first insulating layer for the cell spacer and the second insulating layer for the gate spacer of the cell region are removed. Form.

도 2d를 참조하면, 상기 셀지역의 층간절연막(27)과 게이트 스페이서용 제1절연막(24) 및 버퍼산화막(23)을 식각하여 기판 표면을 노출시키는 콘택홀(28)을 형성한다.Referring to FIG. 2D, the interlayer insulating layer 27 in the cell region, the first insulating layer 24 for the gate spacer 24, and the buffer oxide layer 23 are etched to form a contact hole 28 exposing the substrate surface.

그런다음, 상기 셀지역의 게이트 스페이서용 제1절연막(24)이 형성된 게이트(22) 양측벽에 셀 스페이서용 제2절연막(29)을 형성한다.Next, a second insulating layer 29 for cell spacers is formed on both sidewalls of the gate 22 where the first insulating layer 24 for gate spacers in the cell region is formed.

이때, 상기 셀 스페이서용 제2절연막(29)을 질화막을 사용하여 형성한다.In this case, the cell insulating second insulating layer 29 is formed using a nitride film.

도 2e를 참조하면, 상기 콘택홀(28)이 매립하도록 기판 전면 상에 플러그용 도전막을 형성한 후, 이를 에치백(etch-back)하여 상기 콘택홀 내에 랜딩플러그(Landing Plug, L/P)를 형성한다.Referring to FIG. 2E, a plug conductive film is formed on the entire surface of the substrate so that the contact hole 28 is embedded, and then, a backing plug is etched back into a landing plug (L / P) in the contact hole. To form.

이후, 도시하지는 않았으나, 공지된 일련의 후속 공정을 차례로 진행하여 본 발명의 실시예에 따른 반도체 소자를 제조한다.Subsequently, although not shown, a series of successive known processes are sequentially performed to manufacture a semiconductor device according to an embodiment of the present invention.

전술한 바와 같이, 본 발명은 셀지역 및 주변지역에 형성하던 셀 스페이서용 절연막을 주변지역에 먼저 형성한 후, 랜딩플러그 형성 전에 셀지역에 셀 스페이서용 절연막을 형성함으로서, 게이트간을 절연시키는 층간절연막의 매립 특성을 향상시킬 수 있다.As described above, according to the present invention, an insulating layer for cell spacers formed in the cell region and the surrounding region is first formed in the surrounding region, and then the insulating layer for the cell spacer is formed in the cell region before the landing plug is formed, thereby insulating the interlayers. The embedding characteristics of the insulating film can be improved.

따라서, 상기 층간절연막 식각시 상기 층간절연막이 미 개방되는 낫-오픈 현상을 방지할 수 있다.Therefore, the sickle-open phenomenon in which the interlayer insulating layer is not opened when the interlayer insulating layer is etched can be prevented.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 셀지역 및 주변지역에 형성하던 셀 스페이서용 절연막을 주변지역에 먼저 형성한 후, 랜딩플러그 형성 전에 셀지역에 셀 스페이서용 절연막을 형성함으로서, 게이트간을 절연시키는 층간절연막의 매립 특성을 향상시킬 수 있다.As described above, according to the present invention, an insulating layer for cell spacers formed in the cell region and the surrounding region is first formed in the surrounding region, and then the insulating layer for the cell spacer is formed in the cell region before the landing plug is formed, thereby insulating the interlayer between gates. The embedding characteristics of the insulating film can be improved.

따라서, 본 발명은 콘택홀 형성을 위한 층간절연막 식각시 낫-오픈 발생을 방지하게 되면서 콘택 저항의 안정화를 이룰 수 있게 된다.Therefore, the present invention prevents sick-opening during etching of the interlayer insulating layer for forming the contact hole, and stabilizes the contact resistance.

Claims (4)

셀지역 및 주변지역으로 구획되고, 상기 각 지역에 게이트가 구비된 반도체기판 상에 버퍼산화막과 게이트 스페이서용 제1절연막 및 게이트 스페이서용 제2절연막, 그리고, 셀 스페이서용 제1절연막을 차례로 형성하는 단계;A buffer oxide film, a first insulating film for gate spacers, a second insulating film for gate spacers, and a first insulating film for cell spacers are sequentially formed on a semiconductor substrate divided into a cell region and a peripheral region and having a gate in each region. step; 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 제거하는 단계;Removing the first insulating film for the cell spacer and the second insulating film for the gate spacer in the cell region; 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막이 제거된 기판 전면 상에 게이트를 덮도록 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface of the substrate from which the first insulating film for the cell spacer and the second insulating film for the gate spacer of the cell region are removed; 상기 셀지역의 층간절연막을 식각하여 기판 표면을 노출시키는 콘택홀을 형성하는 단계; 및Forming a contact hole exposing the surface of the substrate by etching the interlayer insulating film in the cell region; And 상기 셀지역의 게이트 스페이서용 제1절연막이 형성된 게이트 양측벽에 셀 스페이서용 제2절연막을 형성하는 단계;Forming a second insulating film for cell spacers on both side walls of the gate where the first insulating film for gate spacers in the cell region is formed; 상기 콘택홀 내에 랜딩플러그를 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Forming a landing plug in the contact hole; manufacturing method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 게이트 스페이서용 제1절연막은 질화막으로, 게이트 스페이서용 제2절연막은 TEOS막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.Wherein the first insulating film for the gate spacer is formed of a nitride film, and the second insulating film for the gate spacer is formed of a TEOS film. 제 1 항에 있어서,The method of claim 1, 상기 셀 스페이서용 제1절연막은 질화막으로, 셀 스페이서용 제2절연막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the first insulating film for cell spacers is formed of a nitride film, and the second insulating film for cell spacers is formed of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 제거하는 단계는, Removing the first insulating film for the cell spacer and the second insulating film for the gate spacer in the cell region may include: 상기 셀 스페이서용 제1절연막 상에 셀지역을 노출시키는 감광막패턴을 형성하는 단계;Forming a photoresist layer pattern exposing a cell region on the first insulating layer for the cell spacer; 상기 감광막패턴을 식각마스크로 이용해서 셀지역의 셀 스페이서용 제1절연막과 게이트 스페이서용 제2절연막을 선택적으로 제거하는 단계; 및Selectively removing the first insulating film for the cell spacer and the second insulating film for the gate spacer using the photoresist pattern as an etching mask; And 상기 감광막패턴을 제거하는 단계;로 구성되는 것을 특징으로 하는 반도체 소자의 제조방법.Removing the photoresist pattern; and manufacturing the semiconductor device.
KR1020060095091A 2006-09-28 2006-09-28 Method of manufacturing semiconductor device KR20080029267A (en)

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