KR20080026773A - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same Download PDF

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KR20080026773A
KR20080026773A KR1020060091760A KR20060091760A KR20080026773A KR 20080026773 A KR20080026773 A KR 20080026773A KR 1020060091760 A KR1020060091760 A KR 1020060091760A KR 20060091760 A KR20060091760 A KR 20060091760A KR 20080026773 A KR20080026773 A KR 20080026773A
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South Korea
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storage electrode
contact plug
electrode contact
forming
plug
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KR1020060091760A
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Korean (ko)
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김태훈
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주식회사 하이닉스반도체
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Publication of KR20080026773A publication Critical patent/KR20080026773A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

A semiconductor device and a method for forming the same are provided to prevent characteristic deterioration by preventing a chemical reaction between an etchant and a storage electrode contact plug. A bitline(53) is connected to a landing plug which is formed on a semiconductor substrate(51). A storage electrode contact plug(57) having a shape of wine glass is formed to be connected to the landing plug. A buffer layer(59) is formed on an upper surface of the landing plug. An etch barrier(61) is formed on an upper surface of an entire structure. A sacrificial insulating layer(63) for storage electrode is formed on the upper surface of the entire structure. A storage electrode region(65) for exposing the buffer layer is formed by etching the sacrificial layer and the etch barrier. A storage electrode(67) is connected through the buffer layer to the storage electrode contact plug.

Description

반도체소자 및 그 형성방법{Semiconductor device and Method for forming the same}Semiconductor device and method for forming the same

도 1 은 종래기술의 제1실시예에 따른 반도체소자의 X 축 방향과 Y 축 방향 단면을 각각 도시한 단면도.1 is a cross-sectional view showing a cross-section of the X-axis direction and Y-axis direction of the semiconductor device according to the first embodiment of the prior art, respectively.

도 2 는 종래기술의 제2실시예에 따른 반도체소자의 X 축 방향과 Y 축 방향 단면을 각각 도시한 단면도.2 is a cross-sectional view showing a cross-section of the X-axis direction and the Y-axis direction of the semiconductor device according to the second embodiment of the prior art, respectively.

도 3 은 본 발명의 실시예에 따른 반도체소자의 X 축 방향과 Y 축 방향 단면을 각각 도시한 단면도.3 is a cross-sectional view showing a cross-section of the X-axis direction and Y-axis direction of the semiconductor device according to the embodiment of the present invention, respectively.

본 발명은 반도체소자 및 그 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 따라 와인잔 형태의 콘택플러그를 형성하고 이에 접속되는 저장전극을 형성할 때 후속 공정인 딥 아웃 ( dip out ) 공정시 저장전극 물질의 그레인 바운더리를 통하여 콘택플러그의 상측이 손상되는 현상을 방지할 수 있도록 하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same. In particular, when forming a contact plug in the form of a wine glass and forming a storage electrode connected thereto according to high integration of the semiconductor device, the semiconductor device is stored during a dip out process. The present invention relates to a technique for preventing the upper side of the contact plug from being damaged through grain boundaries of the electrode material.

최근 반도체 소자의 고집적화 추세에 따라 셀 크기가 감소되어 충분한 정전 용량을 갖는 캐패시터를 형성하기가 어려워지고 있으며, 특히, 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, a DRAM device including one MOS transistor and a capacitor has a large area in the chip. Reducing the area while increasing the capacity is an important factor for high integration of the DRAM device.

이때 상기 캐패시터는 주로 다결정 실리콘을 도전체로 하여 산화막, 질화막 또는 그 적층막인 오.엔.오(oxide-nitride-oxide)막을 유전체로 사용하고 있다. At this time, the capacitor mainly uses an oxide film, a nitride film, or an O-oxide film (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor.

따라서 캐패시터의 정전용량(C)은 C=(ε0×εr×A)/T (여기서 ε0 은 진공 유전율(permitivity of vacuum), εr 은 유전막의 유전상수(dielectric constant), A는 캐패시터의 표면적, T는 유전막의 두께)로 표시되는 캐패시터의 정전용량(C)을 증가시키기 위하여 유전상수가 높은 물질을 유전체로 사용하거나, 유전막을 얇게 형성하거나 또는 캐패시터의 표면적을 증가시키는 등의 방법이 있다.Therefore, the capacitance C of the capacitor is C = (ε0 × εr × A) / T (where ε0 is the permittivity of vacuum, εr is the dielectric constant of the dielectric film, A is the surface area of the capacitor, T In order to increase the capacitance (C) of the capacitor expressed by the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased.

그러나 이러한 방법들은 모두 각각의 문제점을 가지고 있다. 즉, 높은 유전상수를 갖는 유전물질, 예를 들어 Ta2O5, TiO2 또는 SrTiO3등이 연구되고 있으나, 이러한 물질들의 접합 파괴전압등과 같은 신뢰도 및 박막특성등이 확실하게 확인되어 있지 않아 실제 소자에 적용하기가 어려울 뿐만 아니라 재현성이 떨어지고, 유전막 두께를 감소시키는 것은 소자 동작시 유전막이 파괴되어 캐패시터의 신뢰도에 심각한 영향을 준다.However, all these methods have their own problems. That is, dielectric materials having high dielectric constants, such as Ta2O5, TiO2 or SrTiO3, have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. Not only is it difficult, but it is inferior in reproducibility, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

더욱이 캐패시터의 전하저장전극의 표면적을 증가시키기 위하여 다결정실리콘층을 다층으로 형성한 후, 이들을 관통하여 서로 연결시키는 핀(Fin) 구조로 형성하거나, 콘택의 상부에 실린더 형상의 전하저장전극을 형성하는 등의 방법을 사 용하기도 한다. Furthermore, in order to increase the surface area of the capacitor's charge storage electrode, a polysilicon layer is formed in multiple layers, and then formed into a fin structure through which they are connected to each other, or a cylindrical charge storage electrode formed on the contact. Other methods may be used.

또한, 반도체소자의 고집적화에 따라 콘택플러그와 저장전극 간의 접속이 어려워지는 현상도 유발된다. In addition, as the semiconductor device is highly integrated, the connection between the contact plug and the storage electrode becomes difficult.

도 1 은 종래기술의 제1실시예에 따른 반도체소자를 도시한 단면도로서, X 축 방향과 Y 축 방향 단면을 각각 도시한 것이다.1 is a cross-sectional view of a semiconductor device according to a first embodiment of the prior art, and illustrates cross-sections in the X-axis direction and the Y-axis direction, respectively.

도 1 을 참조하면, 반도체기판(11) 상에 비트라인(13)을 형성한다. Referring to FIG. 1, a bit line 13 is formed on a semiconductor substrate 11.

여기서, 반도체기판(11)은 활성영역을 정의하는 소자분리막(미도시)을 형성하고 상기 구조물 상에 워드라인(미도시)을 형성하고 그 사이의 활성영역에 접속되는 랜딩플러그(미도시)를 형성한 것이다. 이때, 상기 비트라인(13)은 상기 랜딩플러그의 비트라인 콘택 부분에 접속된 것이다.Here, the semiconductor substrate 11 forms a device isolation layer (not shown) defining an active region, forms a word line (not shown) on the structure, and connects a landing plug (not shown) connected to the active region therebetween. It is formed. In this case, the bit line 13 is connected to the bit line contact portion of the landing plug.

그 다음, 전체표면상부에 제1층간절연막(15)을 형성하고 이를 통하여 랜딩플러그에 접속되는 제1저장전극 콘택플러그(17)를 형성한다. Then, the first interlayer insulating film 15 is formed on the entire surface, and thereby the first storage electrode contact plug 17 is connected to the landing plug.

그리고, 상기 구조물 상에 제2층간절연막(19)을 형성하고 이를 통하여 상기 제1저장전극 콘택플러그(17)에 접속되도록 제2저장전극 콘택플러그(21)를 형성하되, 저장전극의 형성공정시 오정렬이 발생하여도 소자의 특성 열화가 발생하지 않도록 상기 제1저장전극 콘택플러그(17)와 일측만이 중첩된 형태로 형성한다. A second storage electrode contact plug 21 is formed on the structure to be connected to the first storage electrode contact plug 17 through the second interlayer dielectric layer 19, and during the formation of the storage electrode. Only one side of the first storage electrode contact plug 17 is overlapped with the first storage electrode contact plug 17 to prevent deterioration of the device even when misalignment occurs.

그 다음, 상기 구조물 상에 식각장벽층(23)인 질화막을 형성한다. Next, a nitride film as an etch barrier layer 23 is formed on the structure.

전체표면상부에 저장전극용 희생절연막(25)을 산화막으로 형성한다. A sacrificial insulating film 25 for storage electrodes is formed on the entire surface of the oxide film.

그 다음, 저장전극 마스크(미도시)를 이용한 사진식각공정으로 희생절연막(25) 및 식각장벽층(23)을 식각하여 제2저장전극 콘택플러그(21)를 노출시키는 저장전극 영역(27)을 형성한다. 이때, 상기 식각공정은 과도식각을 수반하여 제2저장전극 콘택플러그(21)를 소정깊이 식각하게 된다. Next, the storage electrode region 27 exposing the second storage electrode contact plug 21 by etching the sacrificial insulating layer 25 and the etching barrier layer 23 by a photolithography process using a storage electrode mask (not shown). Form. In this case, the etching process involves etching the second storage electrode contact plug 21 by a predetermined depth along with the transient etching.

그리고, 상기 저장전극 영역(27)에 저장전극용 도전층을 형성하여 제2저장전극 콘택플러그(21), 제1저장전극 콘택플러그(17) 및 랜딩플러그(미도시)를 통하여 반도체기판(11)에 접속되는 저장전극(29)을 형성한다.In addition, a conductive layer for a storage electrode is formed in the storage electrode area 27 to form a semiconductor substrate 11 through a second storage electrode contact plug 21, a first storage electrode contact plug 17, and a landing plug (not shown). Is formed to form a storage electrode 29.

도 2 는 종래기술의 제2실시예에 따른 반도체소자를 도시한 단면도로서, X 축 방향과 Y 축 방향 단면을 각각 도시한 것이다. 도 2 는 도 1 의 제2저장전극 콘택플러그(21)의 형성공정이 복잡하고 이로 인하여 유발되는 문제점을 해결할 수 있도록 제1저장전극 콘택플러그를 와인잔 형태로 형성함으로써 제2저장전극 콘택플러그의 형성공정을 생략할 수 있도록 한 것이다. FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the prior art, and illustrates cross sections of the X-axis direction and the Y-axis direction, respectively. FIG. 2 illustrates that the process of forming the second storage electrode contact plug 21 of FIG. 1 is complicated and the first storage electrode contact plug is formed in the shape of a wineglass to solve the problems caused by the second storage electrode contact plug 21. The formation process can be omitted.

도 2 를 참조하면, 반도체기판(31) 상에 비트라인(33)을 형성한다. Referring to FIG. 2, a bit line 33 is formed on the semiconductor substrate 31.

여기서, 반도체기판(31)은 활성영역을 정의하는 소자분리막(미도시)을 형성하고 상기 구조물 상에 워드라인(미도시)을 형성하고 그 사이의 활성영역에 접속되는 랜딩플러그(미도시)를 형성한 것이다. 이때, 상기 비트라인(33)은 상기 랜딩플러그의 비트라인 콘택 부분에 접속된 것이다.Here, the semiconductor substrate 31 forms a device isolation layer (not shown) defining an active region, forms a word line (not shown) on the structure, and connects a landing plug (not shown) connected to the active region therebetween. It is formed. In this case, the bit line 33 is connected to the bit line contact portion of the landing plug.

그 다음, 전체표면상부에 제1층간절연막(35)을 형성하고 이를 통하여 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그(37)를 폴리실리콘으로 형성한다. Next, a first interlayer insulating layer 35 is formed on the entire surface, and a wineglass-type storage electrode contact plug 37 connected to the landing plug is formed of polysilicon.

그 다음, 상기 구조물 상에 식각장벽층(39)인 질화막을 형성한다. Next, a nitride film as an etch barrier layer 39 is formed on the structure.

전체표면상부에 저장전극용 희생절연막(41)을 산화막으로 형성한다. A sacrificial insulating film 41 for a storage electrode is formed on the entire surface as an oxide film.

그 다음, 저장전극 마스크(미도시)를 이용한 사진식각공정으로 희생절연막(41) 및 식각장벽층(39)을 식각하여 저장전극 콘택플러그(37)를 노출시키는 저장전극 영역(43)을 형성한다. 이때, 상기 식각공정은 과도식각을 수반하여 저장전극 콘택플러그(37)를 소정깊이 식각하게 된다. Next, the sacrificial insulating layer 41 and the etching barrier layer 39 are etched by a photolithography process using a storage electrode mask (not shown) to form the storage electrode region 43 exposing the storage electrode contact plug 37. . In this case, the etching process involves etching the storage electrode contact plug 37 to a predetermined depth with the transient etching.

그리고, 상기 저장전극 영역(43)에 저장전극용 도전층을 형성하여 저장전극 콘택플러그(37) 및 랜딩플러그(미도시)를 통하여 반도체기판(31)에 접속되는 저장전극(45)을 형성한다.In addition, the storage electrode conductive layer is formed in the storage electrode region 43 to form the storage electrode 45 connected to the semiconductor substrate 31 through the storage electrode contact plug 37 and the landing plug (not shown). .

후속 공정으로, 상기 희생절연막(41)을 딥 아웃 ( Dip Out ) 하여 저장전극(45)의 표면을 노출시키고 그 표면에 유전체막(미도시) 및 플레이트전극(미도시)을 형성하여 캐패시터를 형성한다. In a subsequent process, the sacrificial insulating film 41 is diped out to expose the surface of the storage electrode 45 and a dielectric film (not shown) and a plate electrode (not shown) are formed on the surface to form a capacitor. do.

그러나, 딥 아웃 공정시 사용되는 에천트가 저장전극(45)의 그레인 바운더리를 통하여 저장전극 콘택플러그(37)까지 전달됨으로써 저장전극 콘택플러그(37)와 에천트의 화학작용에 의해 저장전극 콘택플러그(37)의 상측이 손상된다. However, the etchant used in the dip-out process is transferred to the storage electrode contact plug 37 through the grain boundary of the storage electrode 45 so that the storage electrode contact plug is formed by the chemical reaction between the storage electrode contact plug 37 and the etchant. The upper side of 37 is damaged.

상기한 바와 같이 종래기술에 따른 반도체소자 및 그 형성방법은, 저장전극용 희생절연막의 딥 아웃 공정시 와인잔 형태의 저장전극 콘택플러그 상측이 손상되어 소자의 특성이 열화되는 문제점이 있다. As described above, the semiconductor device and the method of forming the same according to the related art have a problem in that the upper side of the storage electrode contact plug in a wineglass is damaged during the dip-out process of the sacrificial insulating film for the storage electrode, thereby deteriorating the characteristics of the device.

본 발명은 상기한 종래기술의 문제점을 극복하기 위하여, 저장전극 콘택플러그의 상부에 버퍼층을 형성하고 저장전극용 희생절연막 및 저장전극을 형성하여 희생절연막의 딥 아웃 공정시 저장전극 콘택플러그의 손상을 방지할 수 있도록 하여 반도체소자의 고집적화에 필요한 저장전극의 특성 열화를 방지할 수 있도록 하는 반도체소자 및 그 형성방법을 제공하는데 그 목적이 있다.In order to overcome the above-mentioned problems of the related art, a buffer layer is formed on the storage electrode contact plug, and a sacrificial insulating film and a storage electrode are formed on the storage electrode contact plug to damage the storage electrode contact plug during the dip-out process of the sacrificial insulating film. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of forming the same, which can prevent the deterioration of characteristics of the storage electrode required for high integration of the semiconductor device.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자는, In order to achieve the above object, a semiconductor device according to the present invention,

반도체기판 상에 형성된 랜딩플러그와,A landing plug formed on the semiconductor substrate;

상기 랜딩플러그에 접속되는 비트라인과,A bit line connected to the landing plug,

상기 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그와,A storage electrode contact plug in the shape of a wine glass connected to the landing plug;

상기 저장전극 콘택플러그 상측에 형성된 버퍼층과,A buffer layer formed on the storage electrode contact plug;

상기 구조물 상부에 형성되는 식각장벽층 및 저장전극용 희생절연막과,An etch barrier layer and a sacrificial insulating film for a storage electrode formed on the structure;

상기 희생절연막 및 식각장벽층을 통하여 버퍼층에 접속되는 저장전극을 포함하는 것과,A storage electrode connected to the buffer layer through the sacrificial insulating layer and the etching barrier layer;

상기 버퍼층은 WSix 계열의 실리콘 질화물로 형성하는 것을 특징으로 한다. The buffer layer is formed of a silicon nitride of the WSix series.

또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 형성방법은, In addition, the method of forming a semiconductor device according to the present invention to achieve the above object,

반도체기판 상에 형성된 랜딩플러그에 접속되는 비트라인을 형성하는 단계와,Forming a bit line connected to the landing plug formed on the semiconductor substrate;

상기 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그를 형성하는 단계와,Forming a storage electrode contact plug in the shape of a wine glass connected to the landing plug;

상기 랜딩플러그 상측에 버퍼층을 형성하는 단계와,Forming a buffer layer on the landing plug;

상기 구조물 상부에 식각장벽층을 형성하는 단계와,Forming an etch barrier layer on the structure;

상기 구조물 상부에 저장전극용 희생절연막을 형성하는 단계와,Forming a sacrificial insulating film for a storage electrode on the structure;

상기 희생절연막 및 식각장벽층을 식각하여 버퍼층을 노출시키는 저장전극 영역을 형성하는 단계와,Etching the sacrificial insulating layer and the etch barrier layer to form a storage electrode region exposing a buffer layer;

상기 버퍼층을 통하여 저장전극 콘택플러그에 접속되는 저장전극을 형성하는 단계를 포함하는 것과,Forming a storage electrode connected to the storage electrode contact plug through the buffer layer;

상기 저장전극 콘택플러그는 폴리실리콘으로 형성하는 것과,The storage electrode contact plug is formed of polysilicon,

상기 버퍼층은 WSix 계열의 실리콘 산화물로 형성하는 것과,The buffer layer is formed of a silicon oxide of WSix series,

상기 버퍼층은 저장전극 콘택플러그가 형성된 구조물 상부에 버퍼 물질층을 형성하고 이를 저장전극 콘택마스크를 이용한 사진식각공정으로 패터닝하여 형성하는 것과,The buffer layer is formed by forming a buffer material layer on the structure on which the storage electrode contact plug is formed and patterning it by a photolithography process using a storage electrode contact mask;

상기 식각장벽층은 질화막으로 형성하는 것과,The etching barrier layer is formed of a nitride film,

상기 저장전극용 희생절연막은 산화막으로 형성하는 것을 특징으로 한다. The sacrificial insulating film for the storage electrode may be formed of an oxide film.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3 은 본 발명의 실시예에 따른 반도체소자를 도시한 단면도로서, X 축 방향과 Y 축 방향 단면을 각각 도시한 것이다. 3 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention, and showing cross-sections in the X- and Y-axis directions, respectively.

도 3 을 참조하면, 반도체기판(51) 상에 비트라인(53)을 형성한다. Referring to FIG. 3, a bit line 53 is formed on the semiconductor substrate 51.

여기서, 반도체기판(51)은 활성영역을 정의하는 소자분리막(미도시)을 형성하고 상기 구조물 상에 워드라인(미도시)을 형성하고 그 사이의 활성영역에 접속되는 랜딩플러그(미도시)를 형성한 것이다. 이때, 상기 비트라인(53)은 상기 랜딩플러그의 비트라인 콘택 부분에 접속된 것이다.Here, the semiconductor substrate 51 forms a device isolation layer (not shown) defining an active region, forms a word line (not shown) on the structure, and connects a landing plug (not shown) connected to the active region therebetween. It is formed. In this case, the bit line 53 is connected to the bit line contact portion of the landing plug.

그 다음, 전체표면상부에 제1층간절연막(55)을 형성하고 이를 통하여 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그(57)를 폴리실리콘으로 형성한다. Next, a first interlayer insulating film 55 is formed on the entire surface, and a wine glass-type storage electrode contact plug 57 connected to the landing plug is formed of polysilicon.

여기서, 저장전극 콘택플러그(57)는 비트라인(53)과 수직한 단면구조보다 비트라인(53)과 평행한 단면구조가 보다 와인잔 형태를 갖는다.Here, the storage electrode contact plug 57 has a wineglass shape having a cross-sectional structure parallel to the bit line 53 than a cross-sectional structure perpendicular to the bit line 53.

그 다음, 저장전극 콘택플러그(57) 상부에 버퍼층(59)을 패터닝한다. Next, the buffer layer 59 is patterned on the storage electrode contact plug 57.

이때, 버퍼층(59)은 저장전극 콘택플러그(57)가 형성된 구조물 상부에 WSix 계열의 실리콘 질화물을 증착하고 와인잔 형태의 저장전극 콘택플러그를 형성하기 위한 콘택마스크(미도시)를 이용한 사진식각공정으로 상기 실리콘 질화물을 식각하여 저장전극 콘택플러그(57) 상부에만 실리콘 질화물이 형성된 버터층(59)을 형성한다.At this time, the buffer layer 59 is a photolithography process using a contact mask (not shown) for depositing WSix-based silicon nitride on the structure on which the storage electrode contact plug 57 is formed and forming the storage electrode contact plug in the form of a wine glass. The silicon nitride is etched to form a butter layer 59 having silicon nitride formed only on the storage electrode contact plug 57.

그 다음, 상기 구조물 상에 식각장벽층(61)인 질화막을 형성한다. Next, a nitride film as an etch barrier layer 61 is formed on the structure.

전체표면상부에 저장전극용 희생절연막(63)을 산화막으로 형성한다. A sacrificial insulating film 63 for storage electrodes is formed on the entire surface of the oxide film.

그 다음, 저장전극 마스크(미도시)를 이용한 사진식각공정으로 희생절연막(63) 및 식각장벽층(61)을 식각하여 저장전극 콘택플러그(57)를 노출시키는 저장전극 영역(65)을 형성한다. 이때, 상기 식각공정은 과도식각을 수반하여 저장전극 콘택플러그(57)를 소정깊이 식각하게 된다. Next, the sacrificial insulating layer 63 and the etch barrier layer 61 are etched by a photolithography process using a storage electrode mask (not shown) to form the storage electrode region 65 exposing the storage electrode contact plug 57. . In this case, the etching process involves etching the storage electrode contact plug 57 to a predetermined depth along with the transient etching.

그리고, 상기 저장전극 영역(65)에 저장전극용 도전층을 형성하여 저장전극 콘택플러그(57) 및 랜딩플러그(미도시)를 통하여 반도체기판(51)에 접속되는 저장전극(67)을 형성한다.In addition, a storage electrode conductive layer is formed in the storage electrode region 65 to form a storage electrode 67 connected to the semiconductor substrate 51 through the storage electrode contact plug 57 and the landing plug (not shown). .

후속 공정으로, 상기 희생절연막(63)을 딥 아웃 ( Dip Out ) 하여 저장전극(67)의 표면을 노출시키고 그 표면에 유전체막(미도시) 및 플레이트전극(미도시)을 형성하여 캐패시터를 형성한다. In a subsequent process, the sacrificial insulating film 63 is diped out to expose the surface of the storage electrode 67 and a dielectric film (not shown) and a plate electrode (not shown) are formed on the surface to form a capacitor. do.

이때, 딥 아웃 공정시 사용되는 에천트가 저장전극(67)의 그레인 바운더리를 통하여 저장전극 콘택플러그(57)까지 전달되는 현상을 버퍼층(59)이 방지하여 저장전극 콘택플러그(57)와 에천트의 화학작용을 억제함으로써 저장전극 콘택플러그(57)의 특성 열화를 방지한다. At this time, the buffer layer 59 prevents the etchant used in the dip-out process from being transferred to the storage electrode contact plug 57 through the grain boundary of the storage electrode 67 to prevent the storage electrode contact plug 57 and the etchant. By suppressing the chemical reaction of the electrode, deterioration of the characteristics of the storage electrode contact plug 57 is prevented.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자 및 그 형성방법은, 와인잔 형태의 저장전극 콘택플러그의 상부에 버퍼층을 형성하고 후속 공정으로 그 상부에 저장전극을 형성하여 저장전극용 희생절연막의 제거공정시 에천트와 저장전극 콘택플러그의 화학반응을 방지하고 그에 따른 특성 열화 현상을 방지할 수 있도록 하는 효과를 제공하는 발명이다. As described above, in the semiconductor device and the method of forming the same, the buffer layer is formed on the upper portion of the wineglass-type storage electrode contact plug, and the storage electrode is formed on the storage electrode. The present invention provides an effect of preventing the chemical reaction between the etchant and the storage electrode contact plug during the process and thus preventing the deterioration of characteristics.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

반도체기판 상에 형성된 랜딩플러그에 접속되는 비트라인을 형성하는 단계와,Forming a bit line connected to the landing plug formed on the semiconductor substrate; 상기 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그를 형성하는 단계와,Forming a storage electrode contact plug in the shape of a wine glass connected to the landing plug; 상기 랜딩플러그 상측에 버퍼층을 형성하는 단계와,Forming a buffer layer on the landing plug; 상기 구조물 상부에 식각장벽층을 형성하는 단계와,Forming an etch barrier layer on the structure; 상기 구조물 상부에 저장전극용 희생절연막을 형성하는 단계와,Forming a sacrificial insulating film for a storage electrode on the structure; 상기 희생절연막 및 식각장벽층을 식각하여 버퍼층을 노출시키는 저장전극 영역을 형성하는 단계와,Etching the sacrificial insulating layer and the etch barrier layer to form a storage electrode region exposing a buffer layer; 상기 버퍼층을 통하여 저장전극 콘택플러그에 접속되는 저장전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 형성방법.And forming a storage electrode connected to the storage electrode contact plug through the buffer layer. 제 1 항에 있어서, The method of claim 1, 상기 저장전극 콘택플러그는 폴리실리콘으로 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The storage electrode contact plug is formed of polysilicon. 제 1 항에 있어서, The method of claim 1, 상기 버퍼층은 WSix 계열의 실리콘 산화물로 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The buffer layer is a method of forming a semiconductor device, characterized in that formed of silicon oxide of WSix series. 제 1 항에 있어서, The method of claim 1, 상기 버퍼층은 저장전극 콘택플러그가 형성된 구조물 상부에 버퍼 물질층을 형성하고 이를 저장전극 콘택마스크를 이용한 사진식각공정으로 패터닝하여 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The buffer layer is formed by forming a buffer material layer on the structure on which the storage electrode contact plug is formed and patterning it by a photolithography process using a storage electrode contact mask. 제 1 항에 있어서, The method of claim 1, 상기 식각장벽층은 질화막으로 형성하는 것을 특징으로 하는 반도체소자의 형성방법.And the etching barrier layer is formed of a nitride film. 제 1 항에 있어서, The method of claim 1, 상기 저장전극용 희생절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체소자의 형성방법.The sacrificial insulating film for the storage electrode is formed of an oxide film. 반도체기판 상에 형성된 랜딩플러그와,A landing plug formed on the semiconductor substrate; 상기 랜딩플러그에 접속되는 비트라인과,A bit line connected to the landing plug, 상기 랜딩플러그에 접속되는 와인잔 형태의 저장전극 콘택플러그와,A storage electrode contact plug in the shape of a wine glass connected to the landing plug; 상기 저장전극 콘택플러그 상측에 형성된 버퍼층과,A buffer layer formed on the storage electrode contact plug; 상기 구조물 상부에 형성되는 식각장벽층 및 저장전극용 희생절연막과,An etch barrier layer and a sacrificial insulating film for a storage electrode formed on the structure; 상기 희생절연막 및 식각장벽층을 통하여 버퍼층에 접속되는 저장전극을 포함하는 것을 특징으로 하는 반도체소자.And a storage electrode connected to the buffer layer through the sacrificial insulating layer and the etch barrier layer. 제 7 항에 있어서, The method of claim 7, wherein 상기 버퍼층은 WSix 계열의 실리콘 질화물로 형성하는 것을 특징으로 하는 반도체소자.The buffer layer is a semiconductor device, characterized in that formed of silicon nitride of the WSix series.
KR1020060091760A 2006-09-21 2006-09-21 Semiconductor device and method for forming the same KR20080026773A (en)

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