KR920000384B1

KR920000384B1 - Semiconductor memory device and method of fabricating thereof

Info

Publication number: KR920000384B1
Application number: KR1019890001674A
Authority: KR
Inventors: 정인술; 김재원
Original assignee: 현대전자산업 주식회사; 정몽헌
Priority date: 1989-02-14
Filing date: 1989-02-14
Publication date: 1992-01-13
Also published as: KR900013581A

Abstract

The process provides a semiconductor memory structure in which the area of the middle portion of stacked capacitor is increased in order to increase the capacitance of the stacked capacitor. The process includes steps the of: depositing a first conductive material on a drain region; etching the layer of the first conductive material by using a pattern; depositing a second conductive material thereupon in a size smaller than that of the first conductive material layer; etching the layer of the second conductive material; forming a capacitor oxide layer on the tops of the first and second material layers and on their side walls; and depositing a VCC/2 electrode material on the surface of the oxide layer, thereby increasing the area of the capacitor.

Description

Method for manufacturing semiconductor memory device and device thereof

제1도는 종래 공정에 의한 적층형 캐패시터 전하보존 전극까지 형성한 상태의 단면도.1 is a cross-sectional view of a state in which a stacked capacitor charge storage electrode is formed by a conventional process.

제2도는 종래공정으로 형성된 반도체 기억장치의 최종단면도.2 is a final sectional view of a semiconductor memory device formed by a conventional process.

제3도는 본 발명의 공정기술에 의한 적층형 캐패시터 전하보존 전극까지 형성한 상태의 단면도.3 is a cross-sectional view of a state in which a stacked capacitor charge storage electrode is formed according to the process technology of the present invention.

제4도는 본 발명의 공정으로 형성된 반도에 기억장치 최종단면도.4 is a final cross-sectional view of a memory device on the peninsula formed by the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 보호막 2 : 금속배선1: protective film 2: metal wiring

3,5 및 9 : LTO 산화막 4 : 비트선용 전도물질3,5 and 9: LTO oxide 4: conductive material for bit line

6 : VCC/2 전극용 전도물질 7 : 캐패시터 산화막(ONO)6: conductive material for VCC / 2 electrode 7: capacitor oxide film (ONO)

8 : 전하보존 전극용 1차 전도물질 8′ : 전하보존 전극용 2차 전도물질8: primary conductive material for charge storage electrode 8 ′: secondary conductive material for charge storage electrode

10 : 게이트 전도물질 11 : 게이트 산화막10: gate conductive material 11: gate oxide film

12 및 12′ : 소오스 및 드레인영역 13 : 절연산화막12 and 12 ': source and drain regions 13: insulated oxide film

14 : 실리콘기판14 silicon substrate

본 발명은 반도체 고집적 소자의 기억장치에 관한 것으로, 특히 용량을 증대시키기 위해서 MOSFET에 접속된 적층형 캐패시터 전하보존 전극의 중앙의 일정면적을 높게하는 반도체 기억장치의 제조방법 및 그 소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a semiconductor highly integrated device, and more particularly, to a method of manufacturing a semiconductor memory device and a device for increasing a predetermined area at the center of a stacked capacitor charge storage electrode connected to a MOSFET in order to increase its capacity.

DRAM 반도에 기억장치는 집적도 증가에 따라 캐패시터 구조가 트렌치형 및 적층형 구조로 크게 분류되어 지금까지 여러가지 구조들이 개발되어져 왔는데, 그중 적층형 캐패시터 구조를 갖는 종래의 반도체 기억장치의 캐패시터 전하보존 전극의 구조는 평판으로 구성되어져 있기 때문에 집적도 증가에 따른 단위셀의 면적축소시 캐패시터 용량측면에서는 그 구조상에서 한계에 도달하는 문제점이 발생되었다.As memory devices on the DRAM peninsula increase in density, capacitor structures are classified into trench and stacked structures, and various structures have been developed so far. Among them, the structure of a capacitor charge storage electrode of a conventional semiconductor memory device having a stacked capacitor structure has been developed. Since it is composed of a flat plate, when the area of the unit cell is reduced due to the increase in the density, a problem of reaching the limit in terms of the capacitor capacity has occurred.

따라서, 본 발명은 종래의 적층형 캐패시터 구조의 반도체 기억장치가 갖는 캐패시터 용량에 대한 한계를 극복하기 위하여, 전하보존 전극용 1차 전도물질의 표면적을 증가시킬 목적으로 전하보존 전극용 1차 전도물질을 소정의 두께로 형성하고 1차 전도물질 상부 일정부분에 2차 전도물질을 형성하여, 캐패시터의 용량을 증대시키는 기술을 제공하는 데에 그 목적이 있다.Accordingly, the present invention provides a primary conductive material for a charge storage electrode for the purpose of increasing the surface area of the primary conductive material for the charge storage electrode in order to overcome the limitation of the capacitor capacity of the conventional stacked capacitor semiconductor memory device. It is an object of the present invention to provide a technique for increasing the capacity of a capacitor by forming a predetermined thickness and forming a secondary conductive material on an upper portion of the primary conductive material.

즉, 본 발명에 의하면 실리콘 기판상에 MOSFET를 형성하고 드레인 전극 상부에 적층캐패시터를 형성하고 소오스전극 상부에는 비트선을 접속시켜서 한개의 MOSFET 소자와 한개의 캐패시터가 직렬로 연결된 구성으로 캐패시터의 용량을 증대시켜 단위 셀의 면적에서 용량을 증가시킨 메모리 소자를 제공할 수 있게 되었다.That is, according to the present invention, a MOSFET is formed on a silicon substrate, a stacked capacitor is formed on the drain electrode, and a bit line is connected on the source electrode to connect one MOSFET element and one capacitor in series so that the capacitance of the capacitor is increased. It is possible to provide a memory device having an increased capacity in an area of a unit cell.

이하, 본 발명을 첨부된 도면을 참고로 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 종래의 적층캐패시터의 전하보존 전극을 형성하는 단계까지의 단면도로써, 실리콘 기판(14)상에 게이트 산화막(11)을 형성한 후 게이트 전도물질(10)을 형성하고, 소오스 및 드레인영역(12 및 12′)을 형성한 후 게이트 전극 위에 LTO 산화막(()이 일정두께로 형성하고 드레인영역(12′)상부에는 전하보존 전극용 1차 전도물질(8)을 일정두께로 평탄하게 침착하고 패턴을 형성한 상태의 단면도이다.FIG. 1 is a cross-sectional view of a conventional capacitor for forming charge storage electrodes. The gate oxide film 11 is formed on a silicon substrate 14, and then a gate conductive material 10 is formed. After forming (12 and 12 '), an LTO oxide film (()) is formed on the gate electrode with a predetermined thickness, and the primary conductive material 8 for the charge storage electrode is deposited flat on the drain region 12' with a predetermined thickness. It is sectional drawing of the state which formed the pattern.

제2도는 제1도에 이어서 전하보존 전극용 1차 전도물질(8) 상부에 캐패시터 산화막(7)을 ONO층(Oxide-Nitride-Oxide)으로 형성하고, VCC/2 전극용 전도물질(6)을 침착하고 패턴을 형성한다음 식각하고, 그 상부에 절연물질 LTO 산화막(5)을 형성하고 소오스영역(12)상의 일정부분 제거하여 비트선용 전도물질(4)을 침착시켜 접속한 후 그 상부에 절연물질의 LTO 산화막(3)을 형성하고 금속배선(2)을 형성한 다음 보호층(1)을 형성시킨 상태의 단면도로써, 반도체 기억장치는 MOSFET의 드레인 전극에 적층캐패시터를 형성한 것을 나타낸다.FIG. 2 is a capacitor oxide film 7 formed of an ONO layer (Oxide-Nitride-Oxide) on top of the primary conductive material 8 for the charge preserving electrode, followed by FIG. 1, and the conductive material 6 for the VCC / 2 electrode. Is deposited, a pattern is formed and then etched, and an insulating material LTO oxide film 5 is formed thereon, and a portion of the source region 12 is removed to deposit and connect the bit line conductive material 4 thereon. A cross-sectional view of a state in which the LTO oxide film 3 of the insulating material is formed, the metal wiring 2 is formed, and the protective layer 1 is formed. The semiconductor memory device shows that a stacked capacitor is formed at the drain electrode of the MOSFET.

제3도 내지 제4도는 본 발명의 요지를 나타낸 도면으로, 제3도는 종래의 방법(제1도)와 같이 실리콘기판(1) 상부에 게이트 전극을 형성한다음 기판(1)내에 소오스 및 드레인영역(12 및 12′을 형성한다음 게이트 전극 상부에 LTO 산화막(9) 및 전하보존 전극용 1차 전도물질(8)을 침착하고 패턴을 형성한 후 일정 부분 건식식각하고 전하보존 전극용 2차 전도물질(8′)을 전영역 상부에 침착한 후, 전하보존 전극용 1차 전도물질(8) 상부의 일정면적에만 2차 전도물질(8′)이 남도록 패턴을 형성한 후, 건식식각방법으로 식각한 상태의 단면도로써, 전하보존 전극용 1차 전도물질(8)의 두께는 종래와 같이 약 2000-3000Å정도이며 전하보존 전극용 2차 전도물질(8′)의 두께는 역시 2000-3000Å정도이다.3 to 4 show the gist of the present invention. FIG. 3 shows the gate electrode formed on the silicon substrate 1 as in the conventional method (FIG. 1), and then the source and drain in the substrate 1. After forming the regions 12 and 12 ', the LTO oxide layer 9 and the primary conductive material 8 for the charge storage electrode 8 are deposited on the gate electrode, and a pattern is formed. After the conductive material 8 'is deposited on the entire region, the pattern is formed such that the secondary conductive material 8' remains only in a predetermined area on the upper portion of the primary conductive material 8 for the charge storage electrode. The thickness of the primary conductive material 8 for the charge storage electrode is about 2000-3000 kPa as in the prior art, and the thickness of the secondary conductive material 8 'for the charge storage electrode 8 is also 2000-3000 kPa. It is enough.

또한, 전하보존 전극용 2차 전도물질(8′)의 4면 가장자리의 일부가 식각됨으로서, 후공정으로 형성될 비트선용 전도물질(4)이 소오스 영역(12)에 접속되는 공정에 지장을 주지 않게 된다.In addition, a portion of the four-sided edge of the secondary conductive material 8 'for the charge storage electrode is etched, thereby preventing a process of connecting the bit line conductive material 4 to the source region 12 to be formed later. Will not.

제4도는 상기의 전하보존 전극용 2차 전도물질(8′) 및 1차 전도물질(8)의 상부 및 측면에 캐패시터 산화막(7)을 일정두께로 형성하고 그 상부 및 측면에 VCC/2 전극용 전도물질(6)을 형성하고 적층캐패시터를 형성하며, 그 상부에 순차적으로 LTO 산화막(5), 비트선용 전도물질(4), LTO 산화막(3), 금속배선(2) 및 보호층으로 형성시킨 반도체 기억장치의 최종단면도이다.4 shows a capacitor oxide film 7 formed on the upper and side surfaces of the secondary conductive material 8 'and the primary conductive material 8 for the charge storage electrode to a predetermined thickness, and the VCC / 2 electrode on the upper and side surfaces thereof. Forming a conductive capacitor (6) and forming a stacked capacitor, and sequentially formed on top of each other, an LTO oxide film (5), a bit line conductive material (4), an LTO oxide film (3), a metal wiring (2), and a protective layer. The final cross section of the semiconductor memory device is shown.

상기와 같은 적층캐패시터 용량을 식으로 나타내면,If the capacity of the multilayer capacitor as described above is expressed by the formula,

이다.to be.

C=캐패시터 용량, d=전극간 거리, e : 유전율, S : 캐패시터 전극면적C = capacitor capacity, d = distance between electrodes, e: dielectric constant, S: capacitor electrode area

따라서, 본 발명과 같이 적층캐패시터가 형성될 면적이 제한되어 있는 경우, 캐패시터 전극의 표면적을 넓혀서 용량을 증대시킬 수 있기 때문에 반도체 기억장치를 고집적화 하는 경우에 발생하는 용량이 감소되는 문제점을 해결할 수 있는 효과가 있다.Therefore, when the area in which the stacked capacitors are to be formed is limited, as in the present invention, the capacity can be increased by increasing the surface area of the capacitor electrodes, which can solve the problem of reduced capacity generated when the semiconductor memory device is highly integrated. It works.

Claims

A method of manufacturing a stacked capacitor connected to a MOSFET of a highly integrated semiconductor device, wherein a gate electrode, a source and a drain electrode of a MOSFET structure are formed on a silicon substrate, a stacked capacitor connected to the drain electrode is formed, and a bit connected to the source. In the method of manufacturing a semiconductor memory device, which is formed in the order of a line, an insulating layer, a metal wiring, and a protective layer, a process for forming a multilayer capacitor includes forming a primary conductive material for a charge storage electrode in a predetermined thickness on a drain region. Forming a second pattern and etching the second conductive material for the charge storage electrode to a predetermined thickness to etch the secondary conductive material to be smaller than the upper area of the primary conductive material; Forming a capacitor oxide film (ONO) on the side and depositing a conductive material for the VCC / 2 electrode on the capacitor oxide film and on the side Method of manufacturing a semiconductor memory device, comprising a step of increasing the surface area of the emitter electrode.

In a highly integrated semiconductor device in which each gate, source, and drain electrode of a MOSFET is formed on a silicon substrate, a stacked capacitor is formed on the drain region and connected to the MOSFET, and an oxide film of an insulating material and a bit line conductive connected to the source electrode are formed thereon. In a semiconductor memory device comprising a material, an LTO oxide film of an insulating material, a metal wiring, and a protective layer, the structure of the multilayer capacitor is formed by charge retention in which the center lower portion is connected to the drain region while being spaced apart from a predetermined portion of the upper gate electrode. Capacitor formed on the upper surface of the primary conductive material for the electrode to have a predetermined thickness smaller than the area of the primary conductive material and to surround the upper and side surfaces of the primary and secondary conductive materials for the charge storage electrode with a predetermined thickness The conductive material for the VCC / 2 electrode is formed to a certain thickness on the upper side and the side of the oxide film to provide the surface of the capacitor electrode. A semiconductor memory device, characterized in that with a capacitor of a laminated structure against that.