KR940005890B1 - Field effect transistor and fabricating method thereof - Google Patents

Abstract

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Description

Field effect transistor and its manufacturing method

1 is a cross-sectional structure diagram of a memo cell array portion of a DRAM showing an embodiment of the present invention.

2A to 2D are cross-sectional structural views for explaining the manufacturing process of the memory cell portion shown in FIG.

3 is a cross-sectional structure diagram of a memory cell array portion of a DRAM showing a second embodiment of the present invention.

4 shows a third embodiment of the invention,

5 is a cross-sectional structure diagram of a parallel transistor showing a fourth embodiment of the present invention.

6 is a cross-sectional structure diagram showing a conventional DRAM and a memory cell unit.

7A to 7D are cross-sectional structural views for explaining the manufacturing process of the memory cell portion of the DRAM shown in FIG.

* Explanation of symbols for main parts of the drawings

1: p-type silicon substrate 3: transfer gate transistor

4b, 4c, 4c, and 4e: gate electrode 6: source and drain regions

10: Capacitor 11a: Base portion

15: bit line 20a, 20b: sidewall

21a, 21b: sidewall 42a, 42a: sidewall

(In each case, the same symbols indicate the same or equivalent parts.)

The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a field effect transistor and a method of manufacturing the same applied to a DRAM. BACKGROUND ART A DRAM using a MOS transistor is known as a device for storing and recording conventional information.

6 is a cross-sectional structure showing a memory cell portion of a conventional DRAM. 6, a source drain region 6 is formed on the P-type silicon substrate 1 at a predetermined interval. Gate electrodes 4b and 4c are formed between the pair of source drain regions 6 with the gate oxide film 5 interposed therebetween. An insulating oxide film 200 is formed on the upper portion of the gate electrodes 4b and 4c, and sidewalls 200a and 200b are formed on the sidewalls thereof. The bit line 150 is connected to the source / drain region 6 formed between the gates 4b and 4c, and the insulating oxide film 210 and the sidewalls 210a and 210b are formed on the upper and sidewall portions of the bit line 150. ) Is formed.

The other source drain region 6 is connected with a base portion 11a constituting the lower electrode of the capacitor which accumulates electric charges, and the side wall 200a is formed between the base portion 11a and the gate electrode 4b. ) And the insulating oxide film 200.

That is, the bottom end of the sidewall 210a formed on the sidewall portion of the bit line 150 is positioned on the gate electrode 4b and is formed at the junction region between the sidewall 210a and the insulating oxide film 200. The height of a) becomes a little low.

This is due to the manufacturing process as described later. Thus, in the conventional memory cell portion, the insulating oxide film 20 on the gate electrode 4b has a thick and thin portion and has a step shape at the boundary portion thereof.

7A to 7D are cross-sectional structural views for explaining the manufacturing process of the memory cell portion of the conventional DRAM shown in FIG.

A manufacturing process will be described with reference to FIGS. 6 through 7D. First, as shown in FIG. 7A, gate electrodes 4b and 4c are formed on the P-string silicon substrate 1 at a predetermined interval with the gate oxide film 5 interposed therebetween. An insulating oxide film 200 is formed to cover the gate electrodes 4b and 4c. Next, the source and drain regions 6 are formed, and the side walls 200a and 200b are formed so as to cover the side surfaces of the gate electrodes 4b and 4c and the insulating oxide film 200. Next, as shown in FIG. 7B, the bit line 150 is formed so as to be connected to the source drain region 6 formed on the P-type silicon substrate 1 between the gate electrodes 4b and 4c.

Here, the sidewalls 200b and the insulating oxide film 200 are interposed between the gate electrodes 4b and 4c and the bit lines 150 to form a dielectric breakdown voltage. An insulating oxide film 210 is formed on the bit line 150.

An oxide film 30 is formed on the entire surface as shown in FIG. 7C. As shown in FIG. 7D, the sidewall 210a is formed by anisotropically etching the oxide film 30. In this case, when the sidewall 210a is formed, a part of the insulating oxide film 200 formed on the gate electrodes 4b and 4c is overetched, and the thickness of a part of the insulating oxide film 200 due to the overetching becomes thin. Condition does not occur.

In this state, as shown in FIG. 6, the base portion is connected to the source / drain region 6 so as to be in contact with the sidewall 200a, the insulating oxide film 200, the sidewall 210a, and the insulating oxide film 210. As shown in FIG. When the 11a is formed, in the overetched portion of the oxide film 200 on the gate electrode 4b, the thickness of the insulating oxide film 200 interposed between the base portion 11a and the gate electrode 4b is made thin. It becomes the shape to become.

In addition, when a part of the insulating oxide film 200 is overetched by the overetching in the shape of the sidewall 210a and the thickness of the part becomes thin, the portion of the insulating oxide film 200 becomes thinner than the other part. At the boundary, an etch occurs.

As described above, when the sidewall 210a for forming the insulation breakdown voltage between the bit line 150 and the base portion 11a constituting the lower electrode of the capacitor is formed in the memory cell of the conventional DRAM, Since the insulating oxide film 200 on 4b) is overetched, the overetched portion of the insulating oxide film 200 becomes thinner and thinner, and the boundary area between the original and the thinned portion and the thinned portion It was in the shape which an etching part produces.

In such a shape, there is a problem that the breakdown voltage performance between the base portion 11a and the gate electrode 4b is deteriorated, and again, electric field concentration occurs in the etching portion.

In other words, when the semiconductor device is integrated in the related art, when the semiconductor device has a multilayered wiring structure, the thickness of the insulating layer interposed between the multilayered wiring layers becomes thin and it is difficult to improve the insulation breakdown voltage.

This invention is made | formed in order to solve the above subjects, and an object of this invention is to provide the field effect transistor which can improve the insulation breakdown voltage between multilayer wiring layers, and its manufacturing method even if it is integrated.

The invention according to claim 1 is a gate electrode formed on a surface of a semiconductor substrate between a pair of impurity regions formed on a surface of a semiconductor substrate and a pair of impurity gaps interposed therebetween, and a first upper portion formed on the gate electrodes. A first insulating layer having a pair of first sidewall insulating films formed on both sides of the oxide film, the gate electrode, and the first upper oxide film, and connected to one impurity region and in contact with the side surface of one first sidewall insulating film; In addition, one end thereof is formed on one side of the conductive layer existing on the gate electrode with an insulating film interposed therebetween, the second upper oxide film and the conductive layer formed on the conductive layer, and the second upper oxide film. And a second insulating layer having a second sidewall insulating film located on the surface of the other first sidewall insulating film.

The invention according to claim 2 is a gate electrode formed between a pair of impurity regions and a pair of impurity regions formed on a surface of a semiconductor substrate with a gate oxide film interposed therebetween, and a first upper portion formed on the gate electrode. A first insulating layer having a pair of first sidewall insulating films formed on both sides of an oxide film, a gate electrode and a first upper oxide film, and connected to one impurity region and in contact with a side surface of one first sidewall insulating film; In addition, one end thereof extends with an insulating film interposed therebetween on the gate electrode, and includes a first upper conductive layer formed on the first conductive layer, a first upper conductive layer, a first conductive layer, and a second upper oxide layer. A second insulating layer formed on one side and having a second sidewall insulating film formed on one surface thereof and positioned on the surface of the other first sidewall insulating film; A second conductive layer connected to the other impurity region and formed in contact with the side surface of the other first sidewall insulating film and the side surface of the second sidewall insulating film and electrically insulated from the first conductive layer. do.

The invention according to claim 3 forms an electrode layer on a semiconductor substrate, and forms a first insulating layer comprising a first upper oxide film covering an upper portion of the electrode layer and a sidewall insulating film covering a side portion, and forming a first insulating layer. Forming an impurity region in a region adjacent to the sidewall insulating film, and forming a conductive layer and a second insulating layer on the upper surface of the semiconductor substrate and the first insulating layer so that the first insulating layer has an end surface on the top thereof. The step of patterning the semiconductor substrate, the step of forming the third insulating layer on the entire surface of the semiconductor substrate, and the third insulating layer are etched so that the conductive layer located on the upper surface of the first insulating layer is in contact with the side surface and the first sidewall insulating film And forming a second side wall insulating film such that the bottom end is positioned on the surface thereof.

[Action]

In the invention according to the first claim, a pair of impurity regions are formed on the surface of the semiconductor substrate, and a gate electrode is formed on the surface of the semiconductor substrate with the gate oxide film interposed therebetween so as to be located between the pair of impurity regions. An upper oxide film was formed, and a pair of first sidewall insulating films were formed on both sides of the gate electrode and the first upper oxide film, respectively, to form a first insulating layer and to be connected to one impurity region so that one first sidewall was formed. One side of the conductive layer and the second upper oxide film is formed by contacting the side surface of the insulating film, and having one end of the conductive layer extending over the gate electrode with the insulating film interposed therebetween, and forming a second upper oxide film on the conductive layer. The second sidewall insulating film is formed so that the bottom end thereof is positioned on the surface of the other first sidewall insulating film. When the conductive layer is formed with the upper oxide film interposed therebetween, the dielectric breakdown voltage between the electrode layer and the conductive layer is not lowered at the junction region between the lower surface side end of the second sidewall insulating film and the first upper oxide film as in the prior art.

In the invention according to the second claim, a pair of impurity regions are formed on a surface of the semiconductor substrate, a gate electrode is formed on the surface of the semiconductor substrate between the pair of impurity regions, and a gate electrode is formed, and the first upper oxide film on the gate electrode is formed. And a pair of first sidewall insulating films on both sides of the gate electrode and the first upper oxide film are formed to form a first insulating layer and to contact the side surface of one of the first sidewall insulating films in one impurity region and the one side thereof. A first conductive layer is formed so that an end thereof extends over the gate electrode with an insulating film interposed therebetween, and on one side of the second upper oxide film, the first conductive layer, and the second upper oxide film on the first conductive layer. The second sidewall insulating film is formed so that the lower surface side end thereof is located on the surface of the other first sidewall insulating film, and the second first sidewall is formed in the other impurity region. Since the sidewall insulating film is in contact with the side surface and the sidewall of the second sidewall insulating film, and a second conductive layer electrically insulated from the first conductive layer is formed, the lower surface side end of the second sidewall insulating film and the first upper oxide film The dielectric breakdown voltage between the electrode layer and the conductive layer does not decrease in the junction region.

In the invention according to the third claim, an electrode layer is formed on a semiconductor substrate, and a first conductive layer made of a first upper oxide film covering an upper portion of the electrode layer and a first sidewall insulating film covering a side portion is formed and the first conductive layer is formed. An impurity region is formed in a region adjacent to the sidewall insulating film of the semiconductor substrate, and a conductive layer and a second insulating layer are formed on the upper surface of the semiconductor substrate and the first insulating layer, and patterned into a shape having its end surface on top of the first insulating layer. And a third insulating layer is formed on the entire surface of the semiconductor substrate, and the third insulating layer is etched to contact the side of the conductive layer located on the upper surface of the first insulating layer and on the surface of the first sidewall insulating film. Since the second sidewall insulating film is formed so that the side ends are positioned, the first upper oxide film at the time of forming the second sidewall insulating film is eliminated so that the breakdown voltage does not decrease. All.

EXAMPLE

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described in detail based on drawing. 1 is a cross-sectional structure diagram of a memory cell array portion of a DRAM showing one embodiment of the present invention.

Referring to FIG. 1, a memory cell array portion of a DRAM is constituted by a transfer gate transistor 3 and a capacitor 10. As shown in FIG. The transfer gate transistor 3 is a surface of a P-type silicon substrate 1 positioned between a pair of source / drain regions 6 and a pair of source / drain regions 6 formed on the surface of the P-type silicon substrate 1. And gate electrodes 4b and 4c formed therebetween with the gate oxide film 5 interposed therebetween. The gate electrodes 4b and 4c are covered with the insulating oxide film 20 and the sidewalls 20a and 20b.

The capacitor 10 has a stacked structure of a lower electrode (storage node) 11, a dielectric layer 12, and an upper electrode (cell plate) 13. The lower electrode 11 extends in the vertical direction along the outermost circumference of the base portion 11a and the base portion 11a which are connected to the source / drain region 6 formed adjacent to the field oxide film 2, and the standing wall portion 11b. It consists of two parts. Since the erected wall portion 11B of the lower electrode 11 constitutes a capacitive portion both on the inner and outer sides, it is effective for securing a constant capacitance in the case of miniaturization. The bit line 15 is connected to the source / drain region 6 on one side of the transfer gate transistor 3. Gate electrodes 4b and 4c are formed on the field oxide film 2, and an insulating oxide film 20 is formed to cover the gate electrodes 4b and 4c. The interlayer insulating film 22 is formed on the upper electrode 13, and the wiring layer 18 is formed on the interlayer insulating film 22 at positions corresponding to the gate electrodes 4b, 4c, 4d, and 4e, respectively.

The feature of the present embodiment is a position where the sidewall 21a formed on the sidewall portion of the bit line 15 is in contact with the sidewall 20a formed on the sidewall portions of the gate electrodes 4b and 4c.

That is, in this embodiment, since the lower end of the side wall 21a formed on the sidewall portion of the bit line 15 is in contact with the sidewall 20a of the gate electrodes 4b and 4c unlike the prior art, Likewise, the thickness of the insulating oxide film 20 on the gate electrodes 4b and 4c is not thinned, and the insulation breakdown voltage between the base portion 11a and the gate electrodes 4b and 4c can be improved.

2A to 2D are cross-sectional structural diagrams for explaining the manufacturing process of the memory cell unit in the memory cell array unit shown in FIG. Next, the manufacturing process will be described with reference to FIGS. First, as shown in FIG. 2A, the gate electrodes 4b and 4c are formed with the gate oxide film 5 interposed therebetween at a predetermined interval on the P-type silicon engine 1.

An insulating oxide film 20 is formed to cover the gates 4b and 4c. Next, the source and drain regions 6 are formed, and the side walls 20a and 20b are formed so as to cover the side surfaces of the gate electrodes 4b and 4c and the insulating oxide film 20. Next, as shown in FIG. 2B, the bit line 15 is formed on the source / drain region 6 formed between the gate electrodes 4b and 4c, and the insulating oxide film 21 is formed on the bit line 15. As shown in FIG. do.

In this embodiment, the width W of the beak line 15 is formed wider than the width of the conventional bit line (see FIG. 6).

An oxide film 30 is formed on the entire surface as shown in FIG. 2C.

As shown in FIG. 2D, the sidewall 21a is formed by anisotropically etching the oxide film 30. The sidewall 21a can be formed such that the lower end of the sidewall 21a is in contact with the sidewall 20a of the gate electrodes 4b and 4c.

As a result, as shown in FIG. 1, even when the base portion 11a is formed on the source / drain region 6 so as to be in contact with the side walls 20a and 21a, the base portion 11a and the gate electrode 4b. And 4c), the insulation breakdown performance can be improved without the pressure of the film of the insulation layer interposed between 4c and 4c.

In addition, as in the prior art, the insulating oxide film 20 is overetched so that a part thereof becomes thin, and an unfavorable state in which electric field concentration occurs due to an etching portion between the thinned portion and the original portion does not occur.

3 is a cross-sectional structure diagram of a memory cell array portion of a DRAM showing a second embodiment of the present invention.

Referring to Fig. 3, the second embodiment differs from the first embodiment shown in Fig. 1 by the capacitor structure.

In other words, the capacitor 10 of the second embodiment is composed of a lower electrode formed from a base portion 11a formed to be connected to the source / drain region 6 and a erected wall portion 11b formed in a region sandwiched between the insulating film 26 thereon. 11) and the upper electrode 13 formed on the dielectric layer 12 formed to cover the lower electrode 11. An oxide film 24 is formed on the insulating oxide film 21 and the field oxide film 2 on the bit line 15, and an insulating layer 25 is formed on the oxide film 24.

In addition, the width of the bit line 15 is formed to be wide as in the first embodiment shown in the twelfth, and sidewalls 21a are formed in the sidewalls thereof. The lower end of the sidewall 21a is formed in contact with the upper end surface of the sidewall 20a of the gate electrodes 4b and 4c as in the first embodiment shown in FIG.

By such a configuration, the same effects as in the first embodiment shown in FIG. 1 can be obtained. That is, the insulation breakdown performance of the base portion 11a and the gate electrodes 4b and 4c constituting the lower electrode 11 of the capacitor can be improved.

4 is a cross-sectional structure diagram of a two-gate FET showing the third embodiment of the present invention. Referring to FIG. 4, a pair of source / drain regions 6 are formed on the P-type silicon substrate 1. On the source / drain region 6, the wiring layer 48 is formed with the contact layer 47 interposed therebetween.

Two gate electrodes 44b and 44c are formed between the pair of source / drain regions 6, and the gate electrode 44c has the gate electrode 44b with the insulating oxide film 42 and the sidewall 42b interposed therebetween. It is built on the structure. An insulating oxide film 43 is formed on the gate electrode 44c, and sidewalls 43a and 43b are formed on the sidewall thereof. An interlayer insulating film 45 is formed to cover the entire surface.

Here, the present embodiment is characterized in that the lower side of the side wall 43a of the gate electrode 44c is in contact with the upper end surface of the side wall 42a of the gate electrode 44b.

5 is a cross-sectional structure diagram of a parallel transistor showing the fourth embodiment of the present invention.

Referring to FIG. 5, a source / drain region 6 is formed on the P-type silicon substrate 1 at predetermined intervals, and the gate electrode is interposed between the source and drain regions 6 with an insulating oxide film 5 therebetween. (4b, 4c) are formed. The wiring layer 55 is formed on the source / drain region 6 sandwiched between the gate electrodes 4b and 4c. The insulating oxide film 21 and the side walls 21a and 21b are formed on the wiring layer 55.

The wiring layer 53 is formed on the source / drain region 6 with the contact layer 52 interposed therebetween, and the portions other than the contact layer 52 are formed are covered with the interlayer insulating film 51.

As a feature point in this fourth embodiment, the position where one end of the lower side of the sidewall 21a formed on both sides of the wiring layer 55 is in contact with the insulating layer covering the gate electrodes 4b and 4c is the sidewall 20a. It is called the upper end of. As described above, the sidewall structure of the present invention can be applied to various semiconductor devices, and the manufacturing process of the first embodiment shown in FIG. 1 is shown in FIGS. 2A to 2D, but the manufacturing process of the present invention is limited thereto. For example, when the width of the bit line 1 is the same as the conventional length, and the side wall 21a is formed on the side surface thereof, the oxide film 30 is thickened to increase the thickness of the side wall 21a. In the same manner, the bit line 15 can be formed in the same shape, and the width of the bit line 15 can be increased, and the thickness of the oxide film 30 when the sidewall 21a is formed can be thickened. The same sidewall 21a can be formed.

According to the invention described in the first claim, a semiconductor substrate is formed by forming a first insulating layer having a first upper oxide film on the gate electrode and a pair of first sidewall insulating films on both sides of the gate electrode and the first upper oxide film. A conductive layer is formed so as to be in contact with the side surface of one of the first sidewall insulating films on one side of the pair of impurity regions formed on the surface of the substrate, and one end thereof extends with an insulating film interposed therebetween on the gate electrode. A second insulating layer having a second upper oxide film, a conductive layer, and a second sidewall insulating film on one surface of the second upper oxide film, the second sidewall insulating film being positioned on the surface of the other first sidewall insulating film; When the conductive layer is formed on the electrode layer with the first upper oxide film interposed therebetween, the lower surface side end of the second sidewall insulating film and the first upper oxide film In the joint region even when the thing the withstand voltage between the electrode layer and the conductive layer is lowered because integration was able to do this provides a field effect transistor capable of improving the withstand voltage of the multi-layer wiring layer.

According to the invention as set forth in the second claim, a first insulating layer having a first upper oxide film on the gate electrode and a pair of first sidewall insulating films on both sides of the gate electrode and the first upper oxide film is formed to form a semiconductor substrate. On the one side of the pair of impurity regions formed on the surface, a first conductive layer is formed so as to be in contact with the side surface of one of the first sidewall insulating films and one end thereof extends with an insulating film interposed therebetween on the gate electrode. A second upper oxide film on the conductive layer and a second sidewall insulating film positioned on the surface of the first sidewall insulating film on the other side of the lower surface side of one side of the first conductive layer and the second upper oxide film; A second insulating layer is formed and in contact with the side of the first sidewall insulating film and the side of the second sidewall insulating film in the other impurity region and electrically connected with the first conductive layer. By forming an insulated second conductive layer, the dielectric breakdown voltage between the electrode layer and the conductive layer is not lowered at the junction area between the lower surface side end of the second sidewall insulating film and the first upper oxide film as in the prior art. In addition, it is possible to provide a field effect transistor capable of improving the insulation breakdown voltage between different wiring layers.

According to the invention as set forth in the third claim, an electrode layer is formed on a semiconductor substrate, and a first insulating layer comprising a first upper oxide film covering an upper portion of the electrode layer and a first sidewall insulating film covering a side portion thereof is formed. An impurity region is formed in a region adjacent to the first sidewall insulating film, and a conductive layer and a second insulating layer are formed on the upper surface of the semiconductor substrate and the first insulating layer, and have a side surface on the first insulating layer. By forming a third insulating layer on the entire surface of the semiconductor substrate and etching the third insulating layer on the surface of the first sidewall insulating film which is in contact with the side surface of the conductive layer located on the upper surface of the first insulating layer. By forming the second sidewall insulating film so that the lower side is positioned, the first upper oxide film is removed at the time of forming the second sidewall insulating film and the dielectric breakdown voltage is lowered. Even if there is no integration il it became days to provide a method of manufacturing a field effect transistor capable of improving the dielectric strength between the multi-layer wiring layer.

Claims (3)

A pair of impurity regions formed on the surface of the semiconductor substrate, a gate electrode formed between the pair of impurity regions, having a gate oxide film interposed therebetween on the surface of the semiconductor substrate, a first upper oxide film formed on the gate electrode and the gate A first insulating layer having an electrode and a pair of first sidewall insulating films formed on both side surfaces of the first upper sub-film, and a sidewall of the first sidewall insulating film connected to the one impurity region. In addition, one end thereof is formed on one side of the conductive layer formed on the gate electrode with the insulating film interposed therebetween, the second upper oxide film formed on the conductive layer, the conductive layer, and the second upper oxide film. Second insulation having a second sidewall insulating film having a side end positioned on a surface of the other first sidewall insulating film; And a field effect transistor comprising a. A pair of impurity regions formed on the surface of the semiconductor substrate, a gate electrode formed between the pair of impurity regions with a gate computerized film interposed therebetween, and a first upper oxide film formed on the gate electrode and the gate A first insulating layer having an electrode and a pair of first sidewall insulating films formed on both side surfaces of the first upper oxide film, and a first insulating layer connected to the one impurity region and in contact with a side surface of the first first sidewall insulating film. In addition, one end thereof has a first conductive layer extending over the gate electrode with an insulating film therebetween, a second upper oxide film formed on the first conductive layer, the first conductive layer, and the second conductive layer. A second sidewall insulating film formed on one side of the upper oxide film and having a bottom end thereof located on the surface of the other first sidewall insulating film. A second insulating layer having a film and a second sidewall insulating film connected to said other impurity region and being folded to be formed on the side surface of said other first sidewall insulating film and said sidewall of said second sidewall insulating film; And a second conductive layer electrically insulated from the conductive layer. Forming a first insulating layer on the semiconductor substrate, the first insulating layer comprising a first upper oxide film covering an upper portion of the electrode layer and a first sidewall insulating film covering a side portion, and adjacent to the first sidewall insulating film of the semiconductor substrate. Forming an impurity region in the region of the semiconductor substrate; and forming a conductive layer and a second insulating layer on the upper surface of the semiconductor substrate and the first insulating layer, and patterning the semiconductor layer to have an end surface on the first insulating layer. And forming a third insulating layer on the entire surface of the semiconductor substrate, and etching the third insulating layer so as to be in contact with a side surface of the conductive layer located on the upper surface of the first insulating layer. And forming a second sidewall insulating film on the surface of the first axial wall insulating film so that its lower end is positioned.

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