JPH0430465A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0430465A JPH0430465A JP2136486A JP13648690A JPH0430465A JP H0430465 A JPH0430465 A JP H0430465A JP 2136486 A JP2136486 A JP 2136486A JP 13648690 A JP13648690 A JP 13648690A JP H0430465 A JPH0430465 A JP H0430465A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- conductive layer
- insulating film
- layer
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に利用され、特に、半導体基板を覆
う層間絶縁膜上に形成された配線同士をコンタクトホー
ルを介して接続する構成の半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to semiconductor devices, and in particular, to semiconductor devices having a structure in which interconnections formed on an interlayer insulating film covering a semiconductor substrate are connected to each other via contact holes. Regarding equipment.
本発明は、三層以上の導電層を有し、各導電層に対する
コンタクトホールが設けられた半導体装置において、
最上層の導電層のコンタクトホールが形成された下方に
、電気的に浮遊状態である例えば多結晶シリコン層から
構成された補助的導電層を設けることにより、
金属配線と半導体基板との短絡を防止したものである。The present invention provides a semiconductor device having three or more conductive layers and contact holes for each conductive layer, in which an electrically floating state is provided below where the contact hole is formed in the uppermost conductive layer. For example, by providing an auxiliary conductive layer made of a polycrystalline silicon layer, short circuits between the metal wiring and the semiconductor substrate are prevented.
第４図は従来例の要部を示す縦断面図で、スタック容量
型ＤＲＡＭを示す。FIG. 4 is a vertical sectional view showing the main parts of a conventional example, showing a stacked capacitance type DRAM.
第４図において、１はシリコン基板、２はフィ−ルド酸
化膜、３はゲート酸化膜、４はゲート多結晶シリコン層
、５はＭＯＳ）ランジスタのソースまたはドレイン領域
となる不純物拡散層、６および１０は層間絶縁膜、７は
容量蓄積電極、８は容量絶縁膜、９はセルプレート、１
１は金属配線、ならびに１２〜１５はコンタクトホール
である。In FIG. 4, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate polycrystalline silicon layer, 5 is an impurity diffusion layer that becomes a source or drain region of a MOS transistor, 6 and 10 is an interlayer insulating film, 7 is a capacitive storage electrode, 8 is a capacitive insulating film, 9 is a cell plate, 1
1 is a metal wiring, and 12 to 15 are contact holes.
ここで、金属配線１１は、不純物拡散層５と、ゲート多
結晶シリコン層４と、フィールド酸化膜２上にわたって
形成されたセルプレート９とに対して、同時に層間絶縁
膜１０に開孔されたコンタクトホール１２を介して接続
される。Here, the metal wiring 11 is a contact that is simultaneously opened in the interlayer insulating film 10 to the impurity diffusion layer 5, the gate polycrystalline silicon layer 4, and the cell plate 9 formed over the field oxide film 2. It is connected via the hole 12.
このように、複数の導電層間を同時に開孔するようなコ
ンタクトホールを形成する場合、層間絶縁膜の厚い部分
と薄い部分とが混在するために、コンタクトホールのエ
ツチング時間は層間絶縁膜の厚い部分にあわせて決定さ
れる。この場合、層間絶縁膜の膜厚差が極端に異なると
、例えば、金属配線１１とセルプレート９間を接続する
コンタクトホール１２を、金属配線１１と不純物拡散層
５とを接続するコンタクトホール１３および１４ならび
に金属配線１１とゲート多結晶シリコン層４とを接続す
るコンタクトホール１５とを同時にあける場合、コンタ
クトホール１３．１４および１５に比べてコンタクトホ
ール１２の深さが浅いので、セルプレート９は過大な時
間エツチング雰囲気にさらされることにより、セルプレ
ート９自身がエツチングされ、最後には、コンタクトホ
ール１２の部分を拡大した第５図に示すように、コンタ
クトホール１２がフィールド酸化膜２を突き抜けてしま
い、後に金属配線１１を形成した場合、金属配線１１と
シリコン基板１とが電気的に短絡してしまう欠点があっ
た。In this way, when forming a contact hole that simultaneously opens between multiple conductive layers, the etching time for the contact hole is longer than the etching time for the thicker part of the interlayer insulating film because the thicker and thinner parts of the interlayer insulating film coexist. It will be decided according to the In this case, if the interlayer insulating film has an extremely different thickness, for example, the contact hole 12 connecting the metal wiring 11 and the cell plate 9 may be replaced with the contact hole 13 connecting the metal wiring 11 and the impurity diffusion layer 5. 14 and the contact hole 15 connecting the metal wiring 11 and the gate polycrystalline silicon layer 4, the contact hole 12 is shallower than the contact holes 13, 14 and 15, so the cell plate 9 is too large. By being exposed to the etching atmosphere for a long time, the cell plate 9 itself is etched, and eventually the contact hole 12 penetrates through the field oxide film 2, as shown in FIG. 5, which is an enlarged view of the contact hole 12. However, when the metal wiring 11 is formed later, there is a drawback that the metal wiring 11 and the silicon substrate 1 are electrically short-circuited.
本発明の目的は、前記の欠点を除去することにより、複
数の導電層間に同時にコンタクトホールを形成しても、
金属配線と半導体基板とが短絡することのない半導体装
置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks, thereby making it possible to form contact holes between multiple conductive layers at the same time.
An object of the present invention is to provide a semiconductor device in which a metal wiring and a semiconductor substrate are not short-circuited.
本発明は、半導体基板の一主面に形成された三層以上の
導電層と、前記三層以上の導電層を覆うて形成された層
間絶縁膜と、前記層絶縁膜を貫通してそれぞれ前記導電
層に到達して形成された少なくとも３個のコンタクトホ
ールとを備えた半導体装置において、前記導電層のうち
最上層の導電層のコンタクトホールが形成された下方に
設けられ、電気的に浮遊状態に保持された補助的導電層
を備えたことを特徴とする。The present invention provides three or more conductive layers formed on one principal surface of a semiconductor substrate, an interlayer insulating film formed to cover the three or more conductive layers, and an interlayer insulating film that penetrates through the layer insulating film. In a semiconductor device having at least three contact holes formed by reaching a conductive layer, the conductive layer is provided below the contact hole in the uppermost conductive layer of the conductive layer, and is in an electrically floating state. characterized by comprising an auxiliary conductive layer held in place.
また、本発明は、前記補助的導電層は多結晶シリコン層
から構成とすることができる。Further, in the present invention, the auxiliary conductive layer may be composed of a polycrystalline silicon layer.
最上層の導電層の下郎には、例えば多結晶シリコン層か
ら構成され、電気的に浮遊（フローティング）状態に保
持された補助的導電層が設けられているので、コンタク
トホール形成時に、例え当該導電層がエツチングにより
なくなったにしても、補助的導電層に遮られて半導体基
板に達することはない。An auxiliary conductive layer made of, for example, a polycrystalline silicon layer and held in an electrically floating state is provided below the uppermost conductive layer. Even if the layer is etched away, it is not blocked by the auxiliary conductive layer and does not reach the semiconductor substrate.
従って、金属配線と半導体基板との短絡を防止すること
が可能となる。しかも、補助的導電層は電気的に浮遊状
態に保持されているので、装置の特性に影響を及ぼすこ
ともない。Therefore, it is possible to prevent short circuits between the metal wiring and the semiconductor substrate. Moreover, since the auxiliary conductive layer is held in an electrically floating state, it does not affect the characteristics of the device.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の第一実施例の要部を示す縦断面図で、
スタック容量型ＤＲＡＭを示す。また、第２図（ａ）お
よび（ｂ）は第１図のコンタクトホール１２部分の詳細
を示す平面図およびそのＡ−Ａ’断面図である。FIG. 1 is a longitudinal sectional view showing the main parts of the first embodiment of the present invention.
A stacked capacity DRAM is shown. 2(a) and 2(b) are a plan view showing details of the contact hole 12 portion of FIG. 1 and a cross-sectional view thereof taken along the line AA'.
本第−実施例は、半導体基板としてのシリコン基板１の
一主面上に形成された、三層の導電層としての、不純物
拡散層５、ゲート多結晶シリコン層４およびセルプレー
ト９と、これらを覆うて形成された層間絶縁膜６および
１０と、この層間絶縁膜６および１０または１０を貫通
して、不純物拡散層５およびゲート多結晶シリコン層４
、またはセルプレート９に到達して形成されたコンタク
トホール１３．１４および１５、ならびに１２とを備え
た半導体装置において、
本発明の特徴とするところの、
最上層の導電層であるところのセルプレート９のコンタ
クトホール１２が形成された下方に、層間絶縁膜６と容
量絶縁膜８とで囲んで、電気的に浮遊状態に保持した補
助導電層としての多結晶シリコンからなる容量蓄積電極
７ａを備えている。The present embodiment includes an impurity diffusion layer 5, a gate polycrystalline silicon layer 4, and a cell plate 9 as three conductive layers formed on one main surface of a silicon substrate 1 as a semiconductor substrate. The impurity diffusion layer 5 and the gate polycrystalline silicon layer 4 are formed by penetrating the interlayer insulating films 6 and 10 or 10.
, or contact holes 13, 14 and 15, and 12 formed by reaching the cell plate 9. A feature of the present invention is that the cell plate is the uppermost conductive layer. A capacitor storage electrode 7a made of polycrystalline silicon as an auxiliary conductive layer is surrounded by an interlayer insulating film 6 and a capacitor insulating film 8 and held in an electrically floating state below the contact hole 12 of No. 9. ing.
なお、第１図において、２はフィールド酸化膜、３はゲ
ート酸化膜、７は多結晶シリコンからなる容量蓄積電極
、および１１は金属配線である。In FIG. 1, 2 is a field oxide film, 3 is a gate oxide film, 7 is a capacitor storage electrode made of polycrystalline silicon, and 11 is a metal wiring.
本第二実施例によれば、第２図（ａ）および（ｂ）に示
すように、例えば１５０ＯＡの多結晶シリコン層で形成
されたセルプレート９が、コンタクトホール１２を形成
する際の過大なエツチングによりエツチングされ、最終
的にコンタクトホール１２がセルプレート９を突き抜け
ても、下層に例えば５０〜２００人の容量絶縁膜８を介
して３０００〜４０００ Ａの多結晶シリコン層で形成
された容量蓄積電極７ａがあるので、コンタクトホール
１２がシリコン基板１まで達することを防ぐことができ
る。According to the second embodiment, as shown in FIGS. 2(a) and 2(b), the cell plate 9 formed of, for example, a 150 OA polycrystalline silicon layer is Even if the contact hole 12 is etched and finally penetrates through the cell plate 9, the capacitance storage is formed by a polycrystalline silicon layer of 3000 to 4000 A with a capacitance insulating film 8 of 50 to 200 amps in the lower layer. The presence of the electrode 7a can prevent the contact hole 12 from reaching the silicon substrate 1.
第３図（ａ）およびら）は本発明第二実施例のコンタク
トホール部分の詳細を示す平面図およびそのＢＢ′断面
図である。FIGS. 3(a) and 3(a) are a plan view showing details of a contact hole portion of a second embodiment of the present invention and a sectional view taken along line BB' thereof.
本第二実施例は、第一実施例と同様に、本発明の特徴と
するところの、金属配線１１とセルプレート９とを接続
するコンタクトホール１２を開孔する領域のセルプレー
ト９とを接続するコンタクトホール１２を開孔する領域
のセルプレート９の下方に、フィールド酸化膜２と層間
絶縁膜６とで囲んで、電気的に浮遊状態のゲート多結晶
シリコン層４ａを設けたものである。The second embodiment, like the first embodiment, connects the cell plate 9 in the region where the contact hole 12 connecting the metal wiring 11 and the cell plate 9 is formed, which is a feature of the present invention. An electrically floating gate polycrystalline silicon layer 4a is provided below the cell plate 9 in the area where the contact hole 12 is to be formed, surrounded by the field oxide film 2 and the interlayer insulating film 6.
本第二実施例では、セルプレート９とゲート多結晶シリ
コン層４ａとの間に、層間絶縁膜６として例えば２００
０〜５０００ Ａのシリコン酸化膜あるいはＢＰＳＧ膜
を有し、さらに、例えば３０００〜４０００ Ａのゲー
ト多結晶シリコン層４ａを有するために、コンタクト形
成時の過大なエツチングにより金属配線１１とシリコン
基板１が電気的に短絡することを防止できる。In the second embodiment, the interlayer insulating film 6 is formed between the cell plate 9 and the gate polycrystalline silicon layer 4a.
Since it has a silicon oxide film or a BPSG film with a thickness of 0 to 5000 A, and further has a gate polycrystalline silicon layer 4a with a thickness of, for example, 3000 to 4000 A, the metal wiring 11 and the silicon substrate 1 may be damaged due to excessive etching during contact formation. Electrical short circuits can be prevented.
また、本第二実施例では、セルプレート９とゲート多結
晶シリコン層４ａの間に２０００〜５０００ Ａのシリ
コン酸化膜あるいはＢＰＳＧ膜からなる層間絶縁膜６を
有するので、第一実施例に比べてさらに長い時間の過大
なエツチングに耐えることができる。In addition, in the second embodiment, since the interlayer insulating film 6 made of a silicon oxide film or BPSG film of 2000 to 5000 A is provided between the cell plate 9 and the gate polycrystalline silicon layer 4a, compared to the first embodiment, Furthermore, it can withstand excessive etching for a long time.
以上説明したように、本発明は、コンタクトホールを開
孔する部分の最上層の導電層直下に、補助導電層として
、電気的に浮遊状態の例えば多結晶シリコン層を設ける
ことにより、コンタクトホール形成時の過大なエツチン
グにより金属配線とシリコン基板とが電気的に短絡する
ことを防止できる効果がある。As explained above, the present invention enables contact hole formation by providing an electrically floating state, for example, a polycrystalline silicon layer, as an auxiliary conductive layer directly under the uppermost conductive layer in the area where the contact hole is to be opened. This has the effect of preventing electrical short-circuits between the metal wiring and the silicon substrate due to excessive etching at the time of etching.
第１図は本発明の第一実施例の要部を示す縦断面図。
第２図（ａ）はそのコンタクトホール部分の詳細を示す
平面図。
第２図ら）は第２図（ａ）のＡ−Ａ’断面図。
第３図（ａ）は本発明第二実施例のコンタクトホール部
分の詳細を示す平面図。
第３図ら）は第３図（ａ）のＢ−Ｂ’断面図。
第４図は従来例の要部を示す縦断面図。
第５図（ａ）はそのコンタクトホール部分の詳細を示す
平面図。
第５図ら）は第５図（ａ）のｃ−ｃ’断面図。
１・・・シリコン基板、２・・・フィールド酸化膜、３
・・・ゲート酸化膜、４．４ａ・・・ゲート多結晶シリ
コン層、５・・・不純物拡散層、６．１０・・・層間絶
縁膜、７．７ａ・・・容量蓄積電極、８−・・容量絶縁
膜、９・・セルプレート、１１・・・金属配線、１２〜
１５・・・コンタクトホール。FIG. 1 is a longitudinal sectional view showing the main parts of a first embodiment of the present invention. FIG. 2(a) is a plan view showing details of the contact hole portion. FIG. 2(a) is a sectional view taken along the line AA' in FIG. 2(a). FIG. 3(a) is a plan view showing details of the contact hole portion of the second embodiment of the present invention. FIG. 3(a) is a sectional view taken along line BB' in FIG. 3(a). FIG. 4 is a longitudinal sectional view showing the main parts of a conventional example. FIG. 5(a) is a plan view showing details of the contact hole portion. FIG. 5(a) is a sectional view taken along line cc' in FIG. 5(a). 1... Silicon substrate, 2... Field oxide film, 3
...Gate oxide film, 4.4a...Gate polycrystalline silicon layer, 5...Impurity diffusion layer, 6.10...Interlayer insulating film, 7.7a...Capacitance storage electrode, 8-...・Capacitive insulating film, 9...Cell plate, 11...Metal wiring, 12~
15...Contact hole.
Claims (1)
と、 前記三層以上の導電層を覆うて形成された層間絶縁膜と
、 前記層絶縁膜を貫通してそれぞれ前記導電層に到達して
形成された少なくとも３個のコンタクトホールと を備えた半導体装置において、 前記導電層のうち最上層の導電層のコンタクトホールが
形成された下方に設けられ、電気的に浮遊状態に保持さ
れた補助的導電層 を備えたことを特徴とする半導体装置。 ２、前記補助的導電層は多結晶シリコン層から構成され
た請求項１記載の半導体装置。[Claims] 1. Three or more conductive layers formed on one principal surface of a semiconductor substrate, an interlayer insulating film formed to cover the three or more conductive layers, and an interlayer insulating film that penetrates the layer insulating film. and at least three contact holes formed in the uppermost conductive layer among the conductive layers, each contact hole being formed below the contact hole in the uppermost conductive layer and reaching the conductive layer. 1. A semiconductor device comprising an auxiliary conductive layer held in a floating state. 2. The semiconductor device according to claim 1, wherein said auxiliary conductive layer is comprised of a polycrystalline silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2136486A JP3049733B2 (en) | 1990-05-25 | 1990-05-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2136486A JP3049733B2 (en) | 1990-05-25 | 1990-05-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0430465A true JPH0430465A (en) | 1992-02-03 |
| JP3049733B2 JP3049733B2 (en) | 2000-06-05 |
Family
ID=15176270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2136486A Expired - Fee Related JP3049733B2 (en) | 1990-05-25 | 1990-05-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3049733B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237525A (en) * | 1995-01-31 | 2002-08-23 | Fujitsu Ltd | Semiconductor memory device and manufacturing method therefor |
| JP2005252279A (en) * | 2005-03-30 | 2005-09-15 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2008263211A (en) * | 1995-01-31 | 2008-10-30 | Fujitsu Ltd | Semiconductor device |
| US7649261B2 (en) | 1996-07-18 | 2010-01-19 | Fujitsu Microelectronics Limited | Highly integrated and reliable DRAM and its manufacture |
| JP2010050474A (en) * | 2009-10-20 | 2010-03-04 | Fujitsu Microelectronics Ltd | Semiconductor device, and method of manufacturing the same |
| US8404554B2 (en) | 1995-01-31 | 2013-03-26 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013202097A (en) * | 2012-03-27 | 2013-10-07 | Barcos Co Ltd | Bag |
-
1990
- 1990-05-25 JP JP2136486A patent/JP3049733B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237525A (en) * | 1995-01-31 | 2002-08-23 | Fujitsu Ltd | Semiconductor memory device and manufacturing method therefor |
| JP2008263211A (en) * | 1995-01-31 | 2008-10-30 | Fujitsu Ltd | Semiconductor device |
| US8404554B2 (en) | 1995-01-31 | 2013-03-26 | Fujitsu Semiconductor Limited | Method of manufacturing semiconductor device |
| US8674421B2 (en) | 1995-01-31 | 2014-03-18 | Fujitsu Semiconductor Limited | Semiconductor device |
| US7649261B2 (en) | 1996-07-18 | 2010-01-19 | Fujitsu Microelectronics Limited | Highly integrated and reliable DRAM and its manufacture |
| US8143723B2 (en) | 1996-07-18 | 2012-03-27 | Fujitsu Semiconductor Limited | Highly integrated and reliable DRAM and its manufacture |
| JP2005252279A (en) * | 2005-03-30 | 2005-09-15 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2010050474A (en) * | 2009-10-20 | 2010-03-04 | Fujitsu Microelectronics Ltd | Semiconductor device, and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3049733B2 (en) | 2000-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2682455B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| US5365095A (en) | Semiconductor memory device and process | |
| US6603203B2 (en) | Semiconductor device having capacitive element structure and multilevel interconnection structure and method of fabricating the same | |
| US6218197B1 (en) | Embedded LSI having a FeRAM section and a logic circuit section | |
| KR960005248B1 (en) | Semiconductor memory cell and the manufacture thereof | |
| US6562677B1 (en) | Capacitance element and method of manufacturing the same | |
| US6197675B1 (en) | Manufacturing method for semiconductor device having contact holes of different structure | |
| US6104053A (en) | Semiconductor device comprising capacitor in logic circuit area and method of fabricating the same | |
| JP2004022824A (en) | Semiconductor device and its manufacturing method | |
| JPH0430465A (en) | Semiconductor device | |
| US5068698A (en) | MOS semiconductor device having high-capacity stacked capacitor | |
| JPH09275193A (en) | Semiconductor storage device | |
| JPH10209394A (en) | Semiconductor storage device and its manufacture | |
| JP2809131B2 (en) | Method for manufacturing semiconductor device | |
| KR20000074908A (en) | Capacitor of semicon ductor device and method for fabricating the same | |
| JPS63211672A (en) | Semiconductor integrated circuit device | |
| JPH05243519A (en) | Semiconductor memory device | |
| JPH08236721A (en) | Semiconductor device and method of its fabrication | |
| JP2987882B2 (en) | Method for manufacturing semiconductor memory | |
| KR100237130B1 (en) | Semiconductor memory and method for manufacturing the same | |
| JP3398056B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR920000384B1 (en) | Semiconductor memory device and method of fabricating thereof | |
| KR100358164B1 (en) | Method for forming ferroelectric memory device | |
| JPH03145159A (en) | Semiconductor memory device and manufacture thereof | |
| KR910007114B1 (en) | Semiconductor memory device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080331 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090331 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100331 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |