KR20080015599A - Method for manufacturing in semiconductor device - Google Patents

Method for manufacturing in semiconductor device Download PDF

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KR20080015599A
KR20080015599A KR1020060077145A KR20060077145A KR20080015599A KR 20080015599 A KR20080015599 A KR 20080015599A KR 1020060077145 A KR1020060077145 A KR 1020060077145A KR 20060077145 A KR20060077145 A KR 20060077145A KR 20080015599 A KR20080015599 A KR 20080015599A
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manufacturing
semiconductor device
pattern
imd
contact hole
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KR100827485B1 (en
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김진엽
장정렬
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to improve RIE(Reactive Ion Etching) characteristic to remove pattern defect by forming a via hole for connecting to a cooper layer using a PR(Photo Resist) for a polymer. An isolation layer(212) is formed on a semiconductor substrate(211). Source/drain/gate are formed on an active region of the semiconductor substrate. A silicide(213) is formed on the source/drain/gate. A nitride silicon(SiN), FSG(214a,214b), and SiH4(215a,215b) are sequentially deposited on the silicide to form an IMD(Inter-Metal Dielectric). A trench and a via hole are formed on the IMD. A metal barrier(216) and a tungsten(W)(217) are gap-filled in the via hole. A metal barrier(218) is formed on the trench on an upper portion of the via hole. A cooper layer(219) is gap-filled in the metal barrier. A nitride silicon(SiN)(220) is formed on the whole exposed surface with a thickness of 5 to 10 Å. FSG(214c) and SiH4(215c) are sequentially deposited on the nitride silicon(SiN). A selective dual damascene RIE(Reactive Ion Etching) is performed on the trench and a contact hole region for connecting the cooper layer using a PR(Photo Resist)(221) for a polymer as a pattern on the deposited SiH4.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}Method of manufacturing a semiconductor device {METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}

도 1a 내지 도 1b는 종래 반도체 소자의 제조 과정을 도시한 도면,1A to 1B illustrate a manufacturing process of a conventional semiconductor device;

도 2a 내지 도 2d는 본 발명의 일 실시 예에 따른 반도체 소자의 제조 과정을 도시한 도면, 2A to 2D are views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention;

도 3a 내지 도 3d는 본 발명의 다른 실시 예에 따른 반도체 소자의 제조 과정을 도시한 도면.3A to 3D are views illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 폴리머(Polymer)용 감광막(Photo Resist, PR)을 이용하여 구리막과 연결시키기 위한 컨택홀 혹은 비아홀을 형성함으로써, 90㎚ 이하 공정에서의 반응성 이온 식각(Reactive Ion Etching, RIE) 특성을 향상시킬 수 있는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by forming a contact hole or via hole for connecting with a copper film by using a photoresist film (Photo Resist, PR) for a polymer. The present invention relates to a method for improving the reactive ion etching (RIE) characteristics of the.

주지된 바와 같이, 반도체 소자를 제조하는데 있어서, 그 소자의 디자인 룰이 초 고집적화 됨에 따라 회로 선폭(Critical Dimension, CD)이 점차적으로 감소하게 되고, 반도체 층과 층, 그리고, 패턴과 패턴의 구조가 복잡하게 이루어져 있 어 층과 층을 연결하는 컨택홀의 역할은 매우 중요하게 된다. 여기서, 컨택은 텅스텐(W), 구리(Cu) 등의 금속 재료 물질을 사용한다. As is well known, in manufacturing a semiconductor device, as the design rules of the device become extremely high, the circuit dimension (CD) gradually decreases, and the semiconductor layer and the layer, and the pattern and the structure of the pattern Due to the complexity, the role of the contact hole connecting the layers becomes very important. Here, the contact uses a metal material material such as tungsten (W) or copper (Cu).

이러한 컨택홀을 형성하기 위한 종래 반도체 소자의 제조 과정은 도 1과 같다. A manufacturing process of a conventional semiconductor device for forming such a contact hole is shown in FIG. 1.

즉, 도 1a 내지 도 1b는 종래 기술에 따른 반도체 소자의 제조 방법을 나타내는 공정 흐름도이다. 1A to 1B are process flowcharts illustrating a method of manufacturing a semiconductor device according to the prior art.

먼저, 도 1a를 참조하면, 반도체 소자의 듀얼 다마신(Dual Damascene) 컨택홀을 형성하는 방법에서 듀얼 다마신 패턴을 형성하고, RIE를 실시한다. First, referring to FIG. 1A, in a method of forming a dual damascene contact hole of a semiconductor device, a dual damascene pattern is formed and RIE is performed.

보다 구체적으로 설명하면, 반도체 기판(111) 상에 소자분리막(112)을 형성하고, 반도체 기판(111)의 액티브 영역 상에 소스/드레인/게이트를 형성한 후, 소스/드레인/게이트 상에 실리사이드(113)를 각각 형성한다. In more detail, after the device isolation layer 112 is formed on the semiconductor substrate 111, the source / drain / gate is formed on the active region of the semiconductor substrate 111, and the silicide is formed on the source / drain / gate. Each of 113 is formed.

상기와 같이 형성된 실리사이드(113) 상에 컨택을 형성하기 위해 질화실리콘(SiN), FSG(114a, 114b) 및 SiH4(115a, 115b)를 도시된 바와 같이 차례로 증착하여 금속간 물질층(Inter Metal Dielectric, IMD)을 형성하고, 형성된 IMD 상에 트랜치 및 비아홀을 형성하고, 형성된 비아홀에 금속장벽(116) 및 텅스텐(W)(117)을 채운다.In order to form a contact on the silicide 113 formed as described above, silicon nitride (SiN), FSG 114a and 114b, and SiH 4 115a and 115b are sequentially deposited as shown to form an intermetal dielectric. , IMD), trenches and via holes are formed on the formed IMD, and the metal barrier 116 and tungsten (W) 117 are filled in the formed via holes.

이후, 비아홀 상부의 트랜치 상에 금속장벽(118)을 형성하고, 형성된 금속장벽(118)에 구리막(119)을 채우고, 노출된 전면에 질화실리콘(SiN)(120), FSG(114c) 및 SiH4(115c)를 순차적으로 증착하고, 그 위에 노블락(Novolac)용 PR(121)을 패턴으로 하여 구리막(119)과 연결시키기 위한 트랜치 및 컨택홀을 도시된 바와 같이 형성한다. 이때, 트랜치는 3300∼3700Å 정도 형성된다.Thereafter, a metal barrier 118 is formed on the trench above the via hole, the copper barrier 119 is filled in the formed metal barrier 118, and silicon nitride (SiN) 120, FSG 114c, and the exposed front surface are formed. SiH4 115c is sequentially deposited, and trenches and contact holes for connecting with the copper film 119 are formed on the PR 121 for Novolac as a pattern, as shown. At this time, the trench is formed about 3300 ~ 3700 Å.

다음으로, 도 1b를 참조하면, 듀얼 다마신 컨택홀에 대하여 애셔(Asher) 공정을 실시함에 따라 노볼락용 PR(122) 및 듀얼 다마신 RIE 이후에 남은 PR(121)이 제거되어 컨택홀이 형성되는 것이다. 여기서, 도면부호 A는 애셔 공정에 의해 노볼락(Novolac)용 PR(122)이 제거된 상태의 컨택홀을 나타낸다.Next, referring to FIG. 1B, as the Asher process is performed on the dual damascene contact hole, the PR 122 for the novolak and the PR 121 remaining after the dual damascene RIE are removed to remove the contact hole. It is formed. Here, reference numeral A denotes a contact hole in a state in which the Novolac PR 122 is removed by the Asher process.

그러나, 상술한 바와 같이 노볼락용 PR(121)을 이용할 경우, 노볼락용 PR(121)의 두께가 매우 두꺼움에 따라 90㎚ 이하 공정에서의 패턴 크기가 작아지면서 두꺼운 노볼락용 PR에 의한 패턴 불량이 종종 발생하게 되며, 이러한 패턴 불량으로 인하여 RIE 특성이 떨어지게 되어 반도체 수율을 저하시키게 되는 문제점을 갖는다. However, when the novolak PR 121 is used as described above, the thickness of the novolak PR 121 is very thick, so that the pattern size in the 90 nm or less process becomes smaller and the pattern by the thick novolak PR is reduced. Defects often occur, and due to such pattern defects, the RIE characteristics are deteriorated, thereby lowering the semiconductor yield.

따라서, 본 발명은 상술한 문제점을 해결하기 위해 안출한 것으로, 그 목적은 폴리머(Polymer)용 PR을 이용하여 구리막과 연결시키기 위한 컨택홀 혹은 비아홀을 형성함으로써, 90㎚ 이하 공정에서의 RIE 특성을 향상시킬 수 있는 반도체 소자의 제조 방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-described problems, the object of which is to form a contact hole or via hole for connecting with a copper film using a PR for a polymer, RIE characteristics in a process below 90nm It is to provide a method for manufacturing a semiconductor device that can be improved.

이러한 목적을 달성하기 위한 본 발명의 일 관점에 따른 반도체 소자의 제조 방법은 반도체 기판에 형성된 금속막 상의 질화 실리콘 필름에 형성된 금속간 물질층(IMD) 산화막 상에 포토 레지스트(PR) 패턴을 형성하는 과정과, 형성된 PR 패턴에 따라 선택적 식각을 실시하여 IMD 산화막 상에 구리막과 연결될 트랜치 및 컨택 홀 영역을 형성하는 과정과, 형성된 컨택홀 영역에 대하여 애셔 공정을 실시하고, RIE를 위한 PR 패턴 및 컨택홀 내부에 형성된 PR을 제거하여 컨택홀을 형성하는 과정을 포함하는 것을 특징으로 한다. A semiconductor device manufacturing method according to an aspect of the present invention for achieving this object is to form a photoresist (PR) pattern on the intermetallic material layer (IMD) oxide film formed on the silicon nitride film on the metal film formed on the semiconductor substrate And forming a trench and a contact hole region to be connected to the copper film on the IMD oxide by performing selective etching according to the formed PR pattern, performing an asher process on the formed contact hole region, and performing a PR pattern for RIE. And removing the PR formed inside the contact hole to form the contact hole.

또한, 상술한 목적을 달성하기 위한 본 발명의 다른 관점에 따른 반도체 소자의 제조 방법은 반도체 기판에 형성된 금속막 상의 질화 실리콘 필름에 형성된 금속간 물질층(IMD) 산화막 상에 PR 패턴을 형성하는 과정과, 형성된 PR 패턴을 마스크로 선택적 식각 및 애셔 공정을 실시하여 IMD 산화막 상에 구리막과 연결될 비아홀을 형성하는 과정을 포함하는 것을 특징으로 한다. In addition, a method of manufacturing a semiconductor device according to another aspect of the present invention for achieving the above object is a process of forming a PR pattern on the intermetallic material layer (IMD) oxide film formed on the silicon nitride film on the metal film formed on the semiconductor substrate And forming a via hole to be connected to the copper film on the IMD oxide layer by performing selective etching and asher processes using the formed PR pattern as a mask.

이하, 본 발명의 실시 예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해하게 될 것이다. Hereinafter, a plurality of embodiments of the present invention may exist, and a preferred embodiment will be described in detail with reference to the accompanying drawings. Those skilled in the art will appreciate the objects, features and advantages of the present invention through this embodiment.

도 2a 내지 도 2d는 본 발명의 일 실시 예에 따른 반도체 소자의 제조 과정을 도시한 도면이다. 2A to 2D illustrate a process of manufacturing a semiconductor device according to an embodiment of the present invention.

먼저, 도 2a를 참조하면, 반도체 기판(211) 상에 소자 분리막(212)을 형성하고, 반도체 기판(211)의 액티브 영역 상에 소스/드레인/게이트를 형성한 후, 소스/드레인/게이트 상에 실리사이드(213)를 각각 형성한다. First, referring to FIG. 2A, an isolation layer 212 is formed on a semiconductor substrate 211, a source / drain / gate is formed on an active region of the semiconductor substrate 211, and then a source / drain / gate phase is formed. Silicides 213 are formed in each.

상술한 바와 같이 형성된 실리사이드(213) 상에 컨택을 형성하기 위해 질화실리콘(SiN), FSG(214a, 214b) 및 SiH4(215a, 215b)를 도시된 바와 같이 순차적으로 증착하여 IMD를 형성하고, 형성된 IMD 상에 트랜치 및 비아홀을 형성하며, 형성 된 비아홀에 금속장벽(216) 및 텅스텐(W)(217)을 채운다. 이후, 비아홀 상부의 트랜치 상에 금속장벽(218)을 형성하고, 형성된 금속장벽(218)에 구리막(219)을 채우고, 노출된 전면에 질화실리콘(SiN)(220)을 5∼10Å의 두께로 형성한다.In order to form a contact on the silicide 213 formed as described above, silicon nitride (SiN), FSG 214a and 214b and SiH 4 215a and 215b are sequentially deposited as shown to form an IMD, and formed Trench and via holes are formed on the IMD, and metal barriers 216 and tungsten (W) 217 are filled in the formed via holes. Subsequently, a metal barrier 218 is formed on the trench in the upper portion of the via hole, the copper barrier 219 is filled in the formed metal barrier 218, and the silicon nitride (SiN) 220 is formed on the exposed entire surface of 5 to 10 kW. To form.

다음으로, 도 2b를 참조하면, 질화실리콘(SiN)(220) 상에 FSG(214c) 및 SiH4(215c)를 순차적으로 증착시킨 다음에, 도 2c와 같이, 증착된 SiH4(215c) 상에 폴리머(Polymer)용 PR(221)을 패턴으로 구리막(219)과 연결시키기 위한 트랜치 및 컨택홀 영역에 대하여 선택적 듀얼 다마신 RIE를 진행시켜 도시된 바와 같이 형성한다. 이때, 트랜치 영역은 3300∼3700Å 정도 형성되며, 폴리머용 PR은 1000∼2000Å의 두께로 형성된다. Next, referring to FIG. 2B, the FSG 214c and the SiH 4 215c are sequentially deposited on the silicon nitride (SiN) 220, and then the polymer is deposited on the deposited SiH 4 215c as shown in FIG. 2C. A selective dual damascene RIE is formed as shown in the trench and contact hole region for connecting the PR 221 for the polymer to the copper film 219 in a pattern. At this time, the trench region is formed at about 3300 to 3700 GPa, and the PR for the polymer is formed at a thickness of 1000 to 2000 GPa.

이후, 도 2d를 참조하면, 듀얼 다마신 컨택홀에 대하여 애셔(Asher) 공정을 실시함에 따라 폴리머용 PR(222) 및 듀얼 다마신 RIE 이후에 남은 PR(221)이 제거되어 구리막(219)과 연결시키기 위한 컨택홀(B)이 형성되는 것이다. 여기서, 컨택홀(B)은 애셔 공정에 의해 폴리머용 PR(222)이 제거된 상태이다. Subsequently, referring to FIG. 2D, as the Asher process is performed on the dual damascene contact hole, the PR 221 remaining after the dual damascene RIE for the polymer is removed to remove the copper film 219. Contact hole (B) is formed to connect with the. Here, the contact hole B is in a state where the polymer PR 222 is removed by an asher process.

따라서, 폴리머(Polymer)용 PR을 이용하여 구리막과 연결시키기 위한 컨택홀을 형성함으로써, 90㎚ 이하 공정에서의 RIE 특성을 향상시켜 패턴 불량을 없애 반도체 수율을 향상시킬 수 있다. Therefore, by forming a contact hole for connecting with the copper film using the PR for polymer, the RIE characteristics in the 90 nm or less process can be improved to eliminate the pattern defects, thereby improving the semiconductor yield.

도 3a 내지 도 3d는 본 발명의 다른 실시 예에 따른 반도체 소자의 제조 과정을 도시한 도면이다. 3A to 3D are views illustrating a process of manufacturing a semiconductor device according to another embodiment of the present invention.

먼저, 도 3a를 참조하면, 반도체 기판(311) 상에 소자 분리막(312)을 형성하고, 반도체 기판(311)의 액티브 영역 상에 소스/드레인/게이트를 형성한 후, 소스/ 드레인/게이트 상에 실리사이드(313)를 각각 형성한다. First, referring to FIG. 3A, an isolation layer 312 is formed on a semiconductor substrate 311, a source / drain / gate is formed on an active region of the semiconductor substrate 311, and then a source / drain / gate image is formed. Silicides 313 are formed in each.

상술한 바와 같이 형성된 실리사이드(313) 상에 컨택을 형성하기 위해 질화실리콘(SiN), FSG(314a, 314b) 및 SiH4(315a, 315b)를 도시된 바와 같이 순차적으로 증착하여 IMD를 형성하고, 형성된 IMD 상에 트랜치 및 비아홀을 형성하며, 형성된 비아홀에 금속장벽(316) 및 텅스텐(W)(317)을 채운다. 이후, 비아홀 상부의 트랜치 상에 금속장벽(318)을 형성하고, 형성된 금속장벽(318)에 구리막(319)을 채우고, 노출된 전면에 질화실리콘(SiN)(320)을 5∼10Å의 두께로 형성한다.Silicon nitride (SiN), FSG 314a, 314b, and SiH4 315a, 315b were sequentially deposited as shown to form an IMD to form a contact on the silicide 313 formed as described above, and formed Trench and via holes are formed on the IMD, and metal barrier walls 316 and tungsten (W) 317 are filled in the formed via holes. Subsequently, a metal barrier 318 is formed on the trench in the upper portion of the via hole, the copper barrier 319 is filled in the formed metal barrier 318, and the silicon nitride (SiN) 320 is formed on the exposed front surface of 5 to 10 Å thick. To form.

다음으로, 도 3b를 참조하면, 질화실리콘(SiN)(320) 상에 FSG(314c) 및 SiH4(315c)를 순차적으로 증착시킨다.Next, referring to FIG. 3B, the FSG 314c and the SiH 4 315c are sequentially deposited on the silicon nitride (SiN) 320.

이후, 도 3c와 같이, 증착된 SiH4(315c) 상에 구리막(319)과 연결시키기 위하여 폴리머용 PR(321) 패턴을 1000∼2000Å의 두께로 형성시킨 다음에, 도 3d에 도시된 바와 같이 형성된 폴리머용 PR(321) 패턴을 마스크로 선택적 듀얼 다마신 RIE 진행 및 애셔(Asher) 공정을 실시하여 구리막(319)과 연결시키기 위한 비아홀(C)을 형성시킬 수 있다. Thereafter, as shown in FIG. 3D, a PR 321 pattern for the polymer is formed on the deposited SiH 4 315c so as to be connected to the copper film 319 to a thickness of 1000 to 2000 GPa. By using the formed polymer PR 321 pattern as a mask, a selective dual damascene RIE process and an Asher process may be performed to form a via hole C to be connected to the copper layer 319.

따라서, 폴리머(Polymer)용 PR을 이용하여 구리막과 연결시키기 위한 비아홀을 형성하여 90㎚ 이하 공정에서의 RIE 특성을 향상시킴으로써, 기존에서와 같이 비아홀 내에 잔존하는 노블락 PR로 인하여 비아홀이 막히게 되는 막임 현상을 해결할 수 있어 반도체 수율을 향상시킬 수 있다. Therefore, by forming a via hole for connecting with the copper film using the PR for the polymer to improve the RIE characteristics in the 90 nm or less process, the via hole is blocked due to the noblock PR remaining in the via hole as in the past. The phenomenon can be solved, and semiconductor yield can be improved.

또한, 본 발명의 사상 및 특허청구범위 내에서 권리로서 개시하고 있으므로, 본원 발명은 일반적인 원리들을 이용한 임의의 변형, 이용 및/또는 개작을 포함할 수도 있으며, 본 명세서의 설명으로부터 벗어나는 사항으로서 본 발명이 속하는 업계에서 공지 또는 관습적 실시의 범위에 해당하고 또한 첨부된 특허청구범위의 제한 범위 내에 포함되는 모든 사항을 포함한다. In addition, since the present invention is disclosed as a right within the spirit and claims of the present invention, the present invention may include any modification, use and / or adaptation using general principles, and the present invention as a matter deviating from the description of the present specification. It includes everything that falls within the scope of known or customary practice in the art to which it belongs and falls within the scope of the appended claims.

상기에서 설명한 바와 같이, 본 발명은 폴리머용 PR을 이용하여 구리막과 연결시키기 위한 비아홀을 형성하여 90㎚ 이하 공정에서의 RIE 특성을 향상시킴으로써, 기존에서와 같이 비아홀 내에 잔존하는 노블락 PR로 인하여 비아홀이 막히게 되는 막임 현상을 해결할 수 있으며, RIE 특성을 향상시켜 패턴 불량을 없애 반도체 수율을 향상시킬 수 있는 효과가 있다.As described above, the present invention improves the RIE characteristics in the 90 nm or less process by forming a via hole for connecting with a copper film by using a PR for a polymer, thereby providing a via hole due to the noblock PR remaining in the via hole. This clogging phenomenon can be solved, there is an effect that can improve the semiconductor yield by eliminating the pattern defect by improving the RIE characteristics.

Claims (11)

반도체 소자의 제조 방법으로서, As a manufacturing method of a semiconductor device, 반도체 기판에 형성된 금속막 상의 질화 실리콘 필름에 형성된 금속간 물질층(IMD) 산화막 상에 포토 레지스트(PR) 패턴을 형성하는 과정과, Forming a photoresist (PR) pattern on the intermetallic material layer (IMD) oxide film formed on the silicon nitride film on the metal film formed on the semiconductor substrate; 상기 형성된 PR 패턴에 따라 선택적 식각을 실시하여 IMD 산화막 상에 상기 구리막과 연결될 트랜치 및 컨택홀 영역을 형성하는 과정과, Forming a trench and a contact hole region to be connected to the copper layer on an IMD oxide layer by performing selective etching according to the formed PR pattern; 상기 형성된 컨택홀 영역에 대하여 애셔 공정을 실시하고, 상기 RIE를 위한 PR 패턴 및 컨택홀 내부에 형성된 PR을 제거하여 컨택홀을 형성하는 과정Performing a-sher process on the formed contact hole region, and removing the PR pattern and the PR formed inside the contact hole to form a contact hole 을 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 트랜치 영역은, 3300∼3700Å 으로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.The trench region is formed of 3300 to 3700 GPa. 제 1 항에 있어서, The method of claim 1, 상기 PR은, 1000∼2000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.Said PR is formed in thickness of 1000-2000 micrometers, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 1 항 또는 제 3 항에 있어서, The method according to claim 1 or 3, 상기 PR은, 폴리머용 PR인 것을 특징으로 하는 반도체 소자의 제조 방법.Said PR is PR for polymers, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 1 항에 있어서, The method of claim 1, 상기 금속막은, 구리인 것을 특징으로 하는 반도체 소자의 제조 방법.The said metal film is copper, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 1 항에 있어서, The method of claim 1, 상기 식각은, 반응성 이온 식각(RIE)인 것을 특징으로 하는 반도체 소자의 제조 방법.The etching is a method of manufacturing a semiconductor device, characterized in that the reactive ion etching (RIE). 반도체 소자의 제조 방법으로서, As a manufacturing method of a semiconductor device, 반도체 기판에 형성된 금속막 상의 질화 실리콘 필름에 형성된 금속간 물질층(IMD) 산화막 상에 PR 패턴을 형성하는 과정과, Forming a PR pattern on the intermetallic material layer (IMD) oxide film formed on the silicon nitride film on the metal film formed on the semiconductor substrate; 상기 형성된 PR 패턴을 마스크로 선택적 식각 및 애셔 공정을 실시하여 IMD 산화막 상에 상기 구리막과 연결될 비아홀을 형성하는 과정A process of forming via holes to be connected to the copper film on an IMD oxide layer by performing selective etching and asher processes using the formed PR pattern as a mask. 을 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제 7 항에 있어서, The method of claim 7, wherein 상기 PR은, 1000∼2000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 제조 방법.Said PR is formed in thickness of 1000-2000 micrometers, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 7 항 또는 제 8 항에 있어서, The method according to claim 7 or 8, 상기 PR은, 폴리머용 PR인 것을 특징으로 하는 반도체 소자의 제조 방법.Said PR is PR for polymers, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 7 항에 있어서, The method of claim 7, wherein 상기 금속막은, 구리인 것을 특징으로 하는 반도체 소자의 제조 방법.The said metal film is copper, The manufacturing method of the semiconductor element characterized by the above-mentioned. 제 7 항에 있어서, The method of claim 7, wherein 상기 식각은, 반응성 이온 식각(RIE)인 것을 특징으로 하는 반도체 소자의 제조 방법.The etching is a method of manufacturing a semiconductor device, characterized in that the reactive ion etching (RIE).
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