KR20080006207A - Semiconductor, method of manufacturing the same and semiconductor light-emitting diode - Google Patents

Abstract

A semiconductor, a manufacturing method thereof, and a semiconductor LED are provided to improve crystallinity of the semiconductor by vertically and horizontally growing a semiconductor layer on a crystalline surface of a substrate. A semiconductor structure comprises a substrate(1000) and a semiconductor layer(4000). A convexo-concave portion is formed on the substrate. The convexo-concave portion includes a convex portion(1100a), a concave portion(1100b), and a curved side surface(1100c). The convex portion is formed by a horizontal surface, a line, or a spot. The concave portion is formed of a line or a spot. The curved side surface couples the convex portion with the concave portion and has a slant surface of a predetermined curvature. A growth mask pattern is formed on a convex portion of the convexo-concave portion.

Description

Semiconductor structure, method of manufacturing the same and semiconductor light emitting diode

1 is a schematic cross-sectional view showing a conventional semiconductor light emitting diode.

2 to 9C are cross-sectional views illustrating a manufacturing process of a semiconductor structure in accordance with the present invention.

10 to 13 are optical micrographs and SEM pictures showing one embodiment according to the present invention.

14 to 16 are optical micrographs and SEM pictures showing another embodiment according to the present invention.

17 and 18 are optical photomicrographs showing another embodiment according to the present invention.

19 and 20 are TEM photographs showing a cross section of a gallium nitride semiconductor layer of an embodiment according to the present invention.

21 and 22 are cross-sectional views showing one example of a semiconductor light emitting diode according to the present invention.

23 is a cross-sectional view showing another example of a semiconductor light emitting diode according to the present invention;

24 is a graph showing the light emission characteristics of a semiconductor light emitting diode according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100, 1000: substrate 25: etching mask pattern

30, 3000: growth mask pattern

40, 400, 4000: semiconductor layer

5000: N-type semiconductor layer 6000: active layer

7000: P-type semiconductor layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor structure, a method for manufacturing the same, and a semiconductor light emitting diode. More particularly, the present invention relates to a semiconductor structure capable of improving luminous efficiency and securing reliability by reducing crystal defects and improving crystallinity of a semiconductor layer. It relates to a method and a semiconductor light emitting diode.

A light emitting diode (LED) refers to a device that makes a small number of carriers (electrons or holes) injected using a pn junction structure of a semiconductor and emits a predetermined light by recombination thereof. GaAs, AlGaAs, GaN Various colors may be realized by configuring a light emitting source by changing a compound semiconductor material such as InGaN and AlGaInP.

Among the compound semiconductors, nitride semiconductor materials exhibit excellent luminescence properties in the visible and UV regions, and are also used in high power, high frequency electronic devices. In particular, gallium nitride (GaN) has a direct transition bandgap of 3.4 eV at room temperature and is combined with materials such as indium nitride (InN) and aluminum nitride (AlN) at 0.7 eV (InN) to 3.4 eV ( GaN) and 6.2eV (AlN) have a direct energy bandgap and can emit light in a wide wavelength range from visible light to ultraviolet light.

1 is a schematic cross-sectional view showing a conventional semiconductor light emitting diode.

Referring to FIG. 1, a light emitting diode includes a substrate 1 and an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 sequentially formed on the substrate 1. In addition, a portion of the P-type electrode 5 formed on the P-type semiconductor layer 4 and the N-type semiconductor layer 2 exposed by etching part of the P-type semiconductor layer 4 and the active layer 3 is exposed. The formed N-type electrode 6 is included. The P-type semiconductor layer 4 uses a semiconductor compound doped with P-type impurities, and the N-type semiconductor layer 2 uses a semiconductor compound doped with N-type impurities.

P-type and N-type semiconductor layers 4 and 2 formed on the upper and lower portions of the active layer 3 respectively supply current to the active layer 3 to emit light.

In order to improve the performance of the light emitting diode, the internal quantum efficiency of recombining electrons and holes must be high to obtain a large amount of light from the current flowing therein, and also the generated light is emitted to the outside of the light emitting diode. Extraction efficiency should be high. To this end, a semiconductor layer with low crystal defects and excellent crystallinity is first grown on a substrate to increase the internal quantum efficiency of the light emitting diode, and light generated from the active layer is reflected only inside the light emitting diode, that is, total internal reflection. ), The extraction efficiency of the light emitting diode should be increased.

However, conventional nitride semiconductors do not have a substrate that is lattice matched, and the nitride semiconductor layer formed on the sapphire substrate has a high density of about 10 ⁸ to 10 ⁹ / cm ² due to the difference in lattice constants and thermal expansion coefficients of the sapphire and nitride semiconductor layers. Threading dislocation of a.

In addition, the planes in each direction formed by the substrate and the semiconductor layer of the conventional semiconductor light emitting diode are formed in parallel or perpendicular to each other, so that a large amount of light emitted from the active layer does not easily escape to the outside of the light emitting diode, causing total internal reflection inside. Circulated, absorbed and extinguished.

Accordingly, researches to improve the performance of light emitting diodes by reducing crystal defects and increasing extraction efficiency have been actively conducted. As a method for reducing crystal defects, a method of growing a semiconductor layer by horizontal growth is disclosed.

Epitaxial lateral overgrowth (ELO) technology can suppress the penetration into the surface by selectively growing the semiconductor layer vertically and horizontally according to the mask pattern and blocking the through potential in the horizontal growth region. Peneo-Epitaxy (PE), Cantilever Epitaxy (CE), Lateral Epitaxy on Pattened Sapphire (LEPS), etc., are all modified in the ELO technology to suppress penetration of penetration potentials into the surface through horizontal growth. to be.

ELO technology grows a first semiconductor layer on a substrate, deposits a mask material to form a mask pattern by dry etching, and then grows the second semiconductor layer again. Such a technique can prevent the propagation of crystal defects by horizontal growth, but after growing the first semiconductor layer, dry etching must be performed to form a mask pattern, and then the second semiconductor layer has to be grown. There is this.

In the dry etching of the mask pattern, the same problem occurs in the case of the PE technology in which the semiconductor layer is grown after etching to the first semiconductor layer and a part of the substrate.

In addition, in the case of LEPS technology, in which a semiconductor layer is grown on a sapphire substrate having an uneven structure to increase external quantum efficiency, it is difficult to dry-etch the substrate, and the ratio of the vertically growing area to the horizontally growing area is large. A large decrease in penetration potential due to horizontal growth cannot be expected. In addition, in order to form a flat surface by filling a high step of the semiconductor layer grown on the irregularities formed substrate, there is a problem that the specific growth conditions different from the existing and the growth time is long.

In the case of the CE technology in which the semiconductor layer grown on the convex portion of the unevenness is formed by horizontally growing and sealing the semiconductor layer grown on the concave portion using the substrate having the unevenness, there is a difficulty in dry etching the substrate as well. In addition, since the uneven surface of the substrate is formed in parallel or perpendicular to the surface of the semiconductor layer, a large amount of light emitted from the active layer causes total reflection inside and does not escape to the outside of the light emitting diode.

The present invention is to solve the above problems, by forming irregularities on the surface of the substrate through the wet etching to grow the semiconductor layer vertically and horizontally to reduce the penetration potential of the semiconductor layer, to grow through a simpler process, the light emission An object of the present invention is to provide a semiconductor structure, a method of manufacturing the same, and a semiconductor light emitting diode capable of improving the performance and reliability of the diode.

In order to achieve the above object, the present invention provides a semiconductor structure, comprising a substrate having a concave-convex and a semiconductor layer formed on the substrate, the concave-convex and the convex portion formed in the form of a horizontal plane, line or dot, horizontal plane, line Or it provides a semiconductor structure comprising a concave portion formed in the form of a dot, the convex portion and the concave portion is inclined plane having a predetermined slope or a curved surface having a predetermined curvature.

The growth mask pattern may be formed on the convex portion of the convex and convex portions, and the growth mask pattern may be selected from the group consisting of SiO ₂ , SiO _x , SiN ₂ , SiN _x , SiO _x N _y, or a metal material.

The unevenness may be formed by wet etching, and the unevenness may include unevenness in the form of a pyramid or a truncated pyramid.

The semiconductor layer may include an epitaxial layer grown in a vertical direction from the recess and in a horizontal direction across the convex portion. In addition, the semiconductor layer may be discontinuous or an uneven structure may be formed on a surface thereof.

The substrate may be selected from the group consisting of sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP or GaAs, the semiconductor layer is made of GaN, InN, AlN, InGaN, AlGaN or InAlGaN. Can be selected from the group.

The present invention includes the steps of providing a substrate on which the unevenness is formed and forming a semiconductor layer on the substrate, wherein the unevenness is a convex portion formed in the form of a horizontal plane, a line or a point, and in the form of a horizontal plane, a line or a point. The concave portion is formed, and the convex portion and the concave portion connected to provide a method for manufacturing a semiconductor structure, characterized in that it comprises an inclined plane having a predetermined slope or a curved surface having a predetermined curvature.

After preparing the substrate on which the unevenness is formed, the method may include forming a growth mask pattern on the convex portion of the unevenness.

The preparing of the substrate on which the irregularities are formed may include forming an etching mask pattern on the planar substrate and performing wet etching through the etching mask pattern to form the irregularities.

The wet etching is performed in the group consisting of H ₂ SO ₄ , H ₃ PO ₄ , buffered-oxide etch (BOE), HF, HNO ₃ , KOH, NaCl, NaOH, KBrO ₃ solution, a mixed solution thereof, or a dilute solution thereof. The etching solution of choice can be used.

Forming the semiconductor layer may include growing an epitaxial layer in a vertical direction from the recess and in a horizontal direction across the convex portion, which is a low temperature nucleation layer at a temperature of 400 to 800 ° C. Or forming a low temperature buffer layer, vertically growing the epitaxial layer at a temperature of 900 to 1150 ° C, and horizontally growing the epitaxial layer at a temperature of 1050 to 1200 ° C.

The present invention also includes a substrate having irregularities formed thereon, a semiconductor layer formed on the substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer formed on the semiconductor layer, wherein the irregularities are formed in the form of a horizontal plane, line or dot. And a convex portion, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane having a predetermined slope or a side surface of a curved shape having a predetermined curvature by connecting the convex portion and the concave portion. Provided is a semiconductor light emitting diode.

The growth mask pattern may be formed on the convex portion of the convex and convex portions, and the growth mask pattern may be selected from the group consisting of SiO ₂ , SiO _x , SiN ₂ , SiN _x , SiO _x N _y, or a metal material.

The semiconductor layer, the N-type semiconductor layer, the active layer or the P-type semiconductor layer may be discontinuous or a concave-convex structure may be formed on the surface.

Hereinafter, a semiconductor structure and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 to 9C are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to the present invention.

Deposition and growth methods of the material layers described below include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PECVD). Various methods can be used including Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like.

First, the board | substrate with predetermined unevenness | corrugation was provided in the surface. Here, the unevenness is a convex portion formed in the form of a horizontal plane, a line or a point, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane or curved shape having a predetermined slope by connecting the convex portion and the concave part. Characterized by including the side of the.

Referring to FIG. 2, a layered etching mask 20 is deposited on the planar substrate 10. Sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP, GaAs and the like are used as the substrate 10, and SiO ₂ , SiO _x , and SiN are used as materials of the etching mask 20. ₂ , SiN _x , SiO _x N _y and the like are used. Of course, various materials may be used without being limited thereto. The thickness of the etching mask 20 is preferably 100 to 2000Å, and may vary according to the etching depth of the substrate 10, the material of the etching mask 20, the deposition method of the etching mask 20, and the deposition conditions.

Referring to FIG. 3, an etching mask pattern 25 is formed by wet or dry etching the etching mask 20. To this end, a layered photoresist is coated on the etching mask 20, and then a photoresist pattern is formed through a photolithography process using a predetermined photo mask. In addition, a wet etching process using the photoresist pattern as a mask using a buffered-oxide etch (BOE), hydrofluoric acid (HF), or a diluting solution thereof is performed to remove a portion of the etching mask 20 to form an etching mask pattern. 25 can be formed.

The etching mask pattern 25 is variously formed according to the shape, structure, and arrangement pattern of the irregularities to be formed on the substrate 10. As shown in FIG. 4A, the stripe structure 25 may be formed, or as shown in FIG. 4B, the stripe structure 26 may be formed by connecting all of the stripe shapes. In addition, as shown in FIG. 4C, a structure 27 including a square is formed, or as shown in FIG. 4D, a structure 28 including a rhombus or a parallelogram is formed, or a hexagon is formed as shown in FIG. 4E. It is also possible to form the structure 29 included. In addition, the arrangement pattern of the structure including the polygon may be arranged on a straight line consisting of a plurality of polygons perpendicular to each other, such as a horizontal line and a vertical line, as shown in Figures 4c and 4e, a plurality of polygons are perpendicular to each other as shown in Figure 4d It may also be arranged on a straight line having a predetermined slope.

The above-described etching mask pattern is not limited thereto, and may be formed in various structures including a polygon, a circle, an ellipse, and the like, and may be formed in various ways in a shape capable of forming irregularities including convex portions or concave portions. Moreover, the arrangement pattern thereof can also be formed in various ways.

Subsequently, the substrate 10 is etched using the etching mask pattern 25 to form irregularities on the surface of the substrate 10.

As an etching solution for wet etching of the substrate 10, a H ₂ SO ₄ or H ₃ PO ₄ solution may be used in the case of a sapphire (Al ₂ O ₃ ) or a GaN substrate, and BOE (buffered- in the case of a SiC substrate). oxide etch) or HF solution can be used, BOE (buffered-oxide etch), HF, HNO ₃ or KOH solution can be used for Si substrate, NaCl solution can be used for ZnO substrate, GaAs substrate In the case of H ₂ SO ₄ , NaOH or HNO ₃ solution can be used, in the case of GaP or InP substrate can be used H ₂ SO ₄ and KBrO ₃ mixed solution. Of course, not only the above-described etching solution, but also various other etching solutions may be used.

The wet etching of the substrate 10 may have various shapes of an etched cross section according to etching variables such as a crystal direction of the substrate 10, an etching mask pattern, a mixing ratio of an etching solution, an etching temperature, and an etching time.

Referring to FIG. 5A, wet etching is performed using the etching mask pattern 25 as an etching mask to form concavities and convexities 11a, 11b, and 11c on the surface of the substrate 10. The unevenness 11a, 11b, 11c has a predetermined slope by connecting the convex portion 11a formed of the horizontal plane, the concave portion 11b formed of the horizontal plane, and the convex portion 11a and the concave portion 11b. And a side face 11c consisting of an inclined plane.

The convex portions of the concave-convex portion may be formed in a horizontal plane like the convex portion 11a illustrated in FIG. 5A, and may be formed in the form of a line or a dot like the convex portion 12a illustrated in FIG. 5B. In addition, the concave portion of the concave-convex portion may be formed in a horizontal plane like the concave portions 11b and 12b shown in FIGS. 5A and 5B, and may be formed in the form of a line or a point like the concave portion 13b shown in FIG. 5C. have. In addition, as shown in FIG. 5D, the convex portions 14a and the concave portions 14b of the unevenness may be formed in the form of lines or dots at the same time. Of course, the present invention is not limited to the above, and the convex portions and the concave portions of the concave-convex portion may have a structure in which various forms of horizontal planes, lines or points are combined.

When the side surface 11c of the unevenness is formed perpendicular to the horizontal surface of the semiconductor layer, a substantial amount of light generated in the semiconductor layer continues through the side surface of the unevenness formed vertically and the surface of the semiconductor layer or any horizontal plane of the unevenness. As it is totally internally reflected, it does not transmit to the outside, thereby reducing the extraction efficiency of the light emitting diode. Therefore, in order to increase the extraction efficiency of the light emitting diode, it is preferable that the side surface of the unevenness is an inclined plane having a predetermined slope or a curved surface having a predetermined curvature rather than perpendicular to the surface of the semiconductor layer.

As shown in FIG. 5A, the lateral shape of the unevenness is formed in a symmetrical cross-sectional shape in which both side surfaces 11c facing each other with respect to the recessed portion 11b have the same slope, or as shown in FIG. 5E. Both sides 15c facing each other with respect to the portion 15b may have an asymmetric cross-sectional shape having different inclinations. In addition, as shown in FIG. 5F, the side surfaces having various inclinations may have a cross-sectional shape 16c connected thereto, or as shown in FIG. 5G, the curved surface 17c may have a predetermined curvature. As described above, the lateral shape of the irregularities may be formed in various shapes not including a surface perpendicular to the surface of the semiconductor layer.

Unevenness may be formed through a wet etching process that is simpler than a conventional dry etching, and various shapes of an etching cross section may be formed according to etching variables such as an etching mask pattern, a mixing ratio of an etching solution, a temperature of an etching solution, and an etching time. have.

In addition, according to the shape of the etching mask pattern 25 formed in various ways as described above, the shape of the uneven structure formed by etching the substrate 10 may also be variously formed. That is, according to the shapes of the various etching mask patterns as shown in Figures 4a to 4e, the structure of the concave-convex may be formed in a stripe structure, or may be formed in a lattice structure in which a plurality of stripe is connected, polygonal, circular It may also be formed into a structure including an elliptical or the like.

Next, a growth mask pattern 30 for selectively growing a semiconductor layer is provided on a predetermined region of the substrate 10 on which the unevennesses 11a, 11b, and 11c are formed as described above. The growth mask pattern 30 may be used as it is without removing the etching mask pattern 25, or the growth mask pattern 30 may be separately formed after the etching mask pattern 25 is removed. In addition, the growth mask pattern 30 may be formed without proceeding. That is, the semiconductor layer may be grown directly on the substrate 10 on which the unevennesses 11a, 11b, and 11c are formed without the growth mask pattern 30.

When the etching mask pattern 25 is used as the growth mask pattern 30, the growth mask pattern 30 may have a layered structure horizontally on the convex portion, or a horizontal area of the growth mask pattern 30. It may be larger than the area of this convex part. That is, in the etching of the substrate 10, the area of the convex portion may be smaller than the horizontal area of the etching mask pattern, that is, the growth mask pattern 30, as shown in FIG. 5B by etching in the horizontal direction. .

The etching mask pattern 25 may be removed by wet and dry etching. For example, the etching mask pattern 25 may be removed by wet etching using a buffered-oxide etch (BOE), a hydrofluoric acid (HF), or a diluting solution thereof.

The growth mask pattern 30 may be formed through the same process as the formation of the etching mask pattern 25 described above. In this case, the growth mask pattern 30 may use the same material as the etching mask pattern 25, but is not limited thereto.

When the convex portions of the convex and convex portions formed on the substrate are horizontal planes, the growth mask pattern may preferably cover 90% or more of the convex portion horizontal plane area, but is not limited thereto and may cover an area smaller than this. That is, as shown in FIG. 6A, the growth mask pattern 30 is formed on the entire horizontal plane of the uneven convex portion 11a, or as shown in FIG. 6B, the growth mask pattern 31 is the uneven convex portion 11a. It may be formed smaller than the area of. In addition, as shown in FIG. 6C, the growth mask pattern 32 may be formed on the entire horizontal plane of the uneven convex portion 11a and a part of the uneven side 11c. In addition, as shown in FIG. 6D, the growth mask pattern 33 may be formed on the entire horizontal plane of the uneven convex portion 11a, the uneven side surface 11c, and a part of the uneven concave portion 11b.

In addition, when the uneven convex portion formed on the substrate is a line or a point, or when the uneven convex portion has a relatively small area compared to the uneven side and the uneven concave portion, the growth mask pattern 34 is uneven as shown in FIG. 6E. It may be formed on the convex portion 12a and the uneven side surface 12c, or the growth mask pattern may be omitted as shown in FIG. 6F.

This is to allow the semiconductor layer to dominantly grow on the crystal surface of the substrate formed by the etching, that is, the recess or side of the unevenness. Therefore, in the case where the convex portion of the unevenness formed in the substrate is the horizontal plane, the growth mask pattern is preferably formed to cover at least 90% or more of the convex portion horizontal plane area as described above.

The shape and position of the growth mask pattern are not limited to those described above, and may be appropriately adjusted so that the semiconductor layer may be dominantly grown on the crystal surface of the substrate formed by etching. In addition, the cross section of the growth mask pattern may have various shapes, and the thickness thereof may be variously formed according to a process.

Such a growth mask pattern allows the semiconductor layer vertically grown on the crystal surface of the substrate formed by etching, that is, the concave portion or the side surface of the unevenness to be horizontally grown on the convex portion, thereby significantly reducing propagation of the penetration potential to the surface of the semiconductor layer. Accordingly, the internal quantum efficiency, performance and reliability of the light emitting diodes grown on the substrate can be improved.

In addition, when the growth mask pattern is formed of a material having a refractive index smaller than that of the substrate, the reflectance of light may be increased at the interface between the semiconductor layer and the growth mask, and the number of times of total reflection inside the semiconductor layer by dispersing light generated in the semiconductor layer By reducing the extraction efficiency of the light emitting diode can be improved.

Further, as mentioned above, when the uneven convex portions formed on the substrate are lines or dots, or when the uneven convex portions have a relatively small area compared to the uneven side and the uneven concave portions, the growth mask pattern may be omitted.

When the convex portions of the concave and convex portions are made of lines or dots and there is no growth mask pattern on the convex portion, vertical growth of the semiconductor layer may be performed not only on the concave portion of the concave and convex portions, but also on the side and convex portions. At this time, the semiconductor layer grown on the surface, line or dot forming the uneven structure is grown at different growth rates depending on the growth conditions. Thus, the leading vertical growth may be made from any part of the uneven structure, that is, the face, the line or the point, and the horizontal growth may occur from the portion where the leading vertical growth is made with the relatively small growth rate.

In addition, when the convex portion of the unevenness is formed in the horizontal plane and there is no growth mask pattern on the convex portion, it is preferable that the convex portion area is relatively small in order to prevent the dominant vertical growth from the convex portion. For example, when the uneven pattern is formed in a stripe structure or a lattice structure in which a plurality of stripes are all connected, the width of the horizontal plane that forms the convex portion is preferably smaller than 1 μm. In addition, when the unevenness is a structure in which the pattern includes a polygon or a structure including any figure formed by a closed curve or a straight line or the like, the area of the horizontal plane that forms the convex portion is preferably smaller than 1 μm ² .

7A to 7C, the semiconductor layer 40 is formed on the substrate 10 on which the unevennesses 11a, 11b and 11c and the growth mask pattern 30 are formed.

Examples of the semiconductor include GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and the like. The atmosphere (carrier) gas and source gases injected into the MOCVD equipment may be variously changed according to the semiconductor layer manufactured at this time. That is, when the GaN semiconductor layer is formed as the semiconductor layer 40, nitrogen, hydrogen, or a mixed gas of nitrogen and hydrogen is used as the atmosphere gas, and trimethylgallium as the Ga source and ammonia (NH ₃ ) as the N source. Grow using. Here, triethylgallium may be used instead of the trimethylgallium as a Ga source, and N ₂ H ₄ may be added to ammonia as an N source, and dimethylhyrazine may be used.

When the InN semiconductor layer is formed as the semiconductor layer 40, nitrogen is used as an atmosphere gas, and trimethylindium is used as an In source, and ammonia (NH ₃ ) is used as an N source. Here, the atmosphere gas and the In source and the N source gas may be variously changed.

When the AlN single crystal thin film is formed as the semiconductor layer 40, hydrogen is used as the atmosphere gas, and trimethylaluminum as the Al source and ammonia (NH ₃ ) as the N source are grown. Here, the atmosphere gas and the Al source and the N source gas may be variously changed.

In the case of forming the InGaN single crystal thin film using the semiconductor layer 40, nitrogen is used as the atmosphere gas, trimethyindium is used as the In source, trimethygallium is used as the Ga source, and ammonia (NH ₃ ) is used as the N source. Grow by using. Here, the atmosphere gas, the In source, the Ga source, and the N source gas may be variously changed.

When the AlGaN single crystal thin film is formed as the semiconductor layer 40, hydrogen is used as an atmosphere gas, trimethalum is used as the Al source, trimethygallium is used as the Ga source, and ammonia (NH ₃ ) is used as the N source. Grow by using. Here, of course, the atmosphere gas and the In source, Al source, Ga source and N source gas can be variously changed.

In addition, when the InAlGaN single crystal thin film is formed of the semiconductor layer 40, hydrogen or nitrogen is used as an atmosphere gas, trimethyindium is used as the In source, trimethyalumium is used as the Al source, and trimethyl is used as the Ga source. It grows using gallium (Trimethygallium) and ammonia (NH ₃ ) as the N source. Here, of course, the atmosphere gas and the In source, Al source, Ga source and N source gas can be variously changed.

The growth of the semiconductor layer 40 includes a first step of forming a low-temperature nucleation layer or a low-temperature buffer layer, a second step of epitaxial layer growth, and an epitaxial growth. And a third step in which the shallow layer grows horizontally. Other steps may be added in addition to these basic steps, or some of the steps may be omitted.

Each step of manufacturing the semiconductor layer 40 is accomplished by controlling various thin film growth conditions, for example, by controlling the growth temperature. That is, in the case of using a low pressure MOCVD equipment, after forming a low temperature nucleation layer or a low temperature buffer layer for the growth of the epitaxial layer at a relatively low temperature of 400 to 800 ℃, the vertical of the epitaxial layer at a temperature of 900 to 1150 ℃ It is formed by promoting growth and by promoting horizontal growth of the epitaxial layer at a higher temperature of 1050-1200 ° C. This growth step may continue until a flat, continuous semiconductor layer is formed due to the vertical and horizontal growth of the epitaxial layer. Of course, the present invention is not limited thereto, and may be variously formed according to a desired purpose. For example, the semiconductor layer may not be sealed, thereby forming a discontinuous semiconductor layer, or a concave-convex structure may be formed on the surface of the continuous semiconductor layer.

In addition to the temperature conditions, it is possible to control the vertical growth and the horizontal growth of the epitaxial layer by adjusting the ratio of the raw materials to be supplied, the atmosphere gas, the pressure and the time. Depending on the equipment for the growth of the epitaxial layer, there may be a difference, but in the case of MOCVD equipment having a horizontal reactor, in general, the ratio of (group V source flow rate / group III source flow rate) may be increased or the growth pressure may be reduced. By increasing the growth temperature, the relative ratio of the horizontal growth rate to the vertical growth rate can be increased.

As shown in FIG. 7A, the epitaxial layer grows on the concave portion 11b and the side surface 11c of the irregularities formed by the substrate etching, and the growth mask pattern 30 is formed on the convex portion 11a formed of the horizontal plane. The epitaxial layer does not grow. The epitaxial layer grown on the concave and concave portions 11b and the side surfaces 11c may be vertically grown in the shape of a cross section of a triangular or trapezoidal shape at the top thereof, in order to reduce the penetration potential present in the semiconductor layer 40. desirable. That is, due to the triangular or trapezoidal inclined side surface of the semiconductor layer 40, the through dislocations can be significantly reduced in the horizontal direction during the horizontal growth step, thereby significantly reducing the through dislocations. In addition, as shown in FIG. 7B, the epitaxial layer vertically grown from the concave and concave portions 11b and the side surfaces 11c is horizontally grown and covered across the growth mask pattern 30 formed on the convex portion 11a. This vertical and horizontal growth proceeds and the epitaxial layer horizontally grown from the recesses 11b and the side surfaces 11c is sealed with the epitaxial layer horizontally grown from the adjacent recesses 11b and the side surfaces 11c and is shown in FIG. 7C. A continuous low defect semiconductor layer 40 is formed as shown.

As described above, the semiconductor layer formed by vertical and horizontal growth may reduce transmission of penetration potentials to the surface and may improve crystallinity of the semiconductor layer to increase internal quantum efficiency.

In addition, the uneven surfaces 11a, 11b, and 11c of the substrate having various angles and the growth mask pattern 30 may change light traveling directions at various angles to help extract light more easily. Therefore, the number of total reflection of the light generated in the active layer is reduced and the probability of being emitted to the outside increases, thereby significantly improving the external quantum efficiency.

8A to 8C illustrate another example of a semiconductor layer manufactured according to the present invention, in which an epitaxial layer grown in the vertical and horizontal directions as shown in FIG. 8A is sealed on the uneven convex portion 15a. As a result, a discontinuous semiconductor layer 41 can be formed, and the uneven structure 47 is formed on the surface of the continuous semiconductor layer 42 formed by sealing the epitaxial layers grown in the vertical and horizontal directions as shown in FIG. 8B. ), And as shown in FIGS. 8B and 8C, a seal cavity 45 may be formed in the continuous semiconductor layers 42 and 43 formed by sealing the epitaxial layer.

8A or 8B, when the surfaces of the semiconductor layers 41 and 42 are not continuous horizontal surfaces, the surface of the active layer of the light emitting diodes grown on the semiconductor layers 41 and 42 may have a continuous horizontal surface. The surface of the light emitting diode may also not be a continuous horizontal plane. That is, the active layer of the light emitting diode or the surface of the light emitting diode grown on the semiconductor layers 41 and 42 having the discontinuous or uneven structure may be formed as the discontinuous structure and the uneven structure. In this case, the extraction efficiency of the light emitting diode may be improved by reducing the number of total internal reflections of the light emitted from the active layer of the light emitting diode. In addition, when the active layer of the light emitting diode is formed with a concave-convex structure, it is possible to increase the light emitting area of the light because its volume increases compared to the active layer of the flat surface.

In addition, as shown in FIG. 8C, the cavity 45 formed inside the semiconductor layer 43 reflects, scatters, or scatters light, thereby reducing the total reflection amount in the interior, and increasing the extraction efficiency of the light emitting diode. .

9A to 9C illustrate another example of the semiconductor layer manufactured according to the present invention. The semiconductor layer 44 is formed without the growth mask pattern on the substrate 10 on which the unevenness 12a, 12b, 12c is formed. It may be formed. As shown in FIG. 9A, the epitaxial layer grows vertically in the cross-sectional shape of a triangular shape or a trapezoid from the recess 12b of the unevenness formed by etching the substrate 10, and as shown in FIG. 9B, the unevenness of the unevenness The epitaxial layer grown vertically from the portion 12b is horizontally grown across the side surface 12c of the unevenness and the convex portion 12a and covered. This vertical and horizontal growth proceeds and the epitaxial layer horizontally grown from the recess 12b is sealed with the epitaxial layer horizontally grown from the adjacent recess 12b to form a continuous low defect semiconductor layer as shown in FIG. 9C. Form 44. Here, the growth of the epitaxial layer is not limited to the vertical growth from the concave portion 12b of the unevenness, but also on the side surface 12c and the convex portion 12a. At this time, the epitaxial layers grown on the convex portion 12a, the concave portion 12b, and the side surface 12c forming the unevenness are grown at different growth rates depending on the growth conditions, that is, the unevenness 12a, 12b, 12c. Dominant vertical growth may occur from any portion of, and horizontal growth may occur from a portion where the leading vertical growth is made with a relatively small growth rate. In addition, the surface of the semiconductor layer 44 may be formed to include a discontinuous or uneven structure.

The manufacturing method of the semiconductor layer of this invention is not limited to what was mentioned above, A various correction and a change are possible. For example, as described above, the epitaxial layer grown from the concave and concave portions of the uneven surface during vertical growth is formed in a triangular or trapezoidal cross-sectional shape, but is not limited thereto, and the epitaxial layer may be formed in a rectangular cross-sectional shape. Can be.

Hereinafter, the present invention will be described in more detail with reference to Examples.

10 to 13 are optical micrographs and SEM pictures showing one embodiment according to the present invention.

First, an SiO ₂ etching mask is deposited on a sapphire (Al ₂ O ₃ ) substrate through a PECVD method. The thickness of the etching mask is preferably 100 to 2000Å, and may vary depending on the etching depth of the substrate, the material of the etching mask, the deposition method of the etching mask, and the deposition conditions. In addition, when the etching mask is used as a growth mask pattern for selective growth of the semiconductor layer, it may be deposited even thicker than this.

Next, after the photoresist is coated with a thickness of 1 μm or more on the etching mask, a photoresist pattern is formed through a photolithography process. In addition, a wet etching process using the photoresist pattern as a mask is performed by using a buffered-oxide etch (BOE), hydrofluoric acid (HF), or a dilute solution thereof to form the SiO 2 etching mask pattern.

Subsequently, the substrate is etched using the SiO ₂ etching mask pattern to form irregularities on the surface of the substrate. The unevenness of the surface of the sapphire substrate according to the present embodiment is formed by wet etching, and the etching solution consists of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), a mixed solution of sulfuric acid and phosphoric acid, or a dilute solution thereof. It is preferably selected from the group.

In this embodiment, the SiO ₂ etching mask pattern is formed in a stripe structure as shown in FIG. 4A, and the stripe structure is formed so that the longitudinal direction thereof is parallel to the <11-20> direction of the sapphire substrate crystal. In addition, the etching solution was a mixed solution of sulfuric acid and phosphoric acid having a volume ratio of sulfuric acid: phosphoric acid 3: 1, and wet etching was performed for 5 minutes at an etching temperature of 275 ℃.

FIG. 10 is an optical photomicrograph showing a cross section in the case where the unevenness 110a, 110b, 110c is formed on the surface of the substrate 100 by performing such wet etching. As can be seen in the figure, the unevenness (110a, 110b, 110c) formed on the surface of the substrate 100 includes a convex portion (110a) and a concave portion (110b) made of a horizontal plane, based on the concave portion (110b) Side 110c of an asymmetric cross-sectional shape with different slopes.

Even when the same etching mask pattern is used, etching cross-sectional shapes of various shapes can be obtained by varying the conditions of the pattern of the etching mask, the material of the etching solution, the mixing ratio of the etching solution, the etching temperature, and the etching time. For example, in the case of using an etching mask pattern having the same stripe structure as described above, the stripe structure has a longitudinal direction parallel to the <11-00> direction of the sapphire substrate crystal and is etched under the same etching conditions as above. By proceeding, the unevenness 111a, 111b, 111c having a cross-sectional shape as shown in FIG. 11A can be formed. That is, the irregularities 111a, 111b, and 111c formed on the substrate surface include a convex portion 111a and a concave portion 111b formed of a horizontal plane, and have a symmetrical cross-sectional shape having the same slope with respect to the concave portion 111b. Side 111c. In addition, when etching is performed using the same stripe etching mask pattern until the horizontal surface of the convex portion disappears under the same etching conditions as described above, as shown in the SEM photograph of FIG. 11B, the unevenness 112a, 112b, and 112c may be used. Convex portion 112a may be formed in the form of a line. As described above, the convex portion or the concave portion of the concave-convex portion may be formed in the form of a horizontal plane, a line or a point according to the etching conditions, and the side connecting the convex portion and the concave portion may be formed as a surface having a constant inclination or curvature, It may be formed of a plurality of faces having a curvature. Alternatively, the etching depth and width may be variously formed.

Next, a growth mask pattern for selectively growing a semiconductor layer is provided on a predetermined region of the substrate having irregularities as described above. The growth mask pattern may be used as it is without removing the etching mask pattern, or the growth mask pattern may be separately formed after removing the etching mask pattern. In this embodiment, the etching mask pattern was used as the growth mask pattern. Of course, the present invention is not limited thereto, and in the case where the convex portion of the unevenness is a line or a dot, it may proceed without a growth mask pattern.

Thereafter, a semiconductor layer is formed on the substrate on which the uneven and growth mask patterns are formed. As mentioned above, the growth of the semiconductor layer includes three growth stages. That is, in the first step, a low temperature nucleation layer or a low temperature buffer layer is deposited for growth of the epitaxial layer at an initial relatively low temperature, and in the second step, the upper part of the epitaxial layer is vertically grown in a triangular or trapezoidal cross-sectional shape. The third step is to grow the epitaxial layer horizontally. Vertical and horizontal growth of such epitaxial layers may continue until a flat, continuous semiconductor layer is formed.

To this end, the present embodiment grows a low temperature nucleation layer of gallium nitride (GaN) for 1 minute 45 seconds at a low temperature of 560 ℃ on the sapphire substrate on which the irregularities are formed. The gallium nitride epitaxial layer is grown on the low temperature nucleation layer for 60 minutes at a vertical growth temperature of 1020 ° C. Then, the gallium nitride epitaxial layer is grown for 120 minutes at a temperature at which the horizontal growth of 1160 ° C is active.

Fig. 12 is a cross-sectional photograph showing a vertically grown gallium nitride semiconductor layer in which the gallium nitride epitaxial layer is vertically grown from the concave and concave portions 110b and side surfaces 110c. FIG. 13 is a photo showing a vertically and horizontally grown gallium nitride semiconductor layer according to the present embodiment, and as the growth progresses, the gallium nitride epitaxial layer horizontally grown across the convex portion 110a is a growth mask on the convex portion 110a. It can be seen that the low defect gallium nitride semiconductor layer 400 is formed by covering the pattern and sealing the gallium nitride epitaxial layer horizontally grown from adjacent recesses 110b and side surfaces 110c. In addition, a seal cavity 450 may be included in the gallium nitride semiconductor layer 400 on the convex portion 110a.

14 to 16 are optical micrographs and SEM pictures showing another embodiment according to the present invention. This is performed through the same process as in the case of the above embodiment, the shape of the irregularities formed on the substrate using only the etching mask pattern of a different structure is different. The detailed description overlapping with the above will be omitted.

First, an SiO ₂ etching mask pattern is formed on a sapphire (Al ₂ O ₃ ) substrate, and then the substrate is etched using the same to form irregularities on the surface of the substrate.

In the present embodiment, the SiO ₂ etching mask pattern is formed to include a polygonal structure, that is, a rhombus pattern having an angle of 60 degrees and an angle of 120 degrees as shown in FIG. 4D. In addition, the etching solution was a mixed solution of sulfuric acid and phosphoric acid having a volume ratio of sulfuric acid: phosphoric acid 3: 1, and wet etching was performed for 5 minutes at an etching temperature of 275 ℃.

14 is a SEM photograph showing a cross section in the case where the unevenness 113a, 113b, and 113c are formed on the surface of the substrate by performing such wet etching. As can be seen in the figure, it is composed of the convex portion 113a and the inclined side surface 113c formed in a horizontal plane can form a truncated pyramidal irregularities.

As mentioned above, various shapes of the etching shapes may be obtained by changing the etching mask pattern, the material of the etching solution, the mixing ratio of the etching solution, the etching temperature, and the etching time. For example, when etching is performed under the same etching conditions using an etching mask pattern having a square structure as shown in FIG. 4C, as shown in the SEM photograph of FIG. 15A, a convex part formed of a horizontal plane is illustrated. Consists of a 114a and an inclined side surface 114c to form a truncated pyramid-shaped unevenness. In addition, when etching is performed until the horizontal surface of the convex portion disappears under the same etching conditions using the same etching mask pattern as that of the present embodiment, that is, an etching mask pattern having a rhombus, the optical micrograph of FIG. 15B. As can be seen from, the convex portion 115a may form a pyramid-shaped unevenness consisting of points. In addition, as shown in the SEM photograph of FIG. 15C, irregularities 116a, 116b, and 116c including side surfaces 116c formed of a plurality of surfaces having a predetermined slope or curvature may be formed. As such, various arrangement structures, patterns, or cross-sectional shapes of the unevenness may be formed according to the etching conditions.

Next, the semiconductor layer is formed on the substrate on which the uneven and growth mask patterns are formed using the etching mask pattern as a growth mask pattern. That is, a low temperature nucleation layer of gallium nitride (GaN) is grown on the sapphire substrate on which the unevenness is formed for 1 minute 45 seconds at a low temperature of 560 ° C. The gallium nitride epitaxial layer is grown on the low temperature nucleation layer for 60 minutes at a vertical growth temperature of 1020 ° C. Then, the gallium nitride epitaxial layer is grown for 120 minutes at a temperature at which the horizontal growth of 1160 ° C is active.

When the gallium nitride semiconductor layer is formed on a substrate on which truncated pyramidal irregularities 114a, 114b, and 114c are formed as shown in FIG. 14, FIG. 16 is a SEM photograph showing a vertically grown gallium nitride semiconductor layer. As can be seen in, the gallium nitride epitaxial layer is grown prominently from the concave and convex portions of the gallium nitride semiconductor layer 410 in the honeycomb form can be formed. Of course, in the case where the gallium nitride semiconductor layer is continuously vertically and horizontally grown on the substrate on which the unevennesses 114a, 114b, and 114c are formed, the horizontally grown epitaxial layer is sealed with the vertically and horizontally grown epitaxial layer in the adjacent substrate region. To form a flat, continuous low defect semiconductor layer.

17 and 18 are optical micrographs showing another embodiment according to the present invention. This is performed through the same process as in the case of the above embodiment, the shape of the irregularities formed on the substrate by only changing the etching conditions are different. The detailed description overlapping with the above will be omitted.

First, an SiO ₂ etching mask pattern is formed on a sapphire (Al ₂ O ₃ ) substrate, and then the substrate is etched using the same to form irregularities on the surface of the substrate.

In the present embodiment, the SiO ₂ etching mask pattern is formed to include a polygonal structure, that is, a rhombus pattern having an angle of 60 degrees and another angle of 120 degrees. In addition, the etching solution was a mixture solution of sulfuric acid and phosphoric acid having a volume ratio of sulfuric acid: phosphoric acid of 3: 1, and wet etching was performed for a relatively long time at an etching temperature of 275 ° C, that is, 15 minutes or longer.

FIG. 17 is an optical micrograph showing a cross section in the case where the irregularities 117a, 117b, and 117c are formed on the surface of the substrate by performing such wet etching. As can be seen in the figure, both the convex portion 117a and the concave portion 117b can form pyramidal irregularities 117a, 117b, and 117c.

In addition, when forming the gallium nitride semiconductor layer without a growth mask pattern on the substrate on which the convex portions 117a and the concave portions 117b are formed, the pyramidal irregularities 117a, 117b, and 117c are formed vertically. As can be seen in FIG. 18, an optical micrograph showing a grown gallium nitride semiconductor layer, the gallium nitride epitaxial layer is dominantly vertically grown and truncated from any part of the substrate formed by etching, i.e., a face, a line or a dot. A pyramid gallium nitride semiconductor layer 420 may be formed. Here, the semiconductor layers grown on the surfaces, lines, or dots forming the unevenness 117a, 117b, and 117c are grown at different growth rates according to the growth conditions, and arbitrary portions of the unevenness 117a, 117b, and 117c structures. In other words, horizontal growth may occur from a plane, a line or a point where the vertical vertical growth is performed, and a portion where the vertical vertical growth is relatively small. Of course, in the case where the gallium nitride semiconductor layer is continuously vertically and horizontally grown on the substrate on which the irregularities 117a, 117b, and 117c are formed, the horizontally grown epitaxial layer is sealed with the vertically and horizontally grown epitaxial layer in the adjacent substrate region. To form a flat, continuous low defect semiconductor layer.

19 and 20 illustrate partial cross-sectional views of gallium nitride semiconductor layers grown on a substrate on which a stripe-shaped concave-convex structure is formed in parallel with a <11-20> direction of a sapphire substrate crystal according to an embodiment of the present invention. Transmission Electron Microscopy).

Referring to FIG. 19, which shows the concave-convex portion and the gallium nitride semiconductor layer, it can be seen that the penetration potential 500 propagates from the interface between the concave-convex portion 110b and the gallium nitride semiconductor layer 400. In addition, it can be seen that the through dislocation 430 is bent to the inclined side surface 440 of the gallium nitride semiconductor layer 400 grown in a triangular cross-sectional shape. As a result, the density of the through dislocations may be reduced in the surface portion of the gallium nitride semiconductor layer growing vertically on the recess 110b.

In addition, referring to FIG. 20 which shows a cross section of the surface of the gallium nitride semiconductor layer 400 formed by growing horizontally on the convex portion of the unevenness, a penetration potential propagated in the vertical direction due to the horizontal growth of the gallium nitride semiconductor layer 400 It can be confirmed that it is not observed.

The manufacturing method of the semiconductor structure according to the present invention is not limited to the above, and various modifications and changes are possible. For example, the growth temperature is controlled for vertical and horizontal growth of the semiconductor layer at each stage for the growth of the semiconductor layer. have. In addition, in the above embodiment, the manufacturing of the gallium nitride semiconductor layer is illustrated, but the present invention is not limited thereto. In addition to the gallium nitride semiconductor as described above, a single crystal thin film of various compound semiconductors may be manufactured by changing a raw material. .

As described above, the present invention provides a convex portion formed in the form of a horizontal plane, a line or a point, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane or curved shape having a predetermined slope by connecting the convex portion and the concave part. By forming the low defect semiconductor layer by vertical and horizontal growth on the uneven substrate including the side surface of the semiconductor substrate, the crystal defects of the semiconductor light emitting diode grown on the semiconductor layer are reduced, thereby increasing the reliability of the light emitting diode and improving the internal quantum efficiency. Can be improved. In addition, the external quantum efficiency may be improved due to planar and curved shapes having various angles that are not perpendicular to the surface of the semiconductor layer in the uneven structure of the substrate or the growth mask pattern.

Hereinafter, a semiconductor light emitting diode and a method of manufacturing the same according to the present invention will be described.

The present invention is characterized by forming a semiconductor light emitting diode by growing a semiconductor layer manufactured according to the above-described process is reduced crystal defects and improved crystallinity.

21 and 22 are cross-sectional views showing examples of the semiconductor light emitting diode according to the present invention.

Referring to FIG. 21, a light emitting diode includes a substrate 1000 on which unevennesses 1100a, 1100b, and 1100c and a growth mask pattern 3000 are formed, a low defect semiconductor layer 4000 formed on the substrate 1000, and the semiconductor. The N-type semiconductor layer 5000, the active layer 6000, and the P-type semiconductor layer 7000 are sequentially formed on the layer 4000.

The manufacturing process of such a semiconductor light emitting diode will be described.

First, the low defect semiconductor layer 4000 as described above is formed on the substrate 1000. That is, a convex portion 1100a formed in the form of a horizontal plane, a line or a point, a concave portion 1100b formed in the form of a horizontal plane, a line or a point, and the convex portion 1100a are formed on the surface of the substrate 1000 by wet etching. And concave portions 1100b to form concave-convex including an inclined plane or curved side surface 1100c having a predetermined inclination, and then planar and continuous low defect semiconductor layer by vertical and horizontal growth thereon. To form 4000. Here, the growth of the semiconductor layer after the growth mask pattern 3000 is formed on the convex portion 1100a of the concave and convex portion 1100b for growth, but not limited thereto. The growth mask pattern 3000 may be omitted. The N-type semiconductor layer 5000, the active layer 6000, and the P-type semiconductor layer 7000 are sequentially formed on the low defect semiconductor layer 4000.

The N-type semiconductor layer 5000 is a layer in which electrons are generated, and uses a compound semiconductor layer doped with N-type impurities.

The active layer 6000 is a region where quantum wells are formed in a predetermined band gap and electrons and holes are recombined, and may include InGaN. In addition, the emission wavelength generated by the combination of electrons and holes is changed according to the type of material constituting the active layer 6000. Therefore, it is preferable to adjust the semiconductor material contained in the active layer 6000 according to the target wavelength.

In addition, the P-type semiconductor layer 7000 is a layer in which holes are formed, and uses a compound semiconductor layer doped with P-type impurities.

The material layers described above may be fabricated using a variety of deposition and growth methods, including organometallic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma chemical vapor deposition (PCVD), molecular beam growth (MBE), hydride vapor deposition (HVPE), and the like. Is formed through.

Next, as shown in FIG. 22, a portion of the N-type semiconductor layer 5000 is exposed by removing a portion of the P-type semiconductor layer 7000 and the active layer 6000 through a predetermined etching process. The P-type electrode 8000 and the N-type electrode 9000 are formed on the type semiconductor layer 7000 and the exposed N-type semiconductor layer 5000.

Between the P-type semiconductor layer 7000 and the P-type electrode 8000 to inject a uniform current into the entire region of the P-type semiconductor layer 7000 and the semiconductor light emitting diode with low resistance and improve light transmittance. The transparent electrode layer can be further formed in the. As the transparent electrode layer, indium tin oxide (ITO), ZnO, or a transparent metal having conductivity may be used. In addition, a separate ohmic metal layer for smoothly supplying current to the P-type semiconductor layer 7000 or the exposed N-type semiconductor layer 5000 before forming the P-type electrode 8000 and the N-type electrode 9000. May be further formed. Cr and Au may be used as the ohmic metal layer.

The above-described light emitting diode has formed an N-type semiconductor layer, an active layer, and a P-type semiconductor layer after forming a flat and continuous low defect semiconductor layer on the unevenly formed substrate, but is not limited thereto. Alternatively, the N-type semiconductor layer, the active layer, and the P-type semiconductor layer may be formed after the low defect semiconductor layer having the uneven structure is formed.

Referring to FIG. 23, a light emitting diode includes a substrate 2000 on which unevennesses 2100a, 2100b, and 2100c and a growth mask pattern 3100 are formed, and a low light including a uneven structure 4150 formed on the substrate 2000. The defect semiconductor layer 4100, an N-type semiconductor layer 5100, an active layer 6100, and a P-type semiconductor layer 7100 sequentially formed on the semiconductor layer 4100 are included.

As shown in the figure, as the growth on the semiconductor layer 4100 having the uneven structure 4150 can be formed in the active layer 6100 or the surface of the light emitting diode of the light emitting diode structure. In this case, the extraction efficiency of the light emitting diode can be improved by reducing the number of times the light emitted from the active layer 6100 of the light emitting diode is totally internally reflected inside the light emitting diode. In addition, when the active layer 6100 of the light emitting diode has a concave-convex structure, the light emitting area of the light may be increased because its volume increases compared to the active layer of the flat surface.

The light emitting diode of the present invention is not limited to the above description, and may be formed in various structures according to the characteristics of the device and the convenience of the process. For example, the N-type or P-type impurities may be doped into the low-defect semiconductor layer without forming an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the low-defect semiconductor layer. That is, it can be formed by doping N-type or P-type impurities from the beginning of growth or during the growth of the low defect semiconductor layer. In addition, a device having a flip chip structure can be manufactured. Also, as described above, the substrate is removed through a laser lift-off process without etching the P-type semiconductor layer and the active layer to form the N-type electrode, and then the N-type electrode is formed of the N-type semiconductor layer. By forming in the lower surface, the element of the structure perpendicular | vertical to a P-type electrode can be manufactured.

24 is a graph illustrating light emission characteristics of the semiconductor light emitting diode according to the present invention, and shows a result of measuring photoluminescence (PL) in a thin film state in which no electrode is formed. Comparative Example 1 shows a case where a semiconductor layer is formed on a planar substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are formed, and Example 1 forms a semiconductor layer on a substrate having the above-mentioned unevenness. And a case in which an N-type semiconductor layer, an active layer and a P-type semiconductor layer are formed. As can be seen in the drawing, Example 1 in which the semiconductor layer was grown on a substrate on which the unevenness was formed can be seen that the emission intensity was significantly higher than that of Comparative Example 1.

Table 1 shows the light emission characteristics of the semiconductor light emitting diode according to the present invention, and shows the results of measuring the EL (electroluminescence) output ratio for the structures in which the electrodes were formed on the N-type and P-type semiconductor layers. Comparative Example 2 shows a case in which a semiconductor layer is formed on a planar substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are formed. Examples 2, 3, and 4 show the above-mentioned uneven substrates. The case where a semiconductor layer is formed and an N type semiconductor layer, an active layer, and a P type semiconductor layer is shown. In Comparative Examples 2 and 2, 3, and 4, all conditions were the same except for the shape of the substrate surface and the growth conditions of the semiconductor layer, and the emission wavelength was 405 nm. The value compared with the light emission output of the light emitting diode of Comparative Example 2 as 1 is shown.

As can be seen in Table 1, Examples 2 to 5 in which the semiconductor layer was grown on the uneven substrate were higher in light emission output than Comparative Example 2 in which the semiconductor layer was grown on the planar substrate. In addition, in the case of Examples 2 and 3 in which the semiconductor layer was grown on the substrate on which the irregularities formed in the stripe structure were formed, the light output of the light emitting diode was higher as the convex portions of the irregularities were wider. This is because as the region growing horizontally on the convex portion of the unevenness becomes wider, the low defect region increases to increase the internal quantum efficiency. In addition, Example 4 in which the semiconductor layer is grown on a truncated pyramid-shaped concave-convex substrate is higher in light emission output than in Examples 2 and 3 in which the semiconductor layer is grown on a stripe concave-convex substrate. You can see that. This is because a semiconductor layer having better crystallinity is grown on a substrate having a greater angle of light dispersion or a truncated pyramid-shaped unevenness due to various angles in the truncated pyramidal uneven structure.

As mentioned above, although it demonstrated in detail using the preferable embodiment of this invention, the scope of the present invention is not limited to a specific embodiment and should be interpreted by the attached claim. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

The present invention can improve crystallinity by forming irregularities on the surface of the substrate through wet etching, and vertically and horizontally growing the semiconductor layer on the crystal surface of the substrate formed by etching to reduce the penetration potential of the semiconductor layer. This improves the internal quantum efficiency of the light emitting diode and ensures reliability. In addition, the extraction angle of the semiconductor light emitting diode may be improved due to the surface having various angles of the uneven or growth mask pattern of the substrate.

Claims (19)

As a semiconductor structure, Uneven substrate; And A semiconductor layer formed on the substrate, The unevenness may include a convex portion formed in the form of a horizontal plane, a line or a point, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane or a predetermined curvature having a predetermined slope by connecting the convex portion and the concave part. A semiconductor structure comprising a side of the curved shape having. The method according to claim 1, And a growth mask pattern formed on the convex portion of the unevenness. The method according to claim 2, The growth mask pattern is a semiconductor structure, characterized in that selected from the group consisting of SiO ₂ , SiO _x , SiN ₂ , SiN _x , SiO _x N _y or a metal material. The method according to any one of claims 1 to 3, The uneven structure is a semiconductor structure, characterized in that formed by wet etching. The method according to any one of claims 1 to 3, The unevenness is a semiconductor structure, characterized in that it comprises a pyramid or truncated pyramid-shaped unevenness. The method according to any one of claims 1 to 3, And the semiconductor layer comprises an epitaxial layer grown in a vertical direction from the recess and in a horizontal direction across the convex portion. The method according to any one of claims 1 to 3, The semiconductor layer is a semiconductor structure, characterized in that the discontinuous or uneven structure is formed on the surface. The method according to any one of claims 1 to 3, The substrate is a semiconductor structure, characterized in that selected from the group consisting of sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP or GaAs. The method according to any one of claims 1 to 3, The semiconductor layer is selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN or InAlGaN. Providing a substrate having irregularities formed thereon; And Forming a semiconductor layer on the substrate, The unevenness may include a convex portion formed in the form of a horizontal plane, a line or a point, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane or a predetermined curvature having a predetermined slope by connecting the convex portion and the concave part. The manufacturing method of the semiconductor structure characterized by including the curved surface shape which has. The method according to claim 10, After the step of preparing the substrate on which the irregularities are formed, Forming a growth mask pattern on the convex portion of the unevenness. The method according to claim 10, Providing the substrate on which the irregularities are formed, Forming an etching mask pattern on the planar substrate; And Forming a concave-convex by performing wet etching through the etching mask pattern. The method according to claim 12, The wet etching is performed in the group consisting of H ₂ SO ₄ , H ₃ PO ₄ , buffered-oxide etch (BOE), HF, HNO ₃ , KOH, NaCl, NaOH, KBrO ₃ solution, a mixed solution thereof, or a dilute solution thereof. Method for producing a semiconductor structure, characterized in that using the etching solution selected. The method according to claim 12, Forming the semiconductor layer, And growing an epitaxial layer in a vertical direction from the recess and in a horizontal direction across the convex portion. The method according to claim 14, Forming the semiconductor layer, Forming a low temperature nucleation layer or a low temperature buffer layer at a temperature of 400 to 800 ° C .; Vertically growing the epitaxial layer at a temperature of 900 to 1150 ° C .; And A method of manufacturing a semiconductor structure comprising the step of horizontally growing the epitaxial layer at a temperature of 1050 to 1200 ℃. Uneven substrate; A semiconductor layer formed on the substrate; And An N-type semiconductor layer, an active layer and a P-type semiconductor layer formed on the semiconductor layer, The unevenness may include a convex portion formed in the form of a horizontal plane, a line or a point, a concave portion formed in the form of a horizontal plane, a line or a point, and an inclined plane or a predetermined curvature having a predetermined slope by connecting the convex portion and the concave part. A semiconductor light emitting diode comprising a side surface having a curved shape. The method according to claim 16, And a growth mask pattern formed on the convex portion of the unevenness. The method according to claim 17, The growth mask pattern is a semiconductor light emitting diode, characterized in that selected from the group consisting of SiO ₂ , SiO _x , SiN ₂ , SiN _x , SiO _x N _y or a metal material. The method according to any one of claims 16 to 18, The semiconductor layer, the N-type semiconductor layer, the active layer or the P-type semiconductor layer is a semiconductor light emitting diode, characterized in that the discontinuous or irregularities on the surface.

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