KR100786777B1 - Method of manufacturing semiconductor - Google Patents

Abstract

The present invention includes a substrate on which the unevenness is formed and a semiconductor layer formed on the substrate, wherein the unevenness includes a convex portion formed in a horizontal plane and a concave portion formed in an inclined plane or curved side surface thereof. Provided are a manufacturing method and a semiconductor light emitting diode including the same. The unevenness may be formed by wet etching.

The present invention forms irregularities on the surface of the substrate through wet etching, vertically grows a semiconductor layer having a triangular or trapezoidal cross-sectional shape on a convex portion of the irregularities formed in a horizontal plane, and then horizontally grows the recessed portion to increase the penetration potential of the semiconductor layer. By reducing, there is an advantage that the low defect semiconductor layer can be grown in a simpler process, and the performance of the light emitting diode including the low defect semiconductor layer can be improved.

Semiconductor, epitaxial, uneven, penetration potential, horizontal growth, wet etching, light emitting diode, LED

Description

Method of manufacturing semiconductor structure

1 is a schematic cross-sectional view showing a conventional semiconductor light emitting diode.

2 to 6C are cross-sectional views illustrating a manufacturing process of a semiconductor structure in accordance with the present invention.

7A and 7B are optical micrographs showing a cross section of irregularities of this embodiment.

8 and 9 are optical micrographs showing a growth cross section of a gallium nitride semiconductor layer of this embodiment.

10A to 10C are TEM photographs showing a cross section of a gallium nitride semiconductor layer of this embodiment.

11 and 12 are cross-sectional views showing a semiconductor light emitting diode according to the present invention.

13 is a graph showing the light emission characteristics of a semiconductor light emitting diode according to the present invention.

<Explanation of symbols for main parts of the drawings>

10, 100, 1000: substrate

30, 300, 3000: semiconductor layer

4000: N-type semiconductor layer 5000: active layer

6000: P-type semiconductor layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor structure, and more particularly, to a method for manufacturing a semiconductor structure that can improve luminous efficiency and ensure reliability by reducing crystal defects and improving crystallinity of a semiconductor layer.

A light emitting diode (LED) refers to a device that makes a small number of carriers (electrons or holes) injected using a pn junction structure of a semiconductor and emits a predetermined light by recombination thereof. GaAs, AlGaAs, GaN Various colors may be realized by configuring a light emitting source by changing a compound semiconductor material such as InGaN and AlGaInP.

Among the compound semiconductors, the nitride semiconductor material exhibits excellent luminescence properties in the visible and UV regions, and is also used in high power, high frequency electronic devices. In particular, gallium nitride (GaN) has a direct transition bandgap of 3.4 eV at room temperature, and is combined with materials such as indium nitride (InN) and aluminum nitride (AlN) at 0.7 eV (InN) to 3.4 eV (GaN). ), Which has a direct energy band gap of up to 6.2 eV (AlN), which can emit light in a wide wavelength range from visible light to ultraviolet light.

1 is a schematic cross-sectional view showing a conventional semiconductor light emitting diode.

Referring to FIG. 1, a light emitting diode includes a substrate 1 and an N-type semiconductor layer 2, an active layer 3, and a P-type semiconductor layer 4 sequentially formed on the substrate 1. In addition, a portion of the P-type electrode 5 formed on the P-type semiconductor layer 4 and the N-type semiconductor layer 2 exposed by etching part of the P-type semiconductor layer 4 and the active layer 3 is exposed. The formed N-type electrode 6 is included. The P-type semiconductor layer 4 uses a semiconductor compound doped with P-type impurities, and the N-type semiconductor layer 2 uses a semiconductor compound doped with N-type impurities.

P-type and N-type semiconductor layers 4 and 2 formed on the upper and lower portions of the active layer 3 respectively supply current to the active layer 3 to emit light.

In order to improve the performance of the light emitting diode, the internal quantum efficiency in which electrons recombine holes to obtain a large amount of light from the current flowing inside, and the generated light is extracted to the outside of the light emitting diode The extraction efficiency must be high. To this end, a semiconductor layer with low crystal defects and excellent crystallinity is first grown on a substrate to increase the internal quantum efficiency of the light emitting diode, and light generated from the active layer is reflected only inside the light emitting diode, that is, total internal reflection. ), The extraction efficiency of the light emitting diode should be increased.

However, conventional nitride semiconductors do not have a lattice matched substrate, and the nitride semiconductor layer formed on the sapphire substrate has a high density of about 10 ⁹ to 10 ¹⁰ / cm ² due to the difference in lattice constants and thermal expansion coefficients of the sapphire and nitride semiconductor layers. Threading dislocation of a.

In addition, the planes in each direction formed by the substrate and the semiconductor layer of the conventional semiconductor light emitting diode are formed in parallel or perpendicular to each other, so that a large amount of light emitted from the active layer does not easily escape to the outside of the light emitting diode, causing total internal reflection inside. Circulated, absorbed and extinguished.

Accordingly, researches to improve the performance of light emitting diodes by reducing crystal defects and increasing extraction efficiency have been actively conducted. As a method for reducing crystal defects, a method of growing a semiconductor layer by horizontal growth is disclosed.

Epitaxial lateral overgrowth (ELO) technology can suppress the penetration into the surface by selectively growing the semiconductor layer vertically and horizontally according to the mask pattern and blocking the through potential in the horizontal growth region. Peneo-Epitaxy (PE), Cantilever Epitaxy (CE), Lateral Epitaxy on Pattened Sapphire (LEPS), etc. are all modified in the ELO technology to suppress penetration of penetration potential into the surface through horizontal growth. to be.

ELO technology grows a first semiconductor layer on a substrate, deposits a mask material to form a mask pattern by dry etching, and then grows the second semiconductor layer again. This technique can prevent the propagation of crystal defects by horizontal growth, but there is a hassle to dry etching to form a mask pattern, and then to grow the semiconductor layer again. In addition, since the horizontal growth is performed through the mask pattern when the second semiconductor layer is grown, crystallographic tilting of the second semiconductor layer due to the mask pattern may be intensified, thereby causing defects.

In the dry etching of the mask pattern, the same problem occurs in the case of the PE technology in which the semiconductor layer is grown after etching to the first semiconductor layer and a part of the substrate.

In addition, in the case of LEPS technology, in which a semiconductor layer is grown on a sapphire substrate having an uneven structure to increase external quantum efficiency, it is difficult to dry-etch the substrate, and the horizontal growth rate is larger than the horizontal growth area. A decrease in penetration potential due to growth cannot be expected. In addition, in order to form a flat surface by filling a high step of the semiconductor layer grown on the irregularities formed substrate, there is a problem that the specific growth conditions different from the existing and the growth time is long.

In the case of the CE technology in which the semiconductor layer grown on the convex portion of the unevenness is formed by horizontally growing and sealing the semiconductor layer grown on the concave portion using the substrate having the unevenness, there is a difficulty in dry etching the substrate as well. In addition, since the surface of the substrate on which the unevenness is formed is formed in parallel or perpendicular to the surface of the semiconductor layer, a large amount of light emitted from the active layer causes total reflection inside and does not escape to the outside of the light emitting diode.

The present invention is to solve the above problems, by forming a concave-convex on the surface of the substrate through wet etching, vertical growth of the semiconductor layer of the triangular or trapezoidal cross-sectional shape on the convex portion of the concave-convex consisting of a horizontal plane, and then over the concave It is an object of the present invention to provide a method for manufacturing a semiconductor structure that can be grown by a simpler process by growing horizontally to reduce the penetration potential of the semiconductor layer and improving the reliability of the light emitting diode.

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According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor structure, the method comprising: providing a substrate on which irregularities are formed; Forming a low temperature nucleation layer or a low temperature buffer layer at a temperature of 400 to 800 ° C., vertically growing the epitaxial layer at a temperature of 900 to 1150 ° C., and horizontally growing the epitaxial layer at a temperature of 1050 to 1200 ° C. Forming a semiconductor layer on the substrate, including; It includes, the irregularities include a concave portion consisting of a convex portion consisting of a horizontal plane and a side of the inclined plane or curved shape.

The preparing of the substrate on which the irregularities are formed may include forming an etching mask pattern on the planar substrate, performing wet etching through the etching mask pattern to form the irregularities, and removing the etching mask pattern. can do. The substrate may be selected from the group consisting of sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP or GaAs, the wet etching is H ₂ SO ₄ , H ₃ PO ₄ , BOE (buffered -oxide etch), HF, HNO ₃ , KOH, NaCl, NaOH, KBrO ₃ solution, a mixed solution of them or a dilution solution thereof may be used an etching solution selected from the group.

The epitaxial layer is preferably grown in a vertical direction from the convex portion and then in a horizontal direction across the concave portion.

The semiconductor layer may be formed by organometallic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam growth (MBE), or hydride vapor deposition (HVPE).

The semiconductor layer may be selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN or InAlGaN.

The present invention may further include forming an N-type semiconductor layer and a P-type semiconductor layer on the semiconductor layer.

Hereinafter, a semiconductor structure and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 to 5C are cross-sectional views illustrating a manufacturing process of a semiconductor structure according to the present invention.

Deposition and growth methods of the material layers described below include metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition (PECVD). Various methods can be used including Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like.

First, the board | substrate with predetermined unevenness | corrugation was provided in the surface. Here, the unevenness is characterized in that it comprises a concave portion consisting of a convex portion consisting of a horizontal plane and the side of the inclined plane or curved shape. That is, the cross-sectional shape of the concave portion of the unevenness is not a shape including a vertical or horizontal plane, but an inclined plane or curved shape having a predetermined slope.

Referring to FIG. 2, a layered etching mask 20 is deposited on the planar substrate 10. Sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP, GaAs and the like are used as the substrate 10, and SiO ₂ , SiO _x , and SiN are used as materials of the etching mask 20. ₂ , SiN _x , SiO _x N _y and the like are used. Of course, various materials may be used without being limited thereto.

Referring to FIG. 3, the etching mask 20 is wet or dry etched to form a mask pattern 25. To this end, a layered photoresist is coated on the etching mask 20, and then a photoresist pattern is formed through a photolithography process using a predetermined photo mask. The mask pattern 25 may be formed by performing an etching process using the photoresist pattern as a mask to remove a portion of the etching mask 20.

The mask pattern 25 may be formed in a stripe structure or in a lattice structure in which a plurality of stripes are all connected. Of course, the above-described mask pattern 25 is not limited thereto, and may be formed in various ways in a shape capable of forming irregularities including convex portions or concave portions.

Referring to FIG. 4A, wet etching is performed using the mask pattern 25 as an etch mask to form irregularities 11a and 11b on the surface of the substrate 10. The unevenness 11a and 11b includes a convex portion 11a formed of a horizontal plane and a concave portion 11b formed of an inclined plane or curved side surface. In addition, the lower portion of the concave-convex portion 11b is characterized in that the shape of the inclined plane, curved surface, line or point. That is, the concave-convex portion 11b is characterized in that it does not include a surface made parallel or perpendicular to the surface of the semiconductor layer.

When a predetermined surface of the concave-convex portion 11b of the unevenness is formed in parallel or perpendicular to the surface of the semiconductor layer, the light generated in the semiconductor layer is totally internally reflected through the interfaces formed in parallel or at right angles, and thus does not transmit to the outside. Reduces the extraction efficiency. Therefore, in order to increase the extraction efficiency of the light emitting diode, the smaller the area where the surface of the semiconductor layer and the surface of the substrate are formed to be parallel or perpendicular to each other is preferable.

The etched cross-sectional shape of the irregularities is formed in a symmetrical cross-sectional shape in which both sides of the concave portion 11b have the same slope as shown in FIG. 4A, or both sides of the concave portion 12b as shown in FIG. 4B. It can be formed into an asymmetric cross-sectional shape having different inclinations. In addition, as shown in FIG. 4C, the recess 13b is formed in a cross-sectional shape in which side surfaces having various inclinations are connected, or as shown in FIG. 4D, the sides of the recess 14b are formed in a cross-sectional shape of curved surfaces. can do. As described above, the etched cross-sectional shape of the irregularities may be formed in various shapes that do not include a surface that is formed parallel to or perpendicular to the surface of the semiconductor layer in the concave portion.

Unevenness can be formed by a simple wet etching process than the conventional dry etching, and the etching rate due to wet etching of the substrate varies greatly depending on the crystal direction of the substrate, so that the etching mask pattern, the mixing ratio of the etching solution, the etching temperature, and the etching time The shape of the etch cross section may be variously formed according to an etching parameter such as the like.

After the irregularities are formed on the surface of the substrate as described above, the etching mask pattern is removed through wet and dry etching.

5A to 5C, the semiconductor layer 30 is formed on the substrate 10 on which the unevennesses 11a and 11b are formed. The growth of the semiconductor layer 30 is a first step of forming a low-temperature nucleation layer or a low-temperature buffer layer, a second step of vertical growth of the epitaxial layer, and epitaxial And a third step in which the shallow layer grows horizontally. Other steps may be added in addition to these basic steps, and some of the steps may be changed or omitted.

Each step of manufacturing the semiconductor layer 30 is accomplished by controlling various thin film growth conditions, for example, by controlling the growth temperature. That is, in the case of using a low pressure MOCVD equipment, after forming a low temperature nucleation layer or a low temperature buffer layer for the growth of the epitaxial layer at a relatively low temperature of 400 to 800 ℃, the vertical of the epitaxial layer at a temperature of 900 to 1150 ℃ It is formed by promoting growth and by promoting horizontal growth of the epitaxial layer at a higher temperature of 1050-1200 ° C. This growth step may continue until a flat, continuous semiconductor layer is formed due to the vertical and horizontal growth of the epitaxial layer. Of course, the present invention is not limited thereto, and may be variously formed according to a desired purpose. For example, the surface of the semiconductor layer may not be flat, or horizontal growth may be performed, but not a continuous semiconductor layer may be formed.

In addition to the temperature conditions, it is possible to control the vertical growth and the horizontal growth of the epitaxial layer by adjusting the ratio of the raw materials to be supplied, the atmosphere gas, the pressure and the time. Depending on the equipment for the growth of the epitaxial layer, there may be a difference, but in the case of MOCVD equipment having a horizontal reactor, in general, the ratio of (group V source flow rate / group III source flow rate) may be increased or the growth pressure may be reduced. By increasing the growth temperature, horizontal growth can be promoted.

As can be seen in FIG. 5A, the epitaxial layer grows vertically in the triangular cross-sectional shape on the convex portion 11a of the uneven surface having the cross-sectional shape of the horizontal plane, and the uneven concave having the cross-sectional shape of the inclined plane ( An epitaxial layer also grows on 11b). The epitaxial layer may be vertically grown in a triangular or trapezoidal cross-sectional shape, which is desirable to reduce the penetration potential present in the semiconductor layer above the convex portion. That is, the through dislocations can be remarkably reduced by bending the through dislocations in the horizontal direction in the horizontal growth step due to the inclined sides of the triangles or trapezoids. In the figure, an epitaxial layer also grows on the recess 11b, but may not grow depending on growth conditions. In addition, as shown in FIG. 5B, the epitaxial layer formed on the convex portion 11a of the unevenness is horizontally grown across the concave portion 11b to cover the epitaxial layer grown on the concave portion 11b of the unevenness. do. The vertical and horizontal growth proceeds, and the epitaxial layer horizontally grown in the convex portion 11a is sealed with the epitaxial layer horizontally grown in the adjacent convex portion 11a and is flat and continuous low defect as shown in FIG. 5C. The semiconductor layer 30 is formed. Of course, the present invention is not limited thereto, and may be variously formed according to a desired purpose. For example, the surface of the semiconductor layer may not be flat, or horizontal growth may be performed, but not a continuous semiconductor layer may be formed.

At this time, the reason why the epitaxial layer grown on the convex portion 11a of the unevenness can grow horizontally to the top of the recessed portion 11b without being disturbed by the epitaxial layer grown on the concave portion 11b of the unevenness is This is because the growth rate, the growth direction, or the crystal direction of the epitaxial layer grown on the upper surfaces of the surfaces 11a and 11b are different from each other. That is, by forming the concave portion 11b of the concave-convex portion to be made of the inclined plane or the curved side surface instead of the horizontal plane, the convex portion of the concave-convex portion is induced by differently inducing the growth of the epitaxial layer grown on the concave portion 11b. It is possible to horizontally grow on the concave portion 11b without disturbing the epitaxial layer grown on 11a).

As described above, the semiconductor layer formed by the horizontal growth can reduce the transmission potential of the through dislocation to the surface, and can improve the crystallinity of the semiconductor layer.

In addition, the surface of the concave portion of the unevenness having various angles that are not parallel or perpendicular to the surface of the semiconductor layer changes the critical angle of the light to help extract the light more easily. Therefore, the number of total reflection of the light generated in the active layer is reduced and the probability of being emitted to the outside increases, thereby significantly improving the external quantum efficiency.

6A to 6C illustrate another example of a semiconductor layer manufactured according to the present invention. An epitaxial layer grown in the vertical and horizontal directions may be sealed between the convex portions to form a void. . As shown in Fig. 6A, the epitaxial layer grows vertically in a triangular cross-sectional shape on the convex portion 12a of the concave-convex portion having a horizontal cross-sectional shape, and the concave-convex portion having a cross-sectional shape of the inclined plane. An epitaxial layer also grows on (12b). 6B, the epitaxial layer formed on the convex part 12a of unevenness | corrugation grows horizontally across the recessed part 12b, and the epitaxial layer grown on the uneven part 12b of unevenness | corrugation was made. Covered. Referring to FIG. 6C, the epitaxial layer grown vertically and horizontally and horizontally grown at the convex portion 12a is sealed with the epitaxial layer horizontally grown at the adjacent convex portion 12a to form a flat and continuous low defect semiconductor layer. 30 is formed. In this case, the sealed semiconductor layer 30 may cover the recess 12b as it is and may include a recess cavity 15 formed on the recess 12b. In addition, the semiconductor device 30 may include a sealing unit cavity 35 sealed from an upper portion of the semiconductor layer 30 and formed in the semiconductor layer 30.

As such, the recess cavity 15 or the seal cavity 35 formed in the recess 12b or the semiconductor layer 30 reflects, scatters, or scatters light to reduce the total reflection in the inside, and the light emitting diode Can increase the extraction efficiency.

The manufacturing method of the semiconductor layer of this invention is not limited to what was mentioned above, A various correction and a change are possible. For example, although the epitaxial layer grown in the convex portion of the unevenness during vertical growth has been formed in a triangular or trapezoidal cross-sectional shape, the present invention is not limited thereto, and the epitaxial layer may be formed in a rectangular cross-sectional shape. .

Hereinafter, the present invention will be described in more detail with reference to Examples.

First, a layered etching mask is deposited on a planar substrate. As the substrate, sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP, GaAs, etc. may be used, and the present embodiment uses a crystal growth substrate composed of sapphire (Al ₂ O ₃ ). do. SiO ₂ etching mask is deposited on the sapphire substrate by PECVD method. The thickness of the etching mask is preferably 300 to 2000Å, and may vary depending on the etching depth of the substrate, the material of the etching mask, the deposition method of the etching mask, and the deposition conditions.

Next, a dry or wet etching process using the photoresist pattern as a mask is performed to form a mask pattern. To this end, in the present embodiment, after the photoresist is coated with a thickness of 1 μm or more on the etching mask, a photoresist pattern is formed through a photolithography process. In addition, a wet etching process using the photoresist pattern as an etching mask is performed using a buffered-oxide etch (BOE), hydrofluoric acid (HF), or a dilute solution thereof to form the SiO 2 mask pattern.

Subsequently, wet etching is performed on the substrate using the SiO ₂ mask pattern as an etching mask to form irregularities on the surface of the substrate. The unevenness of the surface of the sapphire substrate according to the present embodiment is formed by wet etching, and the etching solution consists of sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), a mixed solution of sulfuric acid and phosphoric acid, or a dilute solution thereof. It is preferably selected from the group.

As an etching solution for the wet etching of the substrate, an H ₂ SO ₄ or H ₃ PO ₄ solution may be used in the case of sapphire (Al ₂ O ₃ ) or GaN substrate, and a buffered oxide oxide (BOE) in the case of SiC substrate Or a HF solution, a buffered-oxide etch (BOE), HF, HNO ₃ or KOH solution can be used for a Si substrate, a NaCl solution can be used for a ZnO substrate, and a GaAs substrate. H ₂ SO ₄ , NaOH or HNO ₃ solution may be used, and a mixed solution of H ₂ SO ₄ and KBrO ₃ may be used in the case of GaP or InP substrates. Of course, not only the above-described etching solution, but also various other etching solutions may be used.

Since the etching rate due to the wet etching of the substrate varies greatly depending on the crystal direction of the substrate, various shapes of the etching cross-section may be formed according to etching parameters such as an etching mask pattern, a mixing ratio of the etching solution, an etching temperature, and an etching time.

The unevenness preferably includes a convex portion formed of a horizontal plane and a concave portion formed of an inclined flat or curved side surface. In addition, the lower portion of the recess is preferably in the shape of an inclined plane, curved surface, lines or points.

In this embodiment, the mask pattern is formed in a stripe structure, and the stripe structure is formed so that the longitudinal direction thereof is parallel to the <11-20> direction of the sapphire substrate crystal. As the etching solution, a mixture solution of sulfuric acid and phosphoric acid having a volume ratio of sulfuric acid: phosphoric acid is 3: 1, and wet etching was performed at an etching temperature of 275 ° C. for 30 minutes. FIG. 7A is an optical photomicrograph showing a cross section in the case where the irregularities 110a and 110b are formed on the surface of the substrate 100 by performing such wet etching. As can be seen in the figure, the unevenness (110a, 110b) formed on the surface of the substrate 100 has an asymmetric cross-sectional shape having different inclinations, the lower portion of the concave portion (110b) in the shape of a line rather than a horizontal plane Include.

Even when the same etching mask pattern is used, etching cross-sectional shapes of various shapes may be obtained by varying the conditions of the direction of the etching mask pattern, the material of the etching solution, the mixing ratio of the etching solution, the etching temperature, and the etching time. For example, in the case of using the mask pattern of the same stripe structure as described above, the longitudinal direction of the stripe structure is formed to be parallel to the <11-00> direction of the sapphire substrate crystal and etching is performed under the same etching conditions as described above. Proceeding, it is possible to form irregularities in the cross-sectional shape as shown in Fig. 7B. That is, the irregularities 120a and 120b formed on the surface of the substrate 100 have a symmetrical cross-sectional shape having the same inclination, and a lower portion thereof includes a recess 120b having a line shape rather than a horizontal plane.

As described above, the recesses of the unevenness may be formed as side surfaces having a constant inclination or curvature, or may be formed as side surfaces having various inclinations or curvatures, that is, the sidewalls having different inclinations or curvatures may be formed. Alternatively, the etching depth and width may be variously formed.

After the irregularities are formed on the surface of the substrate as described above, the etching mask pattern is removed through wet and dry etching. The SiO ₂ mask pattern of this embodiment is removed through wet etching using a buffered-oxide etch (BOE), hydrofluoric acid (HF) or a dilute solution thereof.

Next, a semiconductor layer is formed on the board | substrate with which the unevenness | corrugation was formed as mentioned above.

Examples of the semiconductor include GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and the like. In this embodiment, a GaN semiconductor layer is formed by using a metal-organic chemical vapor deposition (MOCVD) method. At this time, the atmosphere (carrier) gas and the source gas injected into the MOCVD equipment may be variously changed according to the semiconductor layer to be manufactured. That is, when the GaN semiconductor layer is formed as a semiconductor layer, nitrogen, hydrogen, or a mixed gas of nitrogen and hydrogen is used as an atmosphere gas, and trimethylgallium is used as a Ga source and ammonia (NH ₃ ) is used as an N source. To grow. Here, hydrogen or nitrogen may be used as an atmosphere gas, or hydrogen and nitrogen may be mixed and triethylgallium may be used instead of trimethylgallium as a Ga source, and N ₂ H may be used as an N source for ammonia. ₄ may be added and dimethylhyrazine may be used.

When the InN semiconductor layer is formed as the semiconductor layer, nitrogen is used as the atmosphere gas, and trimethylindium is used as the In source and ammonia (NH ₃ ) is used as the N source. Here, the atmosphere gas and the In source and the N source gas may be variously changed.

When the AlN single crystal thin film is formed as the semiconductor layer, hydrogen is used as an atmosphere gas, and trimethylaluminum as an Al source and ammonia (NH ₃ ) as an N source are grown. Here, the atmosphere gas and the Al source and the N source gas may be variously changed.

When the InGaN single crystal thin film is formed as the semiconductor layer, it is grown using nitrogen as an atmosphere gas, trimethyindium as an In source, trimethygallium as a Ga source, and ammonia (NH ₃ ) as an N source. do. Here, the atmosphere gas, the In source, the Ga source, and the N source gas may be variously changed.

When the AlGaN single crystal thin film is formed as the semiconductor layer, it is grown by using hydrogen as an atmosphere gas, trimethalum as an Al source, trimethygallium as a Ga source, and ammonia (NH ₃ ) as an N source. do. Here, of course, the atmosphere gas and the In source, Al source, Ga source and N source gas can be variously changed.

In the case of forming an InAlGaN single crystal thin film as the semiconductor layer, hydrogen or nitrogen is used as an atmosphere gas, trimethyindium is used as an In source, trimethyalumium is used as an Al source, and trimethygallium is used as a Ga source. And ammonia (NH ₃ ) as the N source. Here, of course, the atmosphere gas and the In source, Al source, Ga source and N source gas can be variously changed.

As mentioned above, the growth of the semiconductor layer includes three growth stages. In other words, in the first step, a seed for growing the epitaxial layer is formed at an initial relatively low temperature, in the second step, the epitaxial layer is vertically grown in a triangular or trapezoidal cross-sectional shape, and the third step is epitaxial. The tactile layer is grown horizontally. Vertical and horizontal growth of such epitaxial layers may continue until a flat, continuous semiconductor layer is formed.

To this end, the present embodiment grows a low temperature nucleation layer of gallium nitride (GaN) for 1 minute 45 seconds at a low temperature of 560 ℃ on the sapphire substrate on which the irregularities are formed. The gallium nitride epitaxial layer is grown on the low temperature nucleation layer for 60 minutes at a vertical growth temperature of 1020 ° C. Then, the gallium nitride epitaxial layer is grown for 120 minutes at a temperature at which the horizontal growth of 1160 ° C is active.

8 is a cross-sectional view showing a vertically grown gallium nitride semiconductor layer, the gallium nitride semiconductor layer 300 is grown in the convex portion (110a) and concave portion (110b) of the uneven. 9 is a photo showing a vertically and horizontally grown gallium nitride semiconductor layer, and as the growth progresses, the gallium nitride epitaxial layer grown horizontally across the concave portion 110b in the convex portion 110a is the concave portion 110b. It can be seen that the low-gap gallium nitride semiconductor layer 300 is formed by covering the gallium nitride epitaxial layer grown on the semiconductor layer and sealing the gallium nitride epitaxial layer grown horizontally in the adjacent convex portion 110a. In addition, the recess 110b or the gallium nitride semiconductor layer 300 may include a recess cavity 150 or a seal cavity 350.

The reason why the gallium nitride epitaxial layer grown in the convex portion 110a may be horizontally grown on the concave portion 110b without being disturbed by the gallium nitride epitaxial layer grown in the concave portion 110b may be unevenness 110a, This is because the growth rate, growth direction, or crystal direction of the epitaxial layer grown on the upper surfaces of the surfaces forming 110b) is different from each other.

10A to 10C are transmission electron microscopy (TEM) photographs showing a partial cross section of the gallium nitride semiconductor layer according to the present embodiment.

Referring to FIG. 10A, which shows the convex portion and the gallium nitride semiconductor layer of the unevenness, it can be seen that the penetration potential 400 propagates from the interface between the convex portion 110a and the gallium nitride semiconductor layer 300 of the unevenness. In addition, referring to FIG. 10B showing a cross section of the surface of the gallium nitride semiconductor layer 300 formed on the convex portion of the uneven portion, it can be seen that the density of the through dislocations is significantly reduced. Referring to FIG. 10C, which shows a cross-section of the sealed gallium nitride semiconductor layer 300, a sealing cavity cavity 350 is formed in the gallium nitride semiconductor layer 300, and the gallium nitride semiconductor layer 300 is horizontally grown. It can be seen that the penetration potential propagated in the vertical direction is not observed.

In each step of the present embodiment, the growth temperature is controlled for vertical and horizontal growth of the semiconductor layer.

The manufacturing method of the semiconductor structure according to the present invention is not limited to the above, and various modifications and changes are possible. For example, in the above embodiment, the manufacturing of the gallium nitride semiconductor layer is exemplified, but the present invention is not limited thereto. In addition to the gallium nitride semiconductor as described above, the present invention may be used to manufacture single crystal thin films of various compound semiconductors. Can be.

As described above, the present invention forms a semiconductor layer by horizontal growth on a substrate on which concave and convex portions formed of inclined flat or curved side surfaces are formed, thereby reducing crystal defects, thereby increasing reliability and improving internal quantum efficiency. . In addition, the external quantum efficiency may be improved due to the surface having various angles formed in the concave and convex portions of the concave-convex and not parallel or perpendicular to the surface of the semiconductor layer.

Hereinafter, a semiconductor light emitting diode and a method of manufacturing the same according to the present invention will be described.

The present invention is characterized by forming a semiconductor light emitting diode by growing a semiconductor layer manufactured according to the above-described process to reduce crystal defects and improve crystallinity.

11 and 12 are cross-sectional views illustrating a semiconductor light emitting diode according to the present invention.

Referring to FIG. 11, a light emitting diode includes a substrate 1000 on which unevennesses 1100a and 1100b are formed, a low defect semiconductor layer 3000 formed on the substrate 1000, and N formed sequentially on the semiconductor layer 3000. The semiconductor layer 4000 includes an active layer 5000, an active layer 5000, and a P-type semiconductor layer 6000.

The manufacturing process of such a semiconductor light emitting diode will be described.

First, the low defect semiconductor layer 3000 as described above is formed on the substrate 1000. That is, through the wet etching, the convex portion 1100a of the horizontal plane and the concave portion 1200b formed of the inclined plane or the curved side surface are formed on the surface of the substrate 1000, and then vertically and horizontally thereon. The semiconductor layer 3000 is formed by growth.

The N-type semiconductor layer 4000, the active layer 5000, and the P-type semiconductor layer 6000 are sequentially formed on the low defect semiconductor layer 3000.

The N-type semiconductor layer 4000 is a layer in which electrons are generated, and uses a compound semiconductor layer doped with N-type impurities.

The active layer 5000 is a region in which a predetermined band gap and a quantum well are made to recombine electrons and holes, and may include InGaN. In addition, the emission wavelength generated by the combination of electrons and holes is changed according to the type of material constituting the active layer 5000. Therefore, it is preferable to adjust the semiconductor material included in the active layer 5000 according to the target wavelength.

In addition, the P-type semiconductor layer 6000 is a layer in which holes are formed, and uses a compound semiconductor layer doped with P-type impurities.

The material layers described above may be fabricated using a variety of deposition and growth methods, including organometallic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma chemical vapor deposition (PCVD), molecular beam growth (MBE), hydride vapor deposition (HVPE), and the like. Is formed through.

Next, as shown in FIG. 12, a portion of the N-type semiconductor layer 4000 is exposed by removing a portion of the P-type semiconductor layer 6000 and the active layer 5000 through a predetermined etching process. The P-type electrode 7000 and the N-type electrode 8000 are formed on the type semiconductor layer 6000 and the exposed N-type semiconductor layer 4000.

A transparent electrode layer is disposed between the P-type semiconductor layer 6000 and the P-type electrode 7000 to inject a uniform current into the P-type semiconductor layer 6000 in a large area with low resistance and improve light transmittance. It can form more. As the transparent electrode layer, indium tin oxide (ITO), ZnO, or a transparent metal having conductivity may be used. In addition, a separate ohmic metal layer for smoothly supplying current to the P-type semiconductor layer 6000 or the exposed N-type semiconductor layer 4000 before forming the P-type electrode 7000 and the N-type electrode 8000. May be further formed. Cr and Au may be used as the ohmic metal layer.

The light emitting diode of the present invention is not limited to the above description, and may be formed in various structures according to the characteristics of the device and the convenience of the process. For example, the N-type or P-type impurities may be doped into the low-defect semiconductor layer without forming an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the low-defect semiconductor layer. That is, it can be formed by doping N-type or P-type impurities from the beginning of growth or during the growth of the low defect semiconductor layer. In addition, a device having a flip chip structure can be manufactured. Also, as described above, the substrate is removed through a laser lift-off process without etching the P-type semiconductor layer and the active layer to form the N-type electrode, and then the N-type electrode is formed of the N-type semiconductor layer. By forming in the lower surface, the element of the structure perpendicular | vertical to a P-type electrode can be manufactured.

FIG. 13 is a graph showing light emission characteristics of a semiconductor light emitting diode according to the present invention, and shows a result of measuring photoluminescence (PL) in a thin film state in which no electrode is formed. Comparative Example 1 shows a case where a semiconductor layer is formed on a planar substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are formed. Example 1 forms a semiconductor layer on a substrate on which unevenness is formed, and N The case where a type semiconductor layer, an active layer, and a P type semiconductor layer were formed is shown. As can be seen in the drawing, Example 1 in which the semiconductor layer was grown on a substrate on which the unevenness was formed can be seen that the emission intensity was significantly higher than that of Comparative Example 1.

Table 1 shows the light emission characteristics of the semiconductor light emitting diode according to the present invention, and shows the result of measuring the EL (electroluminescence) output ratio with respect to the structure in which the electrode was formed. Comparative Example 2 shows a case where a semiconductor layer is formed on a planar substrate, and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer are formed. Examples 2, 3, and 4 show a semiconductor layer on a substrate on which irregularities are formed. The case where it forms and the N type semiconductor layer, the active layer, and the P type semiconductor layer is shown. In Comparative Examples 2 and 2, 3, and 4, all conditions were the same except for the shape of the substrate surface and the growth conditions of the semiconductor layer, and the emission wavelength was 405 nm. The value compared with the light emission output of the light emitting diode of Comparative Example 2 as 1 is shown.

As can be seen in Table 1, Examples 2, 3, and 4 in which the semiconductor layer was grown on the substrate on which the irregularities were formed can be seen that the luminous output is higher than that of Comparative Example 2. In addition, it can be seen that the light output is higher as the width of the concave portion of the unevenness becomes relatively wider. This is because, due to the semiconductor layer growing horizontally over the recesses of the unevenness, crystal defects are reduced to increase the internal quantum efficiency. This is because the external quantum efficiency is increased due to the surfaces having various angles formed in the recesses of the unevenness.

As mentioned above, although this invention was demonstrated in detail using the preferable Example, the scope of the present invention is not limited to a specific Example and should be interpreted by the attached Claim. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

The present invention forms irregularities on the surface of the substrate through wet etching, vertically grows a semiconductor layer having a triangular or trapezoidal cross-sectional shape on a convex portion of the irregularities formed in a horizontal plane, and then horizontally grows the recessed portion to increase the penetration potential of the semiconductor layer. Can be reduced to improve crystallinity. This improves the internal quantum efficiency of the light emitting diode and ensures reliability. In addition, the extraction efficiency can be improved due to the surface having various angles which are formed in the concave and convex portions of the uneven surface and are not parallel or perpendicular to the surface of the semiconductor layer.

Claims (20)

delete delete delete delete delete delete delete delete delete delete Providing a substrate having irregularities formed thereon; Forming a low temperature nucleation layer or a low temperature buffer layer at a temperature of 400 to 800 ° C., vertically growing the epitaxial layer at a temperature of 900 to 1150 ° C., and horizontally growing the epitaxial layer at a temperature of 1050 to 1200 ° C. Forming a semiconductor layer on the substrate, including; Including, The unevenness is a manufacturing method of a semiconductor structure, characterized in that it comprises a concave portion consisting of a convex portion consisting of a horizontal plane and an inclined plane or curved side. The method according to claim 11, Providing the substrate on which the irregularities are formed, Forming an etching mask pattern on the planar substrate; Performing wet etching through the etching mask pattern to form irregularities; And Removing the etch mask pattern. The method according to claim 12, The substrate is a method of manufacturing a semiconductor structure, characterized in that selected from the group consisting of sapphire (Al ₂ O ₃ ), GaN, SiC, ZnO, Si, GaP, InP or GaAs. The method according to claim 13, The wet etching is performed in the group consisting of H ₂ SO ₄ , H ₃ PO ₄ , buffered-oxide etch (BOE), HF, HNO ₃ , KOH, NaCl, NaOH, KBrO ₃ solution, a mixed solution thereof, or a dilute solution thereof. Method for producing a semiconductor structure, characterized in that using the etching solution selected. The method according to claim 11, And wherein the epitaxial layer is grown in a vertical direction from the convex portion and then in a horizontal direction across the concave portion. delete The method according to any one of claims 11 to 14, The forming of the semiconductor layer may include organometallic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam growth (MBE), or hydride vapor deposition (HVPE). The manufacturing method of the semiconductor structure. The method according to any one of claims 11 to 14, The semiconductor layer is a method of manufacturing a semiconductor structure, characterized in that selected from the group consisting of GaN, InN, AlN, InGaN, AlGaN or InAlGaN. The method according to any one of claims 11 to 14, Forming an N-type semiconductor layer and a P-type semiconductor layer on the semiconductor layer. delete

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