KR20070112064A - 제어 가능한 위상을 가지는 주기성 전기 신호를 발생하는방법 및 회로 장치 - Google Patents
제어 가능한 위상을 가지는 주기성 전기 신호를 발생하는방법 및 회로 장치 Download PDFInfo
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- KR20070112064A KR20070112064A KR1020070048820A KR20070048820A KR20070112064A KR 20070112064 A KR20070112064 A KR 20070112064A KR 1020070048820 A KR1020070048820 A KR 1020070048820A KR 20070048820 A KR20070048820 A KR 20070048820A KR 20070112064 A KR20070112064 A KR 20070112064A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000000737 periodic effect Effects 0.000 title abstract description 3
- 238000010586 diagram Methods 0.000 description 11
- 230000001105 regulatory effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45361—Indexing scheme relating to differential amplifiers the AAC comprising multiple transistors parallel coupled at their drains only, e.g. in a cascode dif amp, only those forming the composite common source transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45504—Indexing scheme relating to differential amplifiers the CSC comprising more than one switch
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors
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- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
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Abstract
Description
s1의 위상: | s2의 위상: | s1*의 위상: | s2*의 위상: | x: | x*: | P: |
0°또는 240° | 120°또는 0° | 300° | 60° | 0 또는 8 | 4 | 0° |
0° | 120° | 300° | 60° | 1 | 5 | 15° |
0° | 120° | 300° | 60° | 2 | 6 | 30° |
0° | 120° | 300° | 60° | 3 | 7 | 45° |
0° | 120° | 300°또는 60° | 각기 60° 또는 180° | 4 | 각기 8 또는 0 | 60° |
0° | 120° | 60° | 180° | 5 | 1 | 75° |
0° | 120° | 60° | 180° | 6 | 2 | 90° |
0° | 120° | 60° | 180° | 7 | 3 | 105° |
0°또는 120° | 각기 120° 또는 240° | 60° | 180° | 각기 8 또는 0 | 4 | 120° |
Claims (6)
- 지정된 주파수 및 제어신호(x)에 의존하는 위상 P를 가지는 전기 출력신호(sout)를, 지정된 주파수를 가지지만 입력신호 위상들은 서로 다른 수 개의 입력신호들(s1, s2, s1*, s2*)의 가중 중첩으로서, 제어신호(x)에 의해 각기 조절되는 조절 가능 트랜스컨덕턴스 단들로서 각각에 입력신호들(s1, s2, s1*, s2*) 중의 하나가 공급되는 병렬 배치구성의 조절 가능 트랜스컨덕턴스 단들에 적용되는 가중 중첩에 의하여 발생하는 방법에 있어서,제1 입력신호(s1)의 제1 입력신호 위상 및 제2 입력신호 위상이 위상차만큼 더 큰 제2 입력신호(s2)의 제2 입력신호 위상 사이에 놓이는 위상 P를 가지는 출력신호(sout)를 발생할 때, 제1 입력신호(s1)와 제2 입력신호(s2) 및 2개의 추가의 입력신호들(s1*, s2*)은 가중 형태로 중첩되고, 그것에 의해, 2개의 추가의 입력신호들(s1*, s2*)은 위상차만큼 다른 위상들을 가지고 제1 및 제2 입력신호들(s1, s2)에 관하여 위상차의 절반만큼 위상 편이되는 방법.
- 제1항에 있어서, 360°범위에 걸쳐 등거리로 분포된 고정 지정된 입력 위상들을 가지는 복수 개의 입력신호들이 제공되고, 제어신호(x)에 의존하여, 이 복수 개의 입력신호들의 부분(s1, s2, s1*, s2*)이 가중 중첩을 위해 선택되고 사용되는 방법.
- 제1항 또는 제2항에 있어서, 위상차는 120°인 방법.
- 제1항 또는 제2항에 있어서, 제어신호(x)는 디지털 신호이고 출력신호(sout)의 위상 P는 이산적인 위상 단(stage)들에서 발생되는 방법.
- 제1항 또는 제2항에 있어서, 가중 중첩을 위해 항상 영과는 다른 가중치들의 제1 및 제2 입력신호들(s1, s2) 및 추가의 입력신호들(s1*, s2*)이 제공되는 방법.
- 지정된 주파수 및 제어신호에 의존하는 위상을 가지는 전기 출력신호를 발생하는 회로 장치에 있어서, 상기 회로 장치는,제어신호를 입력하기 위한 제어신호 입력단,지정된 주파수 및 각기 다른 입력신호 위상들을 가지는 수개의 입력신호들을 입력하기 위한 입력신호 입력단, 및입력신호들의 가중 중첩으로서, 트랜스컨덕턴스 단들이 제어신호에 의해 개별적으로 제어되고 입력신호들 중의 하나는 트랜스컨덕턴스 단들에 개별적으로 공급되게 하는 가중 중첩에 의하여 출력신호들을 발생하기 위한 병렬 배치구성의 조절가능 트랜스컨덕턴스 단들을 포함하며,제1 입력신호(s1)의 제1 입력신호 위상 및 제2 입력신호 위상이 위상차만큼 더 큰 제2 입력신호(s2)의 제2 입력신호 위상 사이에 놓이는 위상 P를 가지는 출력신호(sout)를 발생할 때, 제1 입력신호(s1)와 제2 입력신호(s2) 및 2개의 추가의 입력신호들(s1*, s2*)은 가중 형태로 중첩되고, 그것에 의해, 2개의 추가의 입력신호들(s1*, s2*)은 위상차만큼 다른 위상들을 가지고 제1 및 제2 입력신호들(s1, s2)에 관하여 위상차의 절반만큼 위상 편이되는 것을 특징으로 하는 회로 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102006023695A DE102006023695B4 (de) | 2006-05-19 | 2006-05-19 | Verfahren und Schaltungsanordnung zur Erzeugung eines periodischen elektrischen Signals mit steuerbarer Phase |
DE102006023695.5 | 2006-05-19 |
Publications (2)
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KR20070112064A true KR20070112064A (ko) | 2007-11-22 |
KR100877364B1 KR100877364B1 (ko) | 2009-01-09 |
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KR1020070048820A KR100877364B1 (ko) | 2006-05-19 | 2007-05-18 | 제어 가능한 위상을 가지는 주기성 전기 신호를 발생하는방법 및 회로 장치 |
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Country | Link |
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US (1) | US7579891B2 (ko) |
JP (1) | JP4718514B2 (ko) |
KR (1) | KR100877364B1 (ko) |
DE (1) | DE102006023695B4 (ko) |
TW (1) | TWI343187B (ko) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US7750707B2 (en) * | 2008-03-17 | 2010-07-06 | Broadcom Corporation | High-resolution low-interconnect phase rotator |
US7928788B2 (en) * | 2008-07-31 | 2011-04-19 | Freescale Semiconductor, Inc. | Double-balanced sinusoidal mixing phase interpolator circuit and method |
US7764091B2 (en) * | 2008-07-31 | 2010-07-27 | Freescale Semiconductor, Inc. | Square to pseudo-sinusoidal clock conversion circuit and method |
US7994837B1 (en) * | 2009-08-07 | 2011-08-09 | Altera Corporation | Techniques for phase interpolation |
JP6372166B2 (ja) * | 2014-05-27 | 2018-08-15 | 富士通株式会社 | 位相補間器 |
US9356588B2 (en) * | 2014-06-09 | 2016-05-31 | Qualcomm Incorporated | Linearity of phase interpolators using capacitive elements |
US9485084B2 (en) * | 2014-06-09 | 2016-11-01 | Qualcomm Incorporated | Linearity of phase interpolators by combining current coding and size coding |
US9160345B1 (en) * | 2014-09-04 | 2015-10-13 | Inphi Corporation | Phase interpolator |
EP3244532A1 (en) * | 2016-05-10 | 2017-11-15 | Université de Strasbourg | Magnetic operational amplifier |
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GB9721384D0 (en) * | 1997-10-08 | 1997-12-10 | Phoenix Vlsi Consultants | Phase locked loop |
US6943606B2 (en) * | 2001-06-27 | 2005-09-13 | Intel Corporation | Phase interpolator to interpolate between a plurality of clock phases |
US7180352B2 (en) * | 2001-06-28 | 2007-02-20 | Intel Corporation | Clock recovery using clock phase interpolator |
KR100630343B1 (ko) * | 2004-07-14 | 2006-09-29 | 삼성전자주식회사 | 아날로그 위상 보간 기술을 이용한 클록 데이터 복원 회로및 그 동작 방법 |
US7298195B2 (en) * | 2005-03-31 | 2007-11-20 | Agere Systems Inc. | Methods and apparatus for improved phase switching and linearity in an analog phase interpolator |
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- 2006-05-19 DE DE102006023695A patent/DE102006023695B4/de not_active Expired - Fee Related
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2007
- 2007-05-08 US US11/745,790 patent/US7579891B2/en active Active
- 2007-05-16 TW TW096117347A patent/TWI343187B/zh active
- 2007-05-17 JP JP2007131469A patent/JP4718514B2/ja active Active
- 2007-05-18 KR KR1020070048820A patent/KR100877364B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
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TW200746643A (en) | 2007-12-16 |
KR100877364B1 (ko) | 2009-01-09 |
DE102006023695B4 (de) | 2010-04-08 |
JP2007312394A (ja) | 2007-11-29 |
US7579891B2 (en) | 2009-08-25 |
US20070268060A1 (en) | 2007-11-22 |
TWI343187B (en) | 2011-06-01 |
JP4718514B2 (ja) | 2011-07-06 |
DE102006023695A1 (de) | 2007-11-22 |
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