KR20070002576A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR20070002576A
KR20070002576A KR1020050058170A KR20050058170A KR20070002576A KR 20070002576 A KR20070002576 A KR 20070002576A KR 1020050058170 A KR1020050058170 A KR 1020050058170A KR 20050058170 A KR20050058170 A KR 20050058170A KR 20070002576 A KR20070002576 A KR 20070002576A
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channel
ion implantation
substrate
semiconductor device
groove
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KR1020050058170A
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Korean (ko)
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김용택
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주식회사 하이닉스반도체
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Publication of KR20070002576A publication Critical patent/KR20070002576A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to prevent the increase of threshold voltage at edges of a channel by using two-step of tilt ion implantation processes to have different doping concentration in the channel edges. A groove(23) is formed by recessing a channel forming region of a substrate(21). Dopants for controlling threshold voltage of a channel are implanted into the substrate. At this time, two-step of tilt ion implantation processes while rotating the substrate to 180 degree are performed, so that the doping concentration at the channel edge portion is lower than the doping concentration at the channel center portion.

Description

반도체 소자의 제조방법{METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따라 형성된 반도체 소자를 도시한 단면도.1 is a cross-sectional view showing a semiconductor device formed according to the prior art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.2A to 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 반도체기판 22 : 소자분리막21 semiconductor substrate 22 device isolation film

23 : 홈 24 : 스크린산화막 23: home 24: screen oxide film

25 : 게이트절연막 26 : 게이트도전막 25 gate insulating film 26 gate conductive film

27 : 하드마스크막 28 : 게이트27: hard mask film 28: gate

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 소자의 tWR(Write Recovery Time) 특성을 개선할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that can improve the write recovery time (tWR) characteristics of the device.

최근, 고집적 모스펫(MOSFET) 소자의 디자인 룰이 100nm급 이하로 급격히 감소함에 따라 그에 대응하는 셀 트랜지스터의 채널 길이도 매우 감소되는 실정이다. 또한, 반도체기판의 도핑 농도 증가로 인한 전계(Electric field) 증가에 따른 접합 누설 전류 증가 현상으로 인해 기존의 플래너(planer) 채널 구조를 갖는 트랜지스터의 구조로는 리프레쉬 특성을 향상시키는 데 그 한계점에 이르렀다. 이에 따라, 유효 채널 길이(effective channel length)를 확보할 수 있는 다양한 형태의 리세스 채널(recess channel)을 갖는 모스펫 소자의 구현에 대한 아이디어 및 실제 공정개발 연구가 활발히 진행되고 있다.Recently, as the design rule of a high-density MOSFET device rapidly decreases to 100 nm or less, the channel length of a corresponding cell transistor is also greatly reduced. In addition, due to the increase in the junction leakage current due to the increase in the electric field due to the increased doping concentration of the semiconductor substrate, the transistor structure having the planar channel structure has reached the limit of improving the refresh characteristics. . Accordingly, studies on the implementation of the MOSFET and the actual process development research have been actively conducted on the implementation of a MOSFET having various types of recess channels capable of securing an effective channel length.

도 1은 종래 기술에 따라 형성된 리세스 채널을 갖는 반도체 소자의 단면도로서, 이를 설명하면 다음과 같다. 1 is a cross-sectional view of a semiconductor device having a recess channel formed according to the prior art, which will be described below.

도 1을 참조하면, 소자분리막(2)이 구비된 반도체기판(1)의 게이트 형성 영역을 리세스하여 홈(3)을 형성하고, 상기 홈(3)을 포함하는 기판 전면 상에 채널 문턱전압 조절을 위한 불순물 이온주입을 수행한다. 그런다음, 상기 기판 결과물 전면 상에 게이트절연막(4), 게이트도전막(5) 및 하드마스크막(6)을 차례로 형성하고, 상기 하드마스크막(6)을 패터닝한 후, 패터닝된 하드마스크막(6)을 식각장벽으로 이용해서 게이트도전막(5)과 게이트절연막(4)을 순차로 식각하여 게이트(7)를 형성한다. Referring to FIG. 1, a groove 3 is formed by recessing a gate formation region of a semiconductor substrate 1 having an isolation layer 2, and a channel threshold voltage on the entire surface of the substrate including the groove 3. Impurity ion implantation is performed for regulation. Then, the gate insulating film 4, the gate conductive film 5, and the hard mask film 6 are sequentially formed on the entire surface of the substrate resultant, the hard mask film 6 is patterned, and then the patterned hard mask film is patterned. The gate 7 is formed by sequentially etching the gate conductive film 5 and the gate insulating film 4 using (6) as an etch barrier.

이후, 도시하지는 않았지만, 상기 게이트(7) 양측에 소오스/드레인 접합영역을 형성하고, 계속해서, 공지된 일련의 후속 공정을 차례로 진행하여 반도체 소자를 제조한다. Subsequently, although not shown, a source / drain junction region is formed on both sides of the gate 7, and then a series of well-known subsequent steps are sequentially performed to manufacture a semiconductor device.

상기한 바와 같이, 리세스 게이트(7)를 형성하게 되면, 채널 도핑 농도를 줄일 수 있어 누설 전류가 감소되므로 데이터 유지 시간을 증가시킬 수 있고, 채널의 유효 길이가 증가되어 소자의 특성이 향상된다. As described above, when the recess gate 7 is formed, the channel doping concentration can be reduced and the leakage current can be reduced, thereby increasing the data retention time, and the effective length of the channel is increased, thereby improving device characteristics. .

그러나, 종래 기술에 따른 리세스 채널을 갖는 반도체 소자에서는, 상기 홈(3) 저면에 대응하는 채널영역과 게이트(7) 양측의 소오스/드레인 접합영역이 접하는 부분, 즉, 홈(3)의 저면에 대응하는 채널의 양측 가장자리(도 1에서 E영역)영역에서 전계가 분산되어, 국부적으로 문턱전압이 증가하므로, 소자의 tWR(Write Recovery Time) 특성이 열화되는 문제점이 있다. However, in the semiconductor device having the recess channel according to the related art, the portion where the channel region corresponding to the bottom surface of the groove 3 and the source / drain junction region on both sides of the gate 7 contact each other, that is, the bottom surface of the groove 3 Since the electric field is dispersed in both edge regions (region E in FIG. 1) of the channel corresponding to the local voltage and the threshold voltage is locally increased, the write recovery time (tWR) characteristic of the device is deteriorated.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 소자의 tWR(Write Recovery Time) 특성을 개선할 수 있는 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a recess gate that can improve the write recovery time (tWR) characteristics of the device, which is devised to solve the conventional problems as described above. .

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 반도체기판의 채널 형성 영역을 리세스하여 홈을 형성하는 단계; 및 상기 홈을 포함한 기판 전면 상에 채널 문턱전압 조절을 위해 불순물을 이온주입하는 단계;를 포함하는 반도체 소자의 제조방법에 있어서, 상기 불순물 이온주입은 경사 이온주입으로 수행하되, 기판을 180°회전시키면서 2회 수행하여 상기 홈의 양측 가장자리부분 하부의 채널 영역의 도핑농도가 채널 중앙부의 도핑농도 보다 낮아지도록 수행하는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: recessing a channel formation region of a semiconductor substrate to form a groove; And implanting impurities on the entire surface of the substrate including the grooves to control channel threshold voltages, wherein the implantation of the impurity ions is performed by gradient ion implantation, and the substrate is rotated 180 °. While performing twice, the doping concentration of the channel region under both side edge portions of the groove is lower than the doping concentration of the channel center portion.

여기서, 상기 불순물 이온주입은 B, BF2 및 In로 구성된 그룹으로부터 선택되는 어느 하나의 도펀트를 사용하여 수행한다.Here, the impurity ion implantation is performed using any one dopant selected from the group consisting of B, BF 2 and In.

또한, 상기 경사 이온주입은 3∼10°각도로 수행한다.In addition, the gradient ion implantation is performed at an angle of 3 to 10 degrees.

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 2A through 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 소자분리막(22)이 구비된 반도체기판(21)의 게이트 형성 영역을 리세스하여 1000∼2000Å 깊이의 홈(23)을 형성한다. Referring to FIG. 2A, the gate forming region of the semiconductor substrate 21 provided with the device isolation film 22 is recessed to form the groove 23 having a depth of 1000 to 2000 Å.

그런다음, 상기 홈(23)을 포함하는 기판 전면 상에 이온주입공정시 기판을 보호해주는 스크린산화막(24)을 형성한다. 이어서, 상기 스크린산화막(24)이 형성된 기판 내에 채널 문턱전압 조절을 위한 불순물을 이온주입한다. Then, the screen oxide film 24 is formed on the entire surface of the substrate including the groove 23 to protect the substrate during the ion implantation process. Subsequently, an ion is implanted into the substrate on which the screen oxide layer 24 is formed to control channel threshold voltages.

여기서, 상기 불순물을 이온주입하는 단계는, 홈(23) 양측 가장자리부분 하부의 채널 영역의 도핑농도가 채널 중앙부의 도핑농도 보다 낮아지도록 기판을 180°회전시키면서 2회 경사 이온주입으로 수행한다. Herein, the ion implantation may be performed by inclined ion implantation twice while rotating the substrate by 180 ° so that the doping concentration of the channel region under both edges of the groove 23 is lower than that of the center portion of the channel 23.

이때, 상기 경사 이온주입은 홈(23)의 폭과 깊이에 따라 3∼10°각도로 수행한다.At this time, the inclined ion implantation is performed at an angle of 3 to 10 degrees depending on the width and depth of the groove 23.

즉, 도 2a에 도시된 바와 같이, 1차 경사 이온주입을 실시한 후, 기판을 180°회전시키고나서, 도 2b에 도시된 바와 같이, 2차 경사 이온주입을 실시하는 2단계 방식으로 채널 문턱전압 조절 이온주입 공정을 진행한다.That is, as shown in FIG. 2A, after the first gradient ion implantation is performed, the substrate is rotated 180 °, and as shown in FIG. 2B, the channel threshold voltage is performed in a two-step manner of performing the secondary gradient ion implantation. A controlled ion implantation process is performed.

한편, 상기 불순물 이온주입은 B, BF2 및 In로 구성된 그룹으로부터 선택되 는 어느 하나의 도펀트를 사용하여 수행한다. On the other hand, the impurity ion implantation is performed using any one dopant selected from the group consisting of B, BF2 and In.

도 2c를 참조하면, 스크린산화막(24)이 제거된 상태에서, 상기 기판 결과물 전면 상에 게이트절연막(25), 게이트도전막(26) 및 하드마스크막(27)을 차례로 형성하고, 상기 하드마스크막(27)을 패터닝한 후, 패터닝된 하드마스크막(27)을 식각장벽으로 이용해서 게이트도전막(26)과 게이트절연막(25)을 순차로 식각하여 리세스 채널을 갖는 게이트(28)를 형성한다. Referring to FIG. 2C, in the state where the screen oxide film 24 is removed, the gate insulating film 25, the gate conductive film 26, and the hard mask film 27 are sequentially formed on the entire surface of the substrate resultant, and the hard mask is formed. After the patterned layer 27 is patterned, the gate conductive layer 26 and the gate insulating layer 25 are sequentially etched using the patterned hard mask layer 27 as an etch barrier to form a gate 28 having a recess channel. Form.

본 발명에서는, 상기한 바와 같이, 문턱전압 조절을 위한 이온주입을 2회 경사 이온주입으로 수행함으로써, 채널 중앙부분(C)은 2회에 걸쳐 중복적으로 이온주입이 되는 반면, 홈(23) 저면에 대응하는 채널의 가장자리부분(E)은 기판의 단차로 인해 2회에 걸친 중복적 이온주입이 이루어지지 않으므로, 상기 채널 가장자리부분(E)의 도핑농도가 채널 중앙부분(C)의 도핑농도보다 낮아지게 된다. In the present invention, as described above, by performing ion implantation for adjusting the threshold voltage by two gradient ion implantations, the channel center portion C is ion implanted twice in duplicate, while the groove 23 Since the edge portion E of the channel corresponding to the bottom surface is not overlapped with the ion implantation twice due to the step of the substrate, the doping concentration of the channel edge portion E is the doping concentration of the center portion C of the channel. Will be lower.

그러므로, 본 발명에서는 홈(23) 저면에 대응하는 채널의 가장자리부분(E)의 전계 분산 효과가 감소하고, 이에 따라, 국부적인 문턱전압 증가 현상이 억제되어 tWR 특성이 개선된다. Therefore, in the present invention, the electric field dispersion effect of the edge portion E of the channel corresponding to the bottom surface of the groove 23 is reduced, whereby the local threshold voltage increase phenomenon is suppressed and the tWR characteristic is improved.

한편, 본 발명에서 상기 게이트절연막(25)은 실리콘산화막으로 형성하는데, 이 경우, 홈(23) 양측 가장자리부분 하부의 채널 영역(E)의 도핑농도가 채널 중앙부(C)의 도핑농도 보다 낮은 것과 관련하여, 홈(23) 양측 가장자리부분에서 형성되는 게이트산화막의 두께가 홈(23)의 중앙부에서 형성되는 게이트산화막의 두께보다 얇아지게 된다. 이에 따라, 채널의 문턱전압 균일성이 향상되는 효과를 추가적으로 얻을 수 있다. Meanwhile, in the present invention, the gate insulating layer 25 is formed of a silicon oxide layer. In this case, the doping concentration of the channel region E below the edges of both sides of the groove 23 is lower than that of the channel center portion C. In this regard, the thickness of the gate oxide film formed at both edges of the groove 23 is thinner than the thickness of the gate oxide film formed at the center of the groove 23. Accordingly, the effect of improving the threshold voltage uniformity of the channel can be additionally obtained.

이후, 도시하지는 않았지만, 상기 게이트(28) 양측에 소오스/드레인 접합영역을 형성하고, 계속해서, 공지된 일련의 후속 공정을 차례로 진행하여 반도체 소자를 제조한다. Subsequently, although not shown, a source / drain junction region is formed on both sides of the gate 28, and then a series of known subsequent steps are sequentially performed to manufacture a semiconductor device.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 리세스 게이트를 갖는 반도체 소자를 제조함에 있어서, 채널 문턱전압 조절을 위한 불순물 이온주입을 경사 이온주입으로 수행하되, 기판을 180°회전시키면서 2회 수행하여, 리세스된 기판 부분의 저면 양측에 대응하는 채널 가장자리의 도핑농도가 채널 중앙부의 도핑농도 보다 낮아지게 함으로써, 채널 가장자리부분에서의 전계 분산 효과가 감소하고, 이에 따라, 국부적인 문턱전압 증가 현상이 억제되어 tWR 특성이 개선된다. 따라서, 소자의 신뢰성 및 수율이 향상되는 효과를 얻을 수 있다. As described above, in the manufacturing of the semiconductor device having the recess gate, the impurity ion implantation for the channel threshold voltage control is performed by the inclined ion implantation, while the substrate is rotated 180 ° twice, the recess By lowering the doping concentration at the channel edges corresponding to both sides of the bottom surface of the substrate, the effect of electric field dispersion at the channel edge is reduced, thereby suppressing the local threshold voltage increase, thereby reducing tWR. Properties are improved. Thus, the effect of improving the reliability and yield of the device can be obtained.

또한, 본 발명은, 채널 가장자리부분과 채널 중앙부분의 도핑농도 차이로 인해 채널 가장자리부분에 대응하는 게이트산화막이 채널 중앙부에 대응하는 게이트산화막 보다 얇게 형성되므로, 채널의 문턱전압 균일성이 향상되는 효과를 부가적으로 얻을 수 있다.In addition, according to the present invention, since the gate oxide film corresponding to the channel edge portion is formed thinner than the gate oxide film corresponding to the channel center portion due to the difference in the doping concentration between the channel edge portion and the center channel portion, the threshold voltage uniformity of the channel is improved. Can additionally be obtained.

Claims (3)

반도체기판의 채널 형성 영역을 리세스하여 홈을 형성하는 단계; 및 상기 홈을 포함한 기판 전면 상에 채널 문턱전압 조절을 위해 불순물을 이온주입하는 단계;를 포함하는 반도체 소자의 제조방법에 있어서, Recessing the channel forming region of the semiconductor substrate to form a groove; And implanting impurities on the entire surface of the substrate including the grooves to control channel threshold voltages. 상기 불순물 이온주입은 경사 이온주입으로 수행하되, 기판을 180°회전시키면서 2회 수행하여 상기 홈의 양측 가장자리부분 하부의 채널 영역의 도핑농도가 채널 중앙부의 도핑농도 보다 낮아지도록 수행하는 것을 특징으로 하는 반도체 소자의 제조방법. The impurity ion implantation may be performed by inclined ion implantation, and the doping concentration of the channel region below both edge portions of the groove may be lower than that of the center portion of the channel by rotating the substrate 180 ° twice. Method of manufacturing a semiconductor device. 제 1 항에 있어서, 상기 불순물 이온주입은 B, BF2 및 In로 구성된 그룹으로부터 선택되는 어느 하나의 도펀트를 사용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the impurity ion implantation is performed using any one dopant selected from the group consisting of B, BF 2, and In. 제 1 항에 있어서, 상기 경사 이온주입은 3∼10°각도로 수행하는 것을 특징으로 하는 반도체 소자의 제조방법. The method of claim 1, wherein the inclined ion implantation is performed at an angle of 3 to 10 degrees.
KR1020050058170A 2005-06-30 2005-06-30 Method of manufacturing semiconductor device KR20070002576A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017152191A1 (en) * 2016-03-04 2017-09-08 Texas Instruments Incorporated Mosfet transistors with robust subthreshold operations

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017152191A1 (en) * 2016-03-04 2017-09-08 Texas Instruments Incorporated Mosfet transistors with robust subthreshold operations
US9899376B2 (en) 2016-03-04 2018-02-20 Texas Instruments Incorporated MOSFET transistors with robust subthreshold operations
US10090299B2 (en) 2016-03-04 2018-10-02 Texas Instruments Incorporated MOSFET transistors with robust subthreshold operations

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