KR20080088907A - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device is provided to improve gate current driving capability while increasing the threshold voltage of a gate by implanting p-type impurity ions into a gate polysilicon layer and by forming an epitaxial growth layer on an active region before a source/drain region is formed. A semiconductor substrate(100) includes an isolation layer(130) for defining an active region(120). A predetermined depth of the active region overlapping a gate formation region is etched to form a recess gate region(140). The isolation layer overlapping the gate formation region is more etched than the depth of the recess gate region by a predetermined depth to form a trench(145) for a fin cell. A gate(160) is formed in the recess gate region and the gate formation region on the trench for the fin cell, including a polysilicon layer into which p-type impurities are implanted, a gate metal layer(154) and a gate hard mask layer(156). An epitaxial growth layer(180) is formed in the active region between the gates. A source/drain region is formed in the epitaxial growth layer and the active region under the epitaxial growth layer. N-type impurity ions can be implanted into the source/drain region.

Description

Semiconductor device and method of forming the same {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

1 is a plan view showing a semiconductor device according to the prior art.

2 is a cross-sectional view showing a semiconductor device and a method of forming the same according to the prior art.

3 is a plan view showing a semiconductor device according to the present invention.

4A and 4B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same. In order to solve the problem that the gate threshold voltage is reduced while the semiconductor device is highly integrated and the process margin for forming the fin cell is reduced, the electrical characteristics of the gate are degraded. By implanting P-type impurity ions into the silicon layer, and further forming an epitaxial growth layer over the active region prior to forming the source / drain regions to increase the trench formation process margins for the recess gate region and fin cell formation. In addition, the present invention relates to an embodiment in which the gate channel length can be easily extended, and the gate channel area can be simultaneously increased while improving the electrical characteristics of the gate while maintaining the effect of increasing the gate threshold voltage.

As semiconductor devices are highly integrated, process margins for forming active regions and device isolation layers are reduced. In addition, as the line width of the gate narrows, a short channel effect, which is a problem in which electrical characteristics of a semiconductor device is degraded due to a decrease in channel length, has occurred. The short channel effect reduces the gate threshold voltage and reduces the gate current driving capability. Therefore, a method of increasing the gate channel area by forming a fin type active region is used as a method for improving the current driving capability.

1 is a plan view showing a semiconductor device according to the prior art.

Referring to FIG. 1, an active region 20 and an isolation layer 30 are provided in a semiconductor substrate 10.

Next, a trench for forming a fin cell in which a recess gate region (not shown) in which the active region 20 overlapping with the gate predetermined region is etched and the device isolation layer 30 overlapping with the gate predetermined region are etched are provided. (Not shown) is provided.

FIG. 2 is a cross-sectional view illustrating a semiconductor device and a method of forming the same according to the prior art. FIG. 2 (i) illustrates a cross section taken along the direction XX ′ of FIG. 1, and FIG. 2 (ii) shows YY '. The cross section along the direction is shown.

Referring to FIG. 2, the device isolation layer 30 and the active region 20 are formed on the semiconductor substrate 10, and the active region 20 is partially etched and recessed by a partial etching process using a mask exposing the gate predetermined region. The gate region 40 is formed, and the isolation layer 30 overlapping the gate predetermined region is etched to form a trench 45 for forming a fin cell.

Next, the gate oxide film 50, the gate polysilicon layer 52, the gate metal layer 54 and the gate hard mask layer pattern 56 filling the recess gate region 40 and the fin cell forming trench 45 are next. To form a gate (60) provided with.

Next, source / drain regions 70 are formed in the active region 20 between the gates 60.

Here, referring to (i) of FIG. 2, the gate channel length may be extended by the recess gate region, and the increase of the gate threshold voltage may be expected, but the process margin for forming the recess gate region is gradually decreasing. This situation is limited. In addition, when the gate channel area is increased by the fin cell 25 when referring to (ii) of FIG. 2, the effect of increasing the current driving capability of the gate and improving the refresh characteristic can be expected. When the impurity ion implantation concentration of 70) increases, there is a problem that the effect by the pin cell is reduced.

As described above, in order to improve the electrical characteristics of the gate, a method of forming a recess gate region and a fin cell and forming a gate including the same is used. However, when the depth of the trench for forming the fin cell is deeply formed, the concentration of impurity ions in the source / drain regions needs to be increased in accordance with the increased current driving capability, thereby increasing the trench indefinitely. Therefore, the process margin for forming the recess gate region and the fin cell is reduced, and the yield and reliability for forming the semiconductor device are reduced.

In order to solve the above problems, the present invention prior to implanting P-type impurity ions into the gate polysilicon layer and forming source / drain regions to increase trench formation process margins for recess gate region and fin cell formation. By further forming an epitaxial growth layer on the active region, the gate channel length can be easily extended, and the gate channel area can be increased simultaneously to improve the electrical characteristics of the gate while maintaining the effect of increasing the gate threshold voltage. It is an object of the present invention to provide a semiconductor device and a method for forming the same.

In order to achieve the above object, the semiconductor device according to the present invention

A semiconductor substrate including an isolation layer defining an active region;

A recess gate region formed by etching the active region overlapping the gate predetermined region by a predetermined depth;

A trench for forming a fin cell, which is formed by etching the device isolation layer overlapping a gate predetermined region deeper than a depth of the recess gate region;

A gate including a polysilicon layer, a gate metal layer, and a gate hard mask layer structure formed in the recess gate region and the gate predetermined region above the fin cell forming trench and implanted with P-type impurities;

An epitaxial growth layer formed in an active region between the gates;

And an epitaxial growth layer and a source / drain region formed in an active region under the epitaxial growth layer.

Here, the etching depth of the recess gate region is 500 ~ 2000Å, wherein the trench is formed to be 300 ~ 1000Å deeper than the depth of the recess gate region, the thickness of the epitaxial growth layer It is characterized in that the 100 ~ 1500Å, the thickness of the source / drain region is characterized in that 100 ~ 2000Å, the source / drain region is characterized in that the implanted N-type impurity ions.

In addition, the method of forming a semiconductor device according to the present invention for forming the semiconductor device

Forming an isolation layer defining an active region on the semiconductor substrate;

Etching the active region overlapping the gate predetermined region to a predetermined depth to form a recess gate region;

Forming a trench for forming a fin cell by etching the device isolation layer overlapping the gate predetermined region deeper than the depth of the recess gate region by a predetermined depth;

Forming a gate having a gate oxide layer, a polysilicon layer into which a P-type impurity is implanted, a gate metal layer, and a gate hard mask layer structure in a gate predetermined region including the recess gate region and the fin cell forming trench;

Forming an epitaxial growth layer by performing a selective epitaxial growth process on the active regions exposed between the gates; and

And implanting impurity ions into an active region under the epitaxial growth layer and the epitaxial growth layer to form a source / drain region.

Here, the etching depth of the recess gate region is 500 ~ 2000Å, wherein the trench is formed to be 300 ~ 1000Å deeper than the depth of the recess gate region, the thickness of the epitaxial growth layer It is characterized in that the 100 ~ 1500Å, the thickness of the source / drain region is characterized in that 100 ~ 2000Å, the source / drain region is characterized in that the implanted N-type impurity ions.

Hereinafter, a semiconductor device and a method for forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing a semiconductor device according to the present invention.

Referring to FIG. 3, an isolation layer 130 defining a bar type active region 120 is provided on a semiconductor substrate 100. The device isolation layer 130 is formed perpendicular to the bar type active region 120. A gate 160 is provided which divides 120 into three portions.

The recess gate region 140 is formed in the active region 120 overlapping the gate 160, and the fin cell formation trench 145 is formed in the device isolation layer 130 overlapping the gate 160. Is provided.

An epitaxial growth layer 180 is provided on the active region 120 exposed by the gate 160. Next, a source / drain region (not shown) is formed in the epitaxial growth layer 180 and the active region 120 under the epitaxial growth layer 180.

Here, when N-type impurity ions are implanted in the source / drain region, P-type impurity ions are implanted in the polysilicon layer pattern included in the gate 160. This method is used to obtain the effect of increasing the threshold voltage (Vt) due to the difference in work function due to the P-type impurities and N-type impurities having opposite properties, in which case the effect of the pin cell is By further forming the epitaxial growth layer 180 since the current driving capability can be reduced, the process margin for forming the recess gate region and the fin cell forming trench can be increased and injected into the source / drain region. Impurity concentration can be adjusted to improve the electrical characteristics of the gate.

4A and 4B are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention. 4A and 4B show cross sections along the XX 'direction of FIG. 3, and FIGS. 4A and 4B show cross sections along the YY' direction of FIG. will be.

Referring to FIG. 4A, the device isolation layer 130 defining the active region 120 is formed on the semiconductor substrate 100. In this case, the device isolation layer 130 may be formed using a shallow trench isolation (STI) process, and may be formed using a high density plasma (HDP) oxide film.

Next, in a subsequent process, a portion of the active region 120 overlapping the gate predetermined region (see gate 160 in FIG. 3), which is a region where the gate is formed on the semiconductor substrate 100, is etched to a predetermined depth to recess the recess. The gate region 140 is formed. In this case, the etching process using a mask exposing the gate predetermined region is a partial etching process to selectively etch only the silicon constituting the active region 120, the etching depth of the recess gate region 140 is 500 ~ 2000Å It is preferable. In this case, the recess gate region 140 may have an effect of expanding the recess gate region 140 by an epitaxial growth layer formed in a subsequent process as described above with reference to FIG. 3. It can be formed lower than the depth of the region. Therefore, the margin of the etching process for forming the recess gate region 140 may be increased.

Thereafter, an etching process using a mask that exposes the gate planar region is performed, but a partial etching process of selectively etching only an oxide layer constituting the device isolation layer 130 is performed to form a fin type active region trench 145. To form. In this case, the trench 145 may be formed to be 300 to 1000 Å deeper than the depth of the recess gate region 140, and the edge portion of the recess gate region 140 is partially etched to round the active region 120. The pin cell 125 (see (ii) of FIG. 4A).

Subsequently, the gate oxide layer 150, the gate polysilicon layer 152, the gate metal layer 154, and the gate hard mask layer 156 may be stacked in a gate predetermined region including the recess gate region 140. And a gate 160 having spacers 158 on the sidewalls. In this case, the gate polysilicon layer 152 uses polysilicon implanted with P-type impurity ions. This is to increase the threshold voltage (Vt) by increasing the difference in the work function (work function) for the source / drain region formed by the N-type impurities in the subsequent process.

Referring to FIG. 4B, an epitaxial growth layer 180 is formed by performing a selective epitaxial growth process on the active region 120 exposed by the gate 160. At this time, the thickness of the epitaxial growth layer 180 is preferably formed to 100 ~ 1500Å. The epitaxial growth layer 180 extends the active region 120 and increases the depth of the recess gate region 140. In addition, since the depth of the trench 145 for forming the fin cell 125 is also deepened, an etching process margin for forming the recess gate region 140 and the trench 145 may be increased.

Next, the source / drain region 170 is formed by implanting impurity ions into the epitaxial growth layer 180 and the active region under the epitaxial growth layer 180. At this time, it is preferable to use N-type impurities such as phosphorous (Phosphorous), it is preferable to control the ion implantation process to be formed in the region corresponding to the depth of 100 ~ 2000Å from the surface of the epitaxial growth layer 180. .

As described above, the semiconductor device and the method of forming the same according to the present invention inject P-type impurity ions into the gate polysilicon layer in order to increase the gate threshold voltage Vt. In addition, an epitaxial growth layer is further formed on the active region prior to forming the source / drain regions in order to increase the trench forming process margin for forming the recess gate region and the fin cell. As the elevated source drain (EDS) structure is formed, the gate channel length can be easily extended, and the gate channel area can be simultaneously increased while maintaining the effect of increasing the gate threshold voltage. The gate leakage current can be reduced, the gate current driving ability can be easily increased, and the refresh characteristics can be improved.

As described above, the semiconductor device and the method of forming the same according to the present invention inject P-type impurity ions into the gate polysilicon layer to increase the gate threshold voltage Vt, and form a recess gate region and a fin cell. An epitaxial growth layer is further formed over the active region prior to forming the source / drain regions to increase the trench formation process margin. Accordingly, while increasing the gate threshold voltage, the gate current driving capability is improved and the refresh characteristics are improved.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (12)

A semiconductor substrate including an isolation layer defining an active region; A recess gate region formed by etching the active region overlapping the gate predetermined region by a predetermined depth; A trench for forming a fin cell, which is formed by etching the device isolation layer overlapping a gate predetermined region deeper than a depth of the recess gate region; A gate including a polysilicon layer, a gate metal layer, and a gate hard mask layer structure formed in the recess gate region and a gate predetermined region above the fin cell forming trench and implanted with P-type impurities; An epitaxial growth layer formed in the active region between the gates; And And a source / drain region formed in the active region below the epitaxial growth layer and the epitaxial growth layer. The method of claim 1, The etching depth of the recess gate region is a semiconductor device, characterized in that 500 ~ 2000Å. The method of claim 1, The trench is a semiconductor device, characterized in that to form a depth of 300 ~ 1000Å more than the depth of the recess gate region. The method of claim 1, The thickness of the epitaxial growth layer is a semiconductor device, characterized in that 100 ~ 1500Å. The method of claim 1, The thickness of the source / drain region is 100 ~ 2000Å semiconductor device. The method of claim 1, And n-type impurity ions are implanted into the source / drain regions. Forming an isolation layer defining an active region on the semiconductor substrate; Etching the active region overlapping the gate predetermined region by a predetermined depth to form a recess gate region; Forming a trench for forming a fin cell by etching the device isolation layer overlapping a gate predetermined region deeper than a depth of the recess gate region by a predetermined depth; Forming a gate having a gate oxide layer, a polysilicon layer implanted with P-type impurities, a gate metal layer, and a gate hard mask layer in a gate predetermined region including the recess gate region and the fin cell forming trench; Forming an epitaxial growth layer by performing a selective epitaxial growth process on the active regions exposed between the gates; And And forming a source / drain region by implanting impurity ions into the epitaxial growth layer and an active region under the epitaxial growth layer. The method of claim 7, wherein The etching depth of the recess gate region is 500 ~ 2000Å, the method of forming a semiconductor device. The method of claim 7, wherein The trench is a method of forming a semiconductor device, characterized in that to form a depth of 300 ~ 1000Å more than the depth of the recess gate region. The method of claim 7, wherein The epitaxial growth layer has a thickness of 100 to 1500 kPa. The method of claim 7, wherein And the thickness of the source / drain regions is 100 to 2000 microns. The method of claim 7, wherein N-type impurity ions are implanted into the source / drain region.

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