KR100909777B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and by forming a SEG film having a predetermined thickness inside the recess, the line width of the recess can be adjusted, and thus overlap between the recess and the gate electrode in the subsequent process of forming the gate pattern. Disclosed is a technique for securing margins and preventing horns caused by the reduction of the line width of the recesses, thereby improving the characteristics and reliability of the cell transistors.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1C are plan views, cross-sectional views and photographs showing a method of manufacturing a semiconductor device and a problem thereof according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of Signs of Major Parts of Drawings>

10, 100: semiconductor substrate 15, 115: device isolation film

16: active region 17, 180: gate polysilicon layer

18, 190: gate metal layer 19, 195: gate hard mask layer

20, 200: gate pattern 25, 210: spacer

30 gate electrode 110 liner nitride film

120: screen oxide film 160: recess

170a, 170b: SEG film 175: oxide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and by forming a SEG film having a predetermined thickness inside the recess, the line width of the recess can be adjusted, and thus overlap between the recess and the gate electrode in the subsequent process of forming the gate electrode. Disclosed is a technique for securing margins and preventing horns caused by the reduction of the line width of the recesses, thereby improving the characteristics and reliability of the cell transistors.

As the design rule of the device is reduced due to the high integration of DRAM memory cells, the size of the cell transistor is reduced and the channel length of the transistor is also shortened. As the channel length becomes shorter, the short-channel effect of the transistor is deepened to reduce the threshold voltage.

Accordingly, in order to prevent the threshold voltage from decreasing due to the short channel effect of the transistor, a threshold voltage of a desired magnitude may be obtained by increasing the doping concentration of the channel.

However, such an increase in channel doping concentration causes a problem of electric field concentration at the source junction and increases leakage current, thereby degrading the refresh characteristics of the DRAM memory cell.

Therefore, in recent years, researches on transistors having recess gates have been concentrated in order to solve this problem.

1A to 1C are a plan view, a cross-sectional view, and a plan view showing a recess gate manufacturing method and a problem thereof of a semiconductor device according to the prior art.

Referring to FIG. 1A, a plan view of an active region 16 and a gate electrode 30 defining an isolation layer 15 is provided.

In this case, since an overlap margin is not secured between the recess (not shown) formed by etching the semiconductor substrate of the active region 16 and the gate electrode 30, misalignment may occur, such as '40'.

Referring to FIG. 1B, a cross-sectional view of the cutting plane taken along the line 'X-X' of FIG. 1A is used to etch a semiconductor substrate 10 including the device isolation layer 15 to form a recess (not shown). .

Next, a stacked structure of the gate polysilicon layer 17, the gate metal layer 18, and the gate hard mask layer 19 filling the recess (not shown) is formed and then etched to form the gate pattern 20. do.

Next, the spacer layer is formed on the entire surface including the gate pattern 20 and then etched to form a recess gate 30 including the spacer 25.

In this case, an overlap margin is not secured between the recess (not shown) and the gate electrode, thereby forming a misaligned recess gate 30 such as '40'.

Referring to FIG. 1C, a SEM image showing a recess gate is formed, and it can be seen that misalignment occurs, such as '40', between a recess (not shown) and the gate electrode.

In the method of manufacturing a semiconductor device according to the related art described above, the line width of the recess is reduced as the design rule is reduced, and the overlap margin is not secured between the recess and the gate electrode as the depth of the recess is deep, thereby causing misalignment. There is this.

In order to solve the above problem, by forming a SEG film having a predetermined thickness inside the recess, it is possible to adjust the line width of the recess, thereby securing an overlap margin between the recess and the gate electrode when forming the gate electrode, which is a subsequent process. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can prevent a horn generated due to a decrease in line width of a recess, thereby improving characteristics and reliability of a cell transistor.

Method for manufacturing a semiconductor device according to the present invention

Forming a pad oxide layer on the semiconductor substrate having the device isolation layer defining an active region;

Etching the pad oxide layer and the semiconductor substrate to form a recess;

Growing a silicon layer of the semiconductor substrate exposed inside the recess to form an SEG film;

Forming a gate oxide film in the recess;

And forming a gate pattern by forming a gate material layer over the entire semiconductor substrate including the recess and then etching the gate material layer.

Forming a pad oxide layer on the semiconductor substrate having the device isolation layer defining an active region;

Etching the pad oxide layer and the semiconductor substrate to form a recess;

Forming an oxide film on the bottom of the recess and growing a silicon layer of the exposed semiconductor substrate to form a SEG film having a predetermined thickness;

Forming a gate oxide film in the recess;

Forming a gate pattern by forming a gate material layer over the entire semiconductor substrate including the recess and then etching the gate material layer;

The depth of the recess is 100 to 2000 microns;

The SEG film is formed at a temperature of 750 to 820 ℃,

The thickness of the SEG film is from 300 to 700Å,

The SEG film further comprises the step of doping using any one selected from B, BF2 or a combination thereof,

The forming of the oxide film on the bottom of the recess further includes forming an oxide film over the entire semiconductor substrate including the recess, and leaving an oxide film only on the bottom of the recess by full etching.

The oxide film is formed of any one selected from PE-TEOS, LP-TEOS, HDP, SOD or a combination thereof,

The oxide film is characterized in that it is left 1/2 to 2/3 from the bottom of the recess.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2D are cross-sectional views illustrating a method of forming a recess gate in a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 2A, a pad oxide layer is formed on an upper portion of a semiconductor substrate 100 having a device isolation layer 115 defining an active region and a sidewall oxide layer (not shown) and a liner nitride layer 110 formed at an interface between the active region and the device isolation layer 115. Form 120.

Referring to FIG. 2B, a hard mask layer pattern (not shown) defining a recessed region is formed on the semiconductor substrate 100.

Next. The recess 160 is formed by etching the pad oxide layer 120 and the semiconductor substrate 100 by using a hard mask layer pattern (not shown) as an etch mask.

In this case, the hard mask layer pattern (not shown) is a laminated structure of an amorphous carbon layer (A-Carbon) and silicon oxynitride layer (SiON), the recess 160 is formed to a depth of 1000 to 2000Å.

Referring to FIG. 2C, a silicon layer of the semiconductor substrate 100 exposed inside the recess 160 is grown to form a silicon epitaxial growth (SEG) film 170a.

In this case, since the pad oxide film 120 is formed on the semiconductor substrate 100, the SEG film 170a is grown only in the recess 160.

Here, the SEG film 170a is formed to a thickness of 300 to 700 kPa at a temperature of 480 to 820 ° C.

Next, the method further comprises doping using any one selected from B, BF2, or a combination thereof.

The doping process may be performed in an undoped or channel doping concentration, and proceeded to an in-situ or ex-situ process.

Referring to FIG. 2D, a gate oxide layer (not shown) is formed in the recess 160, and the gate polysilicon layer 180 and the gate metal layer are formed on the entire semiconductor substrate 100 including the recess 160. The gate pattern 200 is formed by forming a stacked structure of the layer 190 and the gate hard mask layer 195 and etching the same.

Next, a spacer layer (not shown) is formed over the entire surface including the gate pattern 200, and a recess gate including the nitride layer spacer 210 is formed on the sidewall by performing a front side etching process.

3A and 3B are cross-sectional views illustrating a method of forming a recess gate of a semiconductor device in accordance with a second embodiment of the present invention.

Referring to FIG. 3A, an oxide layer (not shown) may be formed so that the recess 160 is buried in the entire upper portion of the semiconductor substrate 100 having the recess 160 formed in the same process as in FIGS. 2A and 2B. To form.

Next, the oxide layer (not shown) is etched by the entire surface etching or the planarization etching process so that the oxide layer 175 is left only at the bottom of the recess 160.

Here, the oxide film 175 is formed of any one selected from PE-TEOS, LP-TEOS, HDP, SOD, or a combination thereof, and the etching process of the oxide film 175 is 1/2 to 2/3 from the bottom of the recess 160. The thickness is left to the left.

Next, an oxide film 175 is not formed in the recess 160, so that the silicon layer of the exposed semiconductor substrate 100 is grown to form the SEG film 170b.

In this case, since the pad oxide film 125 is formed on the semiconductor substrate 100, and the oxide film 175 is buried in the bottom of the recess 160, the SEG film 170b is formed only on a part of the sidewall of the recess 160. Is grown.

Referring to FIG. 3B, a gate oxide layer (not shown) is formed in the recess 160, and the gate polysilicon layer 180 and the gate metal layer are formed on the entire semiconductor substrate 100 including the recess 160. The gate pattern 200 is formed by forming a stacked structure of the layer 190 and the gate hard mask layer 195 and etching the same.

Next, a spacer layer (not shown) is formed over the entire surface including the gate pattern 200, and a recess gate including the nitride layer spacer 210 is formed on the sidewall by performing an entire surface etching process.

In the method of manufacturing a semiconductor device according to the present invention, by forming a SEG film having a predetermined thickness inside the recess, the line width of the recess can be adjusted, and thus, an overlap margin between the recess and the gate electrode when forming the gate electrode, which is a subsequent process, is formed. In addition, the horn generated due to the reduction of the line width of the recess can be prevented, thereby improving the characteristics and reliability of the cell transistor.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (9)

delete Forming a pad oxide layer on the semiconductor substrate having the device isolation layer defining an active region; Etching the pad oxide layer and the semiconductor substrate to form a recess; Forming an oxide film on the bottom of the recess and growing a silicon layer of the exposed semiconductor substrate to form a SEG film having a predetermined thickness; Forming a gate oxide film in the recess; And Forming a gate pattern by forming a gate material layer over the entire semiconductor substrate including the recess and then etching the same; Forming an oxide film on the bottom of the recess Forming an oxide film over the entire semiconductor substrate including the recess; And Leaving an oxide layer only at the bottom of the recess by full etching Method of manufacturing a semiconductor device comprising a. The method of claim 2, The depth of the recess is 100 to 2000Å, the manufacturing method of a semiconductor device. The method of claim 2, The SEG film is a method of manufacturing a semiconductor device, characterized in that formed at a temperature of 750 to 820 ℃. The method of claim 2, The SEG film has a thickness of 300 to 700 GPa. The method of claim 2, The SEG film further comprises the step of doping using any one selected from B, BF2 or a combination thereof. delete The method of claim 2, The oxide film is a method of manufacturing a semiconductor device, characterized in that formed by any one selected from PE-TEO, LP-TEOS, HDP, SOD or a combination thereof. The method of claim 2, The oxide film is a method of manufacturing a semiconductor device, characterized in that about 1/2 to 2/3 from the bottom of the recess.

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