KR20070112557A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20070112557A
KR20070112557A KR1020060045596A KR20060045596A KR20070112557A KR 20070112557 A KR20070112557 A KR 20070112557A KR 1020060045596 A KR1020060045596 A KR 1020060045596A KR 20060045596 A KR20060045596 A KR 20060045596A KR 20070112557 A KR20070112557 A KR 20070112557A
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semiconductor device
manufacturing
gate
layer
gate region
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KR1020060045596A
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Korean (ko)
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전윤석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

A method for manufacturing a semiconductor device is provided to improve Vt control and current leakage property due to doping a channel uniformly and thinly on a surface of a recess gate region by doping boron ion and simultaneously growing an SEG film at inner side of a recess gate region, and perform no additional a process of supplying ion. A pad oxide layer is formed on a semiconductor substrate, and a recess gate region(130) is formed by etching the pad oxide layer and the semiconductor substrate of a predetermined depth. An SEG film(140) is formed by growing a silicon layer of the recess gate region. A gate oxide layer(150) is formed within the recess gate region. After forming a polysilicon layer(160), a gate metal layer(170) and a gate hard mask layer sequentially on the entire surface of the resultant structure, a gate pattern is formed by patterning.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 3차원 셀 형성시 리세스 게이트 영역 내측에 SEG막을 성장시키고, 성장시킴과 동시에 보론 이온을 도핑시켜 채널 영역을 형성함으로써, 리세스 게이트 영역 표면에 균일하고 얇은 채널 도핑이 가능해 Vt 조절 및 누설전류 특성이 향상되고, 소스/드레인 사이에 전체 채널이 균일한 농도로 도핑되기 때문에 추가적인 이온주입 공정을 수행하지 않아도 되어 공정이 단순화되어 셀 트랜지스터의 특성을 향상시키는 기술을 개시한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a three-dimensional cell is formed to grow a SEG film inside a recess gate region, to grow the same, and to simultaneously doping boron ions to form a channel region, thereby making it uniform on the surface of the recess gate region. Thin channel doping improves Vt control and leakage current characteristics, and the entire channel is doped with uniform concentration between source and drain, eliminating the need for additional ion implantation processes, simplifying the process to improve cell transistor characteristics Disclosed is a technique to make.

최근 반도체 소자의 크기가 점점 작아짐에 따라 낮은 셀 콘택 저항과 리프레쉬 특성 등을 확보하기 위해서 리세스 채널 게이트의 적용이 필수적이다. Recently, as the size of a semiconductor device becomes smaller, it is necessary to apply a recess channel gate to secure a low cell contact resistance and refresh characteristics.

리세스 채널 게이트 구조에서는 리세스 게이트의 깊이 및 곡률반경을 포함한 하부 구조의 형태가 매우 중요하며, 이들에 대한 웨이퍼 내의 균일도가 Vt 균일도 및 DIBL 특성에 영향을 미치게 된다. In the recess channel gate structure, the shape of the substructure including the depth and the radius of curvature of the recess gate is very important, and the uniformity in the wafer with respect to them affects the Vt uniformity and DIBL characteristics.

종래기술에 따른 반도체 소자의 제조 방법은 소자분리막이 구비된 반도체 기판을 소정깊이 식각하여 리세스 게이트 영역을 형성한다. In the method of manufacturing a semiconductor device according to the related art, a recess gate region is formed by etching a semiconductor substrate provided with an isolation layer.

다음에, 채널 영역 형성을 위해 이온 주입 공정을 수행한 후 폴리실리콘층, 게이트 금속층 및 게이트 하드마스크층의 적층구조를 형성하고, 상기 적층구조를 식각하여 게이트 패턴을 형성한다.Next, after the ion implantation process is performed to form the channel region, a stack structure of a polysilicon layer, a gate metal layer, and a gate hard mask layer is formed, and the stack structure is etched to form a gate pattern.

이때, 리세스 게이트와 같은 3차원 구조의 셀에서는 이온 주입 방법으로 균일한 채널 영역을 도핑시키는데 어려움이 있다.In this case, in a cell having a three-dimensional structure such as a recess gate, it is difficult to dope a uniform channel region by an ion implantation method.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 채널 전체를 원하는 농도로 도핑시키고 활성화시키는 것은 거의 불가능하여 리세스 게이트 영역의 하부에만 도핑이 되고 상기 리세스 게이트 영역의 양측면은 상대적으로 낮은 농도로 도핑되어 Vt 조절 및 균일도 특성이 악화되는 문제점이 있다. In the above-described method of manufacturing a semiconductor device, it is almost impossible to dope and activate the entire channel to a desired concentration, so that the entire channel is doped only under the recess gate region, and both sides of the recess gate region are relatively low. Doping has a problem in that Vt control and uniformity characteristics are deteriorated.

상기 문제점을 해결하기 위하여, 3차원 셀 형성시 리세스 게이트 영역 내측에 SEG막을 성장시키고, 성장시킴과 동시에 보론 이온을 도핑시켜 채널 영역을 형성함으로써, 리세스 게이트 영역 표면에 균일하고 얇은 채널 도핑이 가능해 Vt 조절 및 누설전류 특성이 향상되고, 소스/드레인 사이에 전체 채널이 균일한 농도로 도핑되기 때문에 추가적인 이온주입 공정을 수행하지 않아도 되어 공정이 단순화되어 셀 트랜지스터의 특성을 향상시키는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다. In order to solve the above problems, the SEG film is grown inside the recess gate region when the three-dimensional cell is formed, and at the same time, the channel region is formed by doping boron ions to form a uniform and thin channel doping on the surface of the recess gate region. Vt control and leakage current characteristics are improved, and the entire channel is doped at a uniform concentration between the source and the drain, so that no additional ion implantation process is required, thereby simplifying the process to improve the characteristics of the cell transistor. It is an object to provide a method.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

(a) 반도체 기판 상부에 패드 산화막을 형성하고, 상기 패드 산화막 및 소정 깊이의 반도체 기판을 식각하여 리세스 게이트 영역을 형성하는 단계; (b) 상기 리세스 게이트 영역의 실리콘층을 성장시켜 SEG막을 형성하는 단계; (c) 상기 리세스 게이트 영역 내부에 게이트 산화막을 형성하는 단계; (d) 상기 구조물 전면에 폴리실리콘층, 게이트 금속층 및 게이트 하드마스크층을 순차적으로 형성한 후 패터닝하여 게이트 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다. (a) forming a pad oxide layer on the semiconductor substrate, and etching the pad oxide layer and the semiconductor substrate having a predetermined depth to form a recess gate region; (b) growing a silicon layer in the recess gate region to form an SEG film; (c) forming a gate oxide film inside the recess gate region; (d) sequentially forming a polysilicon layer, a gate metal layer, and a gate hard mask layer on the entire surface of the structure to form a gate pattern.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 1a를 참조하면, 소자분리막(110)이 구비된 반도체 기판(100)의 활성영역을 소정 깊이 식각하여 리세스 게이트 영역을 형성한다. Referring to FIG. 1A, a recess gate region is formed by etching an active region of a semiconductor substrate 100 provided with an isolation layer 110 to a predetermined depth.

이때, 상기 리세스 게이트 영역 형성 공정은 반도체 기판(100) 상부에 패드 산화막(120)으로 100 내지 400Å 두께의 HTO 또는 PE-산화막을 형성하고, 하드마스크층(미도시)으로 1000 내지 1500Å의 폴리실리콘층 또는 1000 내지 3000Å의 비정질 탄소층을 형성한다. In this case, the recess gate region forming process forms a HTO or PE-oxide film having a thickness of 100 to 400 Å on the pad oxide layer 120 on the semiconductor substrate 100, and a poly of 1000 to 1500 Å as the hard mask layer (not shown). A silicon layer or an amorphous carbon layer of 1000 to 3000 GPa is formed.

다음에, 상기 하드마스크층(미도시)을 식각하여 하드마스크층 패턴(미도시)을 형성하고, 상기 하드마스크층 패턴(미도시)로 패드 산화막(120) 및 소정 깊이의 반도체 기판(100)을 식각하여 리세스 게이트 영역(130)을 형성한다. Next, the hard mask layer (not shown) is etched to form a hard mask layer pattern (not shown), and the pad oxide layer 120 and the semiconductor substrate 100 having a predetermined depth are formed using the hard mask layer pattern (not shown). Etch to form the recess gate region 130.

이때, 리세스 게이트 영역(130)은 후속 공정에서 형성되는 게이트 패턴의 예정 영역보다 작은 30 내지 70nm의 폭을 가지고, 1000 내지 2000Å의 깊이로 형성하는 것이 바람직하다. In this case, the recess gate region 130 may have a width of 30 to 70 nm smaller than a predetermined region of the gate pattern formed in a subsequent process, and may be formed to a depth of 1000 to 2000 μs.

여기서, 후속 공정인 SEG막 성장을 위해 리세스 게이트 영역(130) 형성 후 H2를 사용한 베이크 공정 또는 H2 및 N2 플라즈마를 이용한 클리닝 공정을 수행하여 기판 표면을 세정한다. Here, performing a cleaning process using a subsequent step the film SEG for growing the recessed gate region 130 is formed after baking step or H 2 and N 2 with H 2 plasma to the substrate surface is cleaned.

도 1b를 참조하면, 리세스 게이트 영역(130) 내측의 실리콘층을 성장시켜 일정 두께의 SEG막(140)을 형성한다. Referring to FIG. 1B, a silicon layer inside the recess gate region 130 is grown to form a SEG film 140 having a predetermined thickness.

이때, SEG막(140)은 B2H6, SiH4 및 HCl을 소스 가스로 50 내지 200Å의 두께로 형성한다. At this time, the SEG film 140 is formed of B 2 H 6 , SiH 4 and HCl with a thickness of 50 to 200 kPa as a source gas.

또한, SEG막(140)에 인시투 공정으로 1.0E18 내지 6.0E18/cm3의 농도의 보론 이온을 도핑시킨다. In addition, the SEG film 140 is doped with boron ions having a concentration of 1.0E18 to 6.0E18 / cm 3 in an in-situ process.

도 1c를 참조하면, 리세스 게이트 영역(130)을 포함한 반도체 기판(100) 전면에 게이트 산화막(150)을 형성한다. Referring to FIG. 1C, a gate oxide layer 150 is formed on the entire surface of the semiconductor substrate 100 including the recess gate region 130.

여기서, 게이트 산화막(150)은 750 내지 900℃의 퍼니스에서 20 내지 50Å의 두께로 형성한다. Here, the gate oxide film 150 is formed to a thickness of 20 to 50 kPa in a furnace at 750 to 900 ℃.

도 1d를 참조하면, 상기 구조물 전면에 폴리실리콘층(160), 게이트 금속층 (170)및 게이트 하드마스크층(180)의 적층구조를 형성한다.Referring to FIG. 1D, a stacked structure of the polysilicon layer 160, the gate metal layer 170, and the gate hard mask layer 180 is formed on the entire surface of the structure.

여기서, 폴리실리콘층(160)은 인시투 공정으로 1.0E20 내지 6.0E20/cm3의 농도의 인 이온을 도핑시키며, 5 내지 80torr의 압력, 500 내지 580℃의 온도에서 500 내지 1500Å의 두께로 형성한다. Herein, the polysilicon layer 160 is doped with phosphorus ions having a concentration of 1.0E20 to 6.0E20 / cm 3 in an in-situ process, and is formed to a thickness of 500 to 1500 Pa at a pressure of 5 to 80 torr and a temperature of 500 to 580 ° C. do.

여기서, 게이트 금속층(170)은 800 내지 1300Å의 텅스텐 실리사이드 또는 250 내지 500Å의 텅스텐층으로 형성하는 것이 바람직하며, 게이트 금속층(170) 하부에 텅스텐 실리사이드, 티타늄 질화막, 텅스텐 질화막 및 이들의 조합중 선택된 어느 하나를 사용하여 배리어 막을 형성하는 단계를 더 포함할 수도 있다.Here, the gate metal layer 170 is preferably formed of a tungsten silicide of 800 to 1300 또는 or a tungsten layer of 250 to 500 Å, and any one selected from tungsten silicide, titanium nitride film, tungsten nitride film and combinations thereof below the gate metal layer 170. The method may further include forming a barrier film using one.

도 1e를 참조하면, 상기 적층구조를 식각하여 게이트 패턴을 형성한 후 상기 게이트 패턴 측벽에 스페이서(190)을 형성한다. Referring to FIG. 1E, the stack structure is etched to form a gate pattern, and then spacers 190 are formed on sidewalls of the gate pattern.

본 발명에 따른 반도체 소자의 제조 방법은 상기에 기술한 일반적인 리세스 게이트 형성 외에도 벌브(Bulb)형 리세스 게이트, 볼(Ball)형의 리세스 게이트 및 핀(Fin)형 게이트 형성에도 사용가능한 것을 특징으로 한다. The method for manufacturing a semiconductor device according to the present invention can be used for forming a bulb type recess gate, a ball type recess gate, and a fin type gate in addition to the general recess gate formation described above. It features.

본 발명에 따른 반도체 소자의 제조 방법은 3차원 셀 형성시 리세스 게이트 영역 내측에 SEG막을 성장시키고, 성장시킴과 동시에 보론 이온을 도핑시켜 채널 영역을 형성함으로써, 리세스 게이트 영역 표면에 균일하고 얇은 채널 도핑이 가능해 Vt 조절 및 누설전류 특성이 향상되고, 소스/드레인 사이에 전체 채널이 균일한 농도로 도핑되기 때문에 추가적인 이온주입 공정을 수행하지 않아도 되어 공정이 단순화되어 셀 트랜지스터의 특성을 향상시키는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, a SEG film is grown inside a recess gate region when forming a three-dimensional cell, and at the same time, a channel region is formed by doping boron ions to form a channel region. Channel doping enables improved Vt control and leakage current characteristics, and the entire channel is doped at uniform concentrations between the source and drain, eliminating the need for additional ion implantation processes, simplifying the process to improve cell transistor characteristics There is.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

(a) 반도체 기판 상부에 패드 산화막을 형성하고, 상기 패드 산화막 및 소정 깊이의 반도체 기판을 식각하여 리세스 게이트 영역을 형성하는 단계;(a) forming a pad oxide layer on the semiconductor substrate, and etching the pad oxide layer and the semiconductor substrate having a predetermined depth to form a recess gate region; (b) 상기 리세스 게이트 영역의 실리콘층을 성장시켜 SEG막을 형성하는 단계;(b) growing a silicon layer in the recess gate region to form an SEG film; (c) 상기 리세스 게이트 영역 내부에 게이트 산화막을 형성하는 단계; 및(c) forming a gate oxide film inside the recess gate region; And (d) 상기 구조물 전면에 폴리실리콘층, 게이트 금속층 및 게이트 하드마스크층을 순차적으로 형성한 후 패터닝하여 게이트 패턴을 형성하는 단계;(d) sequentially forming a polysilicon layer, a gate metal layer, and a gate hard mask layer on the entire surface of the structure to form a gate pattern; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 (a) 단계 후 H2를 사용한 베이크 공정 또는 H2 및 N2 플라즈마를 이용한 클리닝 공정을 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of producing a semiconductor device, characterized in that the (a) step after performing a cleaning process using a baking process, or H 2 and N 2 with H 2 plasma more. 제 1 항에 있어서,The method of claim 1, 상기 (b) 단계의 SEG막은 B2H6, SiH4 및 HCl을 소스 가스로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The SEG film of step (b) is a method of manufacturing a semiconductor device, characterized in that to form B 2 H 6 , SiH 4 and HCl as a source gas. 제 1 항에 있어서,The method of claim 1, 상기 (b) 단계의 SEG막에 인시투 공정으로 보론 이온을 도핑시키는 것을 특징으로 하는 반도체 소자의 제조 방법.A method of manufacturing a semiconductor device, wherein the SEG film of step (b) is doped with boron ions in an in-situ process. 제 4 항에 있어서, The method of claim 4, wherein 상기 보론 이온은 1.0E18 내지 6.0E18/cm3의 농도로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법. The boron ion is a method of manufacturing a semiconductor device, characterized in that carried out at a concentration of 1.0E18 to 6.0E18 / cm 3 . 제 1 항에 있어서,The method of claim 1, 상기 SEG막은 50 내지 200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The SEG film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 50 to 200 내지. 제 1 항에 있어서, The method of claim 1, 상기 게이트 산화막은 750 내지 900℃의 퍼니스에서 20 내지 50Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The gate oxide film is a method of manufacturing a semiconductor device, characterized in that formed in a thickness of 20 to 50Å in a furnace at 750 to 900 ℃. 제 1 항에 있어서, The method of claim 1, 상기 폴리실리콘층은 인시투 공정으로 인 이온이 주입된 것을 특징으로 하는 반도체 소자의 제조 방법. The polysilicon layer is a manufacturing method of a semiconductor device, characterized in that the phosphorus ion is implanted in an in-situ process. 제 8 항에 있어서, The method of claim 8, 상기 인의 농도는 1.0E20 내지 6.0E20/cm3인 것을 특징으로 하는 반도체 소자의 제조 방법. The concentration of phosphorus is 1.0E20 to 6.0E20 / cm 3 The method of manufacturing a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 폴리실리콘층은 5 내지 80torr의 압력, 500 내지 580℃의 온도에서 500 내지 1500Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The polysilicon layer is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 500 to 1500 kPa at a pressure of 5 to 80 torr, a temperature of 500 to 580 ℃. 제 1 항에 있어서, The method of claim 1, 상기 게이트 금속층은 텅스텐 또는 텅스텐 실리사이드로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the gate metal layer is formed of tungsten or tungsten silicide.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100854501B1 (en) * 2007-02-23 2008-08-26 삼성전자주식회사 Mos transistor having a recessed channel region and methods of fabricating the same
KR100909777B1 (en) * 2006-07-28 2009-07-29 주식회사 하이닉스반도체 Manufacturing Method of Semiconductor Device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100909777B1 (en) * 2006-07-28 2009-07-29 주식회사 하이닉스반도체 Manufacturing Method of Semiconductor Device
KR100854501B1 (en) * 2007-02-23 2008-08-26 삼성전자주식회사 Mos transistor having a recessed channel region and methods of fabricating the same
US7750399B2 (en) 2007-02-23 2010-07-06 Samsung Electronics Co., Ltd. MOS transistors having recessed channel regions and methods of fabricating the same

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