KR20070002504A - Method of forming a spacer in semiconductor device - Google Patents

Method of forming a spacer in semiconductor device Download PDF

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KR20070002504A
KR20070002504A KR1020050058067A KR20050058067A KR20070002504A KR 20070002504 A KR20070002504 A KR 20070002504A KR 1020050058067 A KR1020050058067 A KR 1020050058067A KR 20050058067 A KR20050058067 A KR 20050058067A KR 20070002504 A KR20070002504 A KR 20070002504A
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spacer
etching
buffer oxide
forming
film
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KR1020050058067A
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Korean (ko)
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이재중
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
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  • General Chemical & Material Sciences (AREA)
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Abstract

A method for forming a spacer in a semiconductor device is provided to obtain a buffer oxide layer of uniform thickness by using two-step etching having different etch selectivity. A buffer oxide layer(20) and a spacer insulating layer are sequentially formed on a semiconductor substrate(10) having a gate electrode pattern(G.P). A first etching and a second etching processes are sequentially performed to the resultant structure to form a spacer(S) and a uniform buffer oxide layer, wherein the second etching is a relatively high etch selectivity against the buffer oxide layer. That is, the etch selectivity of the insulating layer against the buffer oxide layer is 15 : 1.

Description

반도체 소자의 스페이서 형성방법{Method of forming a spacer in semiconductor device}Method for forming a spacer in semiconductor device

도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리 소자의 스페이서 형성방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of forming a spacer of a flash memory device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Explanation of symbols for main parts of drawings *

G.P: 게이트 전극 패턴 S: 스페이서G.P: Gate electrode pattern S: spacer

20: 버퍼산화막20: buffer oxide film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 스페이서 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a spacer of a semiconductor device.

반도체 소자의 제조방법에 있어서, 반도체 기판내의 접합영역을 형성하기 위한 이온주입 공정시 이온주입마스크로 사용되면서 동시에 게이트 패턴 간을 절연시 키기 위해, 게이트 패턴 측벽에 스페이서막을 형성한다. In the method of manufacturing a semiconductor device, a spacer film is formed on sidewalls of a gate pattern so as to be used as an ion implantation mask during an ion implantation process for forming a junction region in a semiconductor substrate and to insulate between gate patterns.

이와 같은 역할을 수행하는 스페이서막 형성을 위한 식각 공정시, 게이트 패턴 상부 및 게이트패턴이 형성되지 않은 영역의 반도체 기판 상부에 증착 형성된 버퍼 산화막에 대한 식각선택비가 낮아서 하부의 버퍼산화막의 손실이 발생하게 되고, 일부영역에서는 버퍼 산화막뿐만 아니라 반도체 기판까지 손실되는 문제점이 발생하였다. In the etching process for forming the spacer film, which plays such a role, the etching selectivity for the buffer oxide film deposited on the semiconductor substrate in the gate pattern and the region where the gate pattern is not formed is low, resulting in loss of the buffer oxide film at the bottom. In some areas, not only the buffer oxide film but also the semiconductor substrate is lost.

또한, 손실된 버퍼 산화막의 상태에서 반도체 기판 내부에 접합영역을 형성하기 위한 이온주입공정을 수행할 때, 이온주입의 깊이 또한 불균일하게 형성되는 문제점이 있었다.In addition, when the ion implantation process for forming the junction region inside the semiconductor substrate in the state of the lost buffer oxide film, there is a problem that the depth of ion implantation is also formed unevenly.

상술한 문제점을 해결하기 위한 본 발명의 목적은 스페이서막 형성을 위한 식각 공정시 하부에 형성된 버퍼산화막의 손실을 방지할 수 있도록 하는 반도체 소자의 스페이서막 형성방법을 제공함에 있다. An object of the present invention for solving the above problems is to provide a method of forming a spacer film of a semiconductor device to prevent the loss of the buffer oxide film formed in the lower portion during the etching process for forming a spacer film.

상술한 목적을 달성하기 위한 본 발명의 사상은 게이트 전극 패턴이 형성된 반도체 기판 상부에 버퍼 산화막 및 스페이서용 절연막을 순차적으로 형성하는 단계 및 상기 절연막에 상기 스페이서 형상을 형성하는 제1 식각 및 상기 버퍼 산화막에 대해 상기 절연막의 선택비가 상기 제1 식각보다 높게 진행되도록 하는 제2 식각을 각각 수행하여 스페이서를 형성하는 단계를 포함한다.According to an aspect of the present invention, a buffer oxide film and an insulating film for a spacer are sequentially formed on a semiconductor substrate on which a gate electrode pattern is formed, and the first etching and the buffer oxide film for forming the spacer shape are formed on the insulating film. And forming a spacer by performing second etching such that the selectivity of the insulating layer is higher than the first etching.

상기 제2 식각은 상기 절연막 대 상기 버퍼산화막의 선택비가 15: 1이 되도록 수행된다.The second etching is performed such that the selectivity ratio of the insulating film to the buffer oxide film is 15: 1.

상기 제1 식각은 SF6가스, HBr가스, Cl2가스 및 O2가스의 혼합가스를 통해 수행된다.The first etching is performed through a mixed gas of SF 6 gas, HBr gas, Cl 2 gas and O 2 gas.

상기 제2 식각은 HBr가스, Cl2가스 및 O2가스의 혼합 가스를 통해 수행된다.The second etching is performed through a mixed gas of HBr gas, Cl 2 gas and O 2 gas.

상기 스페이서용 절연막은 질화막 또는 옥시나이트라이드막이 사용된다.As the insulating film for spacers, a nitride film or an oxynitride film is used.

상기 버퍼 산화막은 200~ 500Å의 두께로 형성한다.The buffer oxide film is formed to a thickness of 200 ~ 500Å.

상기 스페이서용 절연막은 50~ 1000Å의 두께로 형성한다.The spacer insulating film is formed to a thickness of 50 ~ 1000Å.

상기 스페이서가 형성된 후, 상기 스페이서, 버퍼산화막 및 상기 게이트전극패턴을 이온주입마스크로 이온주입공정을 수행하여, 반도체 기판 내부에 접합영역을 형성하는 단계 및 상기 접합영역이 형성된 결과물의 스페이서를 제거하는 단계를 더 포함한다.After the spacer is formed, an ion implantation process is performed on the spacer, the buffer oxide layer, and the gate electrode pattern using an ion implantation mask to form a junction region in the semiconductor substrate, and to remove the spacer of the resultant region on which the junction region is formed. It further comprises a step.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리 소자의 스페이서 형성방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of forming a spacer of a flash memory device according to the present invention.

도 1을 참조하면, 터널 산화막(미도시), 플로팅 게이트 전극용 제1 폴리 실리콘막(12), ONO막(14), 콘트롤 게이트 전극용 제2 폴리 실리콘막(16), 금속 실리사이드막(18)막들이 패터닝되어 형성된 게이트 전극 패턴(G.P)이 반도체 기판(10) 상에 형성되어 있다. Referring to FIG. 1, a tunnel oxide film (not shown), a first polysilicon film 12 for floating gate electrodes, an ONO film 14, a second polysilicon film 16 for a control gate electrode, and a metal silicide film 18 The gate electrode pattern GP formed by patterning the films is formed on the semiconductor substrate 10.

이어서, 상기 게이트 전극패턴(G.P)이 형성된 결과물의 경계를 따라 버퍼 산화막(20) 및 스페이서용 절연막(22)을 순차적으로 형성한다. Subsequently, the buffer oxide film 20 and the spacer insulating film 22 are sequentially formed along the boundary of the resultant product in which the gate electrode pattern G.P is formed.

상기 스페이서용 절연막은 질화막, 옥시나이트라이드막이 사용될 수도 있다. As the insulating film for the spacer, a nitride film or an oxynitride film may be used.

상기 버퍼 산화막(20)은 200~ 500Å 정도의 두께로 형성하고, 상기 스페이서용 절연막은 50~ 1000Å 정도의 두께로 형성한다. The buffer oxide film 20 is formed to a thickness of about 200 to 500 kPa, and the insulating film for spacers is formed to a thickness of about 50 to 1000 kPa.

도 2를 참조하면, 상기 스페이서용 절연막(22)이 형성된 결과물 상에 스페이서 형성을 위한 식각공정을 수행하여, 스페이서(S)를 형성한다. Referring to FIG. 2, the spacer S is formed by performing an etching process for forming a spacer on a resultant on which the insulating film 22 for spacers is formed.

상기 스페이서를 형성하기 위한 식각공정은 제1 식각 및 제2 식각으로 나누어 수행하는 데, 상기 제1 식각은 상기 버퍼 산화막(20)이 노출되기 전까지 스페이서용 절연막(22)을 식각하고, 상기 제2 식각은 상기 버퍼 산화막(20)이 노출되도록 스페이서용 절연막(22)을 식각한다. 이때, 상기 버퍼산화막의 식각이 방지되도록 한다. An etching process for forming the spacer is performed by dividing the first etching and the second etching, wherein the first etching etches the spacer insulating film 22 until the buffer oxide film 20 is exposed, and the second etching is performed. Etching etches the spacer insulating film 22 to expose the buffer oxide film 20. At this time, the etching of the buffer oxide film is prevented.

상기 제1 식각은 스페이서의 형상을 형성하기 위한 식각공정이 수행되되, 상기 절연막인 질화막(22) 식각시 버퍼 산화막(20)에 대한 선택비를 낮게 진행하도록 하는 공정조건을 사용한다. 이때, 상기 버퍼 산화막(20)이 노출되기 전까지 식각공정이 수행되어야 한다. In the first etching process, an etching process for forming the shape of the spacer is performed, and a process condition for lowering the selectivity with respect to the buffer oxide film 20 when the nitride film 22 is etched is used. In this case, an etching process should be performed until the buffer oxide film 20 is exposed.

상기 제2 식각은 상기 제1 식각에 대한 과식각이 수행되되, 상기 절연막인 질화막 식각시 산화막에 대한 선택비를 높게 진행되도록 하는 공정조건 즉, 질화막 (22)대 산화막(20)의 선택비가 15: 1이 되도록 하는 공정조건을 사용한다. 이때, 상기 제1 식각을 통해 노출된 버퍼 산화막(20)이 상기 제2 식각을 통해 제거되는 것이 방지되도록 식각공정이 수행되어야 한다. In the second etching process, the over-etching of the first etching is performed, but the process conditions for increasing the selectivity of the oxide film during the etching of the nitride film as the insulating film, that is, the selectivity of the nitride film 22 to the oxide film 20 is 15. Use the process conditions to be 1. In this case, an etching process should be performed to prevent the buffer oxide layer 20 exposed through the first etching from being removed through the second etching.

상기 제1 식각은 SF6가스, HBr, Cl2 및 O2가스의 혼합가스를 통해 수행되고, 상기 제2 식각은 HBr, Cl2 및 O2가스의 혼합가스를 통해 수행된다. The first etching is performed through a mixed gas of SF 6 gas, HBr, Cl 2 and O 2 gas, the second etching is performed through a mixed gas of HBr, Cl 2 and O 2 gas.

따라서 스페이서(S)를 형성하기 위해, 상기 제1 및 제2 식각이 수행되면, 스페이서(S)가 형성되면서 동시에 상기 버퍼 산화막(20)의 식각이 방지됨으로써, 균일한 두께의 버퍼산화막을 갖게 되어 반도체 기판의 노출이 방지된다. Therefore, when the first and second etchings are performed to form the spacers S, the spacers S are formed and the etching of the buffer oxide layer 20 is prevented at the same time, thereby having a buffer oxide layer having a uniform thickness. Exposure of the semiconductor substrate is prevented.

도 3을 참조하면, 상기 스페이서(S)가 형성된 결과물 전면에 이온주입공정을 수행하여, 반도체 기판(10) 내부 소정영역에 접합영역(24)을 형성한다. Referring to FIG. 3, an ion implantation process is performed on the entire surface of the resultant product on which the spacers S are formed to form a junction region 24 in a predetermined region inside the semiconductor substrate 10.

상기 접합영역을 형성하기 위한 이온주입용 마스크는 게이트전극패턴(G.P)과 스페이서(S)이다. The ion implantation mask for forming the junction region is a gate electrode pattern (G.P) and a spacer (S).

상기 스페이서(S)형성 공정시 균일한 두께를 갖는 상기 버퍼 산화막(20)으로 인해, 상기 접합영역(24)을 형성하는 이온주입의 깊이 또한 균일하게 된다. Due to the buffer oxide film 20 having a uniform thickness during the spacer S formation process, the depth of ion implantation forming the junction region 24 is also uniform.

도 4를 참조하면, 이온주입공정이 완료된 결과물 상에 스페이서(S)를 제거하는 식각공정이 수행됨으로써, 본 공정은 완료된다. Referring to FIG. 4, an etching process of removing the spacers S on the resultant of the ion implantation process is performed, thereby completing the present process.

상기 균일한 두께를 가지면서 반도체 기판의 노출이 방지된 버퍼 산화막(20)으로 인해, 상기 스페이서 제거 공정시 반도체 기판의 손상이 방지될 수 있다. Due to the buffer oxide layer 20 having the uniform thickness and preventing the exposure of the semiconductor substrate, damage to the semiconductor substrate may be prevented during the spacer removal process.

본 발명에 의하면, 스페이서를 형성하기 위해, 상기 절연막인 질화막 식각시 버퍼 산화막에 대한 선택비를 낮게 진행하도록 하는 제1 식각 및 상기 절연막인 질화막 식각시 버퍼 산화막에 대한 선택비를 높게 진행하도록 하는 제2 식각이 수행되면, 스페이서가 형성되면서 동시에 상기 버퍼 산화막의 식각이 방지됨으로써, 균일한 두께의 버퍼 산화막을 갖게 되고, 이 버퍼 산화막으로 인해 이온주입의 깊이 또한 균일해지고, 스페이서 제거공정시 반도체 기판의 노출이 방지될 수 있다. According to the present invention, in order to form a spacer, the first etching to lower the selectivity to the buffer oxide film during the etching of the nitride film as the insulating film and the selectivity to increase the selectivity with respect to the buffer oxide film during the nitride film etching as the insulating film When etching is performed, the spacer is formed and the etching of the buffer oxide film is prevented at the same time, so that the buffer oxide film has a uniform thickness, and the depth of ion implantation becomes uniform due to the buffer oxide film, and the semiconductor substrate is removed during the spacer removal process. Exposure can be prevented.

이상에서 살펴본 바와 같이 본 발명에 의하면, 스페이서를 형성하기 위해, 상기 절연막인 질화막 식각시 버퍼 산화막에 대한 선택비를 낮게 진행하도록 하는 제1 식각 및 상기 절연막인 질화막 식각시 버퍼 산화막에 대한 선택비를 높게 진행하도록 하는 제2 식각이 수행되면, 스페이서가 형성되면서 동시에 상기 버퍼 산화막의 식각이 방지됨으로써, 균일한 두께의 버퍼 산화막을 갖게 되는 효과가 있다. As described above, according to the present invention, in order to form the spacer, the selectivity of the first etching to lower the selectivity to the buffer oxide layer during the etching of the nitride film, which is the insulating film, and the selection ratio of the buffer oxide film during the nitride film etching, the insulating film, When the second etching is performed to proceed high, the spacer is formed and the etching of the buffer oxide film is prevented at the same time, thereby having a buffer oxide film having a uniform thickness.

따라서 상기 버퍼 산화막으로 인해 접합영역을 형성하는 이온주입의 깊이 또한 균일해지고, 스페이서 제거공정시 반도체 기판의 노출이 방지될 수 있는 효과가 있다. Therefore, the depth of the ion implantation forming the junction region is also uniform due to the buffer oxide film, and the exposure of the semiconductor substrate can be prevented during the spacer removal process.

본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.

Claims (8)

게이트 전극 패턴이 형성된 반도체 기판 상부에 버퍼 산화막 및 스페이서용 절연막을 순차적으로 형성하는 단계; 및Sequentially forming a buffer oxide film and an insulating film for a spacer on the semiconductor substrate on which the gate electrode pattern is formed; And 상기 절연막에 상기 스페이서 형상을 형성하는 제1 식각 및 상기 버퍼 산화막에 대해 상기 절연막의 선택비가 상기 제1 식각보다 높게 진행되도록 하는 제2 식각을 각각 수행하여 스페이서를 형성하는 단계를 포함하는 반도체소자의 스페이서 형성방법. Forming a spacer by performing a first etching forming the spacer shape on the insulating layer and a second etching on the buffer oxide layer so that the selectivity of the insulating layer is higher than the first etching. Spacer formation method. 제1 항에 있어서, 상기 제2 식각은The method of claim 1, wherein the second etching is 상기 절연막 대 상기 버퍼산화막의 선택비가 15: 1이 되도록 수행되는 반도체소자의 스페이서 형성방법. And a selectivity ratio of the insulating film to the buffer oxide film is 15: 1. 제1 항에 있어서, 상기 제1 식각은 The method of claim 1, wherein the first etching is SF6가스, HBr가스, Cl2가스 및 O2가스의 혼합가스를 통해 수행되는 반도체소자의 스페이서 형성방법. A method of forming a spacer of a semiconductor device, which is performed through a mixed gas of SF 6 gas, HBr gas, Cl 2 gas, and O 2 gas. 제1 항에 있어서, 상기 제2 식각은 The method of claim 1, wherein the second etching is HBr가스, Cl2가스 및 O2가스의 혼합 가스를 통해 수행되는 반도체소자의 스페이서 형성방법. A method of forming a spacer of a semiconductor device performed through a mixed gas of HBr gas, Cl 2 gas and O 2 gas. 제1 항에 있어서, 상기 스페이서용 절연막은 The method of claim 1, wherein the insulating film for spacers 질화막 또는 옥시나이트라이드막이 사용되는 반도체소자의 스페이서 형성방법. A method of forming a spacer in a semiconductor device in which a nitride film or an oxynitride film is used. 제1 항에 있어서, 상기 버퍼 산화막은 The method of claim 1, wherein the buffer oxide film 200~ 500Å의 두께로 형성하는 반도체소자의 스페이서 형성방법. Spacer forming method of a semiconductor device to form a thickness of 200 ~ 500Å. 제1 항에 있어서, 상기 스페이서용 절연막은 The method of claim 1, wherein the insulating film for spacers 50~ 1000Å의 두께로 형성하는 반도체소자의 스페이서 형성방법. Spacer forming method of a semiconductor device to form a thickness of 50 ~ 1000 ~. 제1 항에 있어서, 상기 스페이서가 형성된 후, The method of claim 1, wherein after the spacer is formed, 상기 스페이서, 버퍼산화막 및 상기 게이트전극패턴을 이온주입마스크로 이온주입공정을 수행하여, 반도체 기판 내부에 접합영역을 형성하는 단계 및 Forming a junction region in the semiconductor substrate by performing an ion implantation process on the spacer, the buffer oxide layer and the gate electrode pattern with an ion implantation mask; and 상기 접합영역이 형성된 결과물의 스페이서를 제거하는 단계를 더 포함하는 반도체 소자의 스페이서 형성방법. And removing a spacer of the resultant product in which the junction region is formed.
KR1020050058067A 2005-06-30 2005-06-30 Method of forming a spacer in semiconductor device KR20070002504A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929239B1 (en) * 2006-11-27 2009-12-01 삼성전자주식회사 How to form a field effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929239B1 (en) * 2006-11-27 2009-12-01 삼성전자주식회사 How to form a field effect transistor

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