KR20060133803A - Method for forming step gate of semiconductor device - Google Patents

Method for forming step gate of semiconductor device Download PDF

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KR20060133803A
KR20060133803A KR1020050053646A KR20050053646A KR20060133803A KR 20060133803 A KR20060133803 A KR 20060133803A KR 1020050053646 A KR1020050053646 A KR 1020050053646A KR 20050053646 A KR20050053646 A KR 20050053646A KR 20060133803 A KR20060133803 A KR 20060133803A
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gate
oxide film
film
active region
sacrificial oxide
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KR1020050053646A
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Korean (ko)
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천성길
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for forming a stepped gate of a semiconductor device is provided to prevent the fall-down of a gate by reinforcing the adhesiveness between the gate and a substrate using a horn type stepped portion formed at both sides of a substrate active region. A sacrificial oxide layer is formed on a semiconductor substrate(21) with an isolation layer(22) capable of defining an active region. A stepped portion is formed at both sides of the active region by etching selectively the sacrificial oxide layer and substrate. A buffer oxide layer is selectively formed on the resultant structure. A nitride layer is formed on the buffer oxide layer and the sacrificial oxide layer. A CMP process is performed on the nitride layer until the sacrificial oxide layer is exposed to the outside. The sacrificial oxide layer is removed therefrom. At this time, a horn type stepped portion is formed at both sides of the active region.

Description

반도체 소자의 단차 게이트 형성방법{Method for forming step gate of semiconductor device}Method for forming step gate of semiconductor device

도 1a 내지 도 1c는 종래의 반도체 소자의 단차 게이트 형성방법을 설명하기 위한 공정별 단면도.1A to 1C are cross-sectional views illustrating processes for forming a stepped gate of a conventional semiconductor device.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 단차 게이트 형성방법을 설명하기 위한 공정별 단면도.2A to 2D are cross-sectional views illustrating processes for forming a stepped gate of a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21: 반도체 기판 22: 소자분리막21: semiconductor substrate 22: device isolation film

23: 희생산화막 24: 버퍼산화막23: sacrificial oxide film 24: buffer oxide film

25: 질화막 26: 게이트산화막25: nitride film 26: gate oxide film

27: 게이트도전막 28: 하드마스크막27: gate conductive film 28: hard mask film

29: 게이트29: gate

본 발명은 반도체 소자의 제조방법에 관한것으로, 보다 상세하게는, 단차 게이트(Step Gate) 형성시, 게이트의 쓰러짐 현상(leaning)을 방지하는 반도체 소자 의 단차 게이트 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a stepped gate of a semiconductor device that prevents the gate from falling when forming a step gate.

반도체 소자의 고집적화에 따라 게이트 전극의 선폭 감소가 진행되고 있는 추세에서, 상기 게이트 전극의 선폭 감소는 채널 길이의 감소를 초래하게 되어 문턱 전압(Vt)이 급격하게 줄어드는 단채널효과(Short Channel Effect)를 유발하게 되고, 이로 인해, 트랜지스터 및 소자 특성의 저하가 야기된다. As the line width of the gate electrode decreases as the semiconductor device is highly integrated, the decrease of the line width of the gate electrode causes a decrease in the channel length, and thus, a short channel effect in which the threshold voltage Vt decreases rapidly. This leads to deterioration of transistor and device characteristics.

이러한 단채널효과를 감소시키기 위해 채널 도핑 불순물을 과도하게 주입하게 되는데, 이로 인하여 소자의 결함(defect) 및 트랩(trap)이 증가하여 리프레쉬(refresh)특성을 감소시키게 된다.In order to reduce the short channel effect, channel doping impurities are excessively injected, thereby increasing the defects and traps of the device, thereby reducing the refresh characteristics.

따라서, 반도체 소자의 고집적화를 위해서는 상기 단채널효과의 방지가 반듯이 해결되어야 할 과제이다Therefore, the prevention of the short channel effect must be solved for high integration of semiconductor devices.

최근에는, 단차 게이트(STep Gate)로 채널길이를 증가시킬 수 있도록 하고 있다.Recently, the channel length can be increased by a step gate.

여기서, 현재 수행되고 있는 단차 게이트 형성방법을 도 1a 내지 도 1c를 참조하여 간략하게 설명하도록 한다.Here, a method of forming a stepped gate currently being performed will be briefly described with reference to FIGS. 1A to 1C.

도 1a를 참조하면, 소자분리막(2)과 액티브영역을 갖는 반도체 기판(1) 상에 감광막패턴(3)을 액티브영역 중심부에 형성한다.Referring to FIG. 1A, a photoresist pattern 3 is formed on a center portion of an active region on a semiconductor substrate 1 having an isolation region 2 and an active region.

도 1b를 참조하면, 상기 감광막패턴을 식각마스크로 이용하여 액티브영역의 양측부가 단차가 생기도록 상기 기판(1)을 일부 두께를 식각한다.Referring to FIG. 1B, the substrate 1 is partially etched by using the photoresist pattern as an etching mask so that both sides of the active region have a step.

다음으로, 상기 식각된 기판 전면 상에 게이트산화막(4)을 형성한다. Next, a gate oxide film 4 is formed on the entire surface of the etched substrate.

도 1c를 참조하면, 상기 게이트산화막(4) 상에 게이트(5)를 형성한다.Referring to FIG. 1C, a gate 5 is formed on the gate oxide film 4.

그러나, 전술한 바와 같은 종래의 단차 게이트 형성방법은 다음과 같은 문제점이 있다.However, the conventional stepped gate forming method as described above has the following problems.

단차 게이트를 형성하여 채널 길이를 증가시킴으로써 단채널효과를 극복할 수 있으나, 식각되는 액티브 영역 상측 게이트에서 라운드 토플러지가 파괴되어 게이트가 단차의 바깥쪽으로 기울어져 인접한 게이트와 만나는 리닝(leaning) 현상이 발생하여 셀 소자의 특성을 감소시킨다.The short channel effect can be overcome by increasing the channel length by forming the stepped gate, but the round top-flush is destroyed in the upper gate of the etched active region, which causes the gate to lean outward to meet the adjacent gate. Thereby reducing the characteristics of the cell device.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, 게이트의 쓰러짐 현상을 방지할 수 있는 반도체 소자의 단차 게이트 형성방법을 제공함에 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a stepped gate of a semiconductor device capable of preventing the gate from falling down, which is devised to solve the conventional problems as described above.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 액티브영역을 한정하는 소자분리막이 구비된 반도체 기판 상에 희생산화막을 형성하는 단계; 상기 액티브영역의 양측부가 단차가 생기도록 상기 희생산화막과 기판 일부 두께를 식각하는 단계; 상기 식각된 기판 표면 상에 버퍼산화막을 형성하는 단계; 상기 버퍼산화막 및 희생산화막 상에 질화막을 형성하는 단계; 상기 희생산화막이 노출될 때까지 질화막을 CMP하는 단계; 상기 희생산화막을 제거하는 단계; 상기 희생산화막이 제거되어 노출된 액티브영역 부분을 그 양측 가장자리가 혼 모양으로 단차지게 식각하는 단계; 상기 잔류된 질화막 및 버퍼산화막을 제거하는 단계; 상기 기판 표면 상에 게이트절연막과 게이트도전막을 차례로 형성하는 단계; 및 상기 혼 모양으로 단차 진 액티브영역 부분 및 그 주변에 잔류되게 상기 게이트도전막과 게이트절연막을 식각하는 단계;를 포함하는 반도체 소자의 단차 게이트 형성방법을 제공한다.In order to achieve the above object, the present invention, forming a sacrificial oxide film on a semiconductor substrate having a device isolation film defining an active region; Etching the thickness of the sacrificial oxide film and a portion of the substrate such that both sides of the active region have a step; Forming a buffer oxide layer on the etched substrate surface; Forming a nitride film on the buffer oxide film and the sacrificial oxide film; CMP the nitride film until the sacrificial oxide film is exposed; Removing the sacrificial oxide film; Etching the portions of the active region exposed by removing the sacrificial oxide layer so that both edges thereof step into a horn shape; Removing the remaining nitride film and the buffer oxide film; Sequentially forming a gate insulating film and a gate conductive film on the substrate surface; And etching the gate conductive film and the gate insulating film so as to remain in the horn-shaped stepped active region and the periphery thereof.

(실시예) (Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 단차 게이트 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2D are cross-sectional views illustrating processes for forming a stepped gate of a semiconductor device according to the present invention.

도 2a를 참조하면, 반도체 기판(21)의 각 지역에 STI(Shallow Trench Isolation) 공정에 따라 액티브영역을 한정하는 소자분리막들(22)을 형성한다.Referring to FIG. 2A, device isolation layers 22 defining active regions are formed in each region of the semiconductor substrate 21 according to a shallow trench isolation (STI) process.

다음으로, 상기 기판 상에 열산화 공정을 통해 희생산화막(23)을 증착한다.Next, a sacrificial oxide film 23 is deposited on the substrate through a thermal oxidation process.

계속해서, 상기 액티브영역의 양측부가 단차가 생기도록 상기 희생산화막(23)과 기판(21) 일부 두께를 식각한다. 이때, 상기 기판(21)은 단차 모양으로 형성된다.Subsequently, portions of the sacrificial oxide film 23 and the substrate 21 are etched so that both side portions of the active region have a step. At this time, the substrate 21 is formed in a stepped shape.

도 2b를 참조하면, 상기 식각된 기판(21) 표면 상에 열산화 공정을 통해 버퍼산화막(24)을 증착한다.Referring to FIG. 2B, a buffer oxide layer 24 is deposited on the surface of the etched substrate 21 through a thermal oxidation process.

다음으로, 상기 버퍼산화막(24) 및 희생산화막(23) 상에 질화막(25)을 증착한다.Next, a nitride film 25 is deposited on the buffer oxide film 24 and the sacrificial oxide film 23.

계속해서, 상기 희생산화막(23)이 노출될 때까지 질화막(25)을 CMP(chemical mechanical polishing)한다.Subsequently, the nitride film 25 is subjected to chemical mechanical polishing (CMP) until the sacrificial oxide film 23 is exposed.

도 2c를 참조하면, 상기 희생산화막을 제거한 후, 상기 희생산화막이 제거되 어 노출된 액티브영역 부분을 그 양측 가장자리가 혼 모양으로 단차지게 식각한다.Referring to FIG. 2C, after the sacrificial oxide film is removed, the sacrificial oxide film is removed to etch the exposed portion of the active region in a stepped shape in a horn shape.

여기서, 본 발명은 상기 액티브영역 양측부에 혼 모양의 단차를 형성함으로써, 후속 게이트형성시 게이트와 기판사이의 견착력을 증대시켜 단차에 의해서 게이트의 쓰러짐 현상을 방지할 수 있을뿐만 아니라, 액티브 영역의 면적을 증가시키는 효과로 인하여 게이트 채널 길이가 증가하게 된다.Here, the present invention forms a horn-shaped step on both sides of the active region, thereby increasing adhesion between the gate and the substrate during subsequent gate formation, thereby preventing the gate from falling down due to the step, and also in the active region. Due to the effect of increasing the area of the gate channel length is increased.

도 2d를 참조하면, 상기 잔류된 질화막 및 버퍼산화막을 제거한다.Referring to FIG. 2D, the remaining nitride film and the buffer oxide film are removed.

다음으로, 상기 기판 표면 상에 게이트산화막(26)을 증착한다.Next, a gate oxide film 26 is deposited on the substrate surface.

계속해서, 상기 게이트산화막(26) 상에 게이트도전막(27)과 하드마스크막(28)을 차례로 증착한 후, 상기 혼 모양으로 단차진 액티브영역 부분 및 그 주변에 잔류되게 상기 하드마스크막(28)과 게이트도전막(27)을 식각하여 본 발명에 따른 단차 게이트(29) 형성을 완성한다.Subsequently, the gate conductive film 27 and the hard mask film 28 are sequentially deposited on the gate oxide film 26, and then the hard mask film ( 28 and the gate conductive film 27 are etched to complete the formation of the stepped gate 29 according to the present invention.

이상에서와 같이, 본 발명은 단차 게이트 형성시, 액티브영역 양측부에 혼(horn) 모양의 단차를 형성하여 게이트와 기판사이의 견착력을 증대시켜 게이트의 쓰러짐 현상을 방지할 수 있다.As described above, in the present invention, when the stepped gate is formed, a horn-shaped step is formed at both sides of the active region to increase the adhesion between the gate and the substrate, thereby preventing the gate from falling down.

따라서, 게이트의 쓰러짐 현상을 방지하여 공정 마진을 개선하고, 셀의 안정적인 동장 성능을 확보하여 불량률을 낮출 수 있으며, 반도체 소자의 전기적 특성 및 리프레쉬 특성을 향상시킬 수 있는 효과가 있다.Therefore, it is possible to prevent the gate from falling down, thereby improving process margins, securing stable copper field performance of the cell, thereby lowering a defect rate, and improving electrical and refresh characteristics of the semiconductor device.

또한, 단차 게이트 구조의 반도체 소자를 형성함으로써, 단채널효과를 해결할 수 있다. In addition, the short channel effect can be solved by forming a semiconductor element having a stepped gate structure.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (1)

액티브영역을 한정하는 소자분리막이 구비된 반도체 기판 상에 희생산화막을 형성하는 단계; Forming a sacrificial oxide film on a semiconductor substrate having a device isolation film defining an active region; 상기 액티브영역의 양측부가 단차가 생기도록 상기 희생산화막과 기판 일부 두께를 식각하는 단계; Etching the thickness of the sacrificial oxide film and a portion of the substrate such that both sides of the active region have a step; 상기 식각된 기판 표면 상에 버퍼산화막을 형성하는 단계; Forming a buffer oxide layer on the etched substrate surface; 상기 버퍼산화막 및 희생산화막 상에 질화막을 형성하는 단계; Forming a nitride film on the buffer oxide film and the sacrificial oxide film; 상기 희생산화막이 노출될 때까지 질화막을 CMP하는 단계; CMP the nitride film until the sacrificial oxide film is exposed; 상기 희생산화막을 제거하는 단계; Removing the sacrificial oxide film; 상기 희생산화막이 제거되어 노출된 액티브영역 부분을 그 양측 가장자리가 혼 모양으로 단차지게 식각하는 단계; Etching the portions of the active region exposed by removing the sacrificial oxide layer so that both edges thereof step into a horn shape; 상기 잔류된 질화막 및 버퍼산화막을 제거하는 단계; Removing the remaining nitride film and the buffer oxide film; 상기 기판 표면 상에 게이트산화막을 형성하는 단계;Forming a gate oxide film on the substrate surface; 상기 게이트산화막 상에 게이트도전막과 하드마스크막을 차례로 형성하는 단계; 및 상기 혼 모양으로 단차진 액티브영역 부분 및 그 주변에 잔류되게 상기 게이트도전막과 하드마스크를 식각하는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 단차 게이트 형성방법. Sequentially forming a gate conductive film and a hard mask film on the gate oxide film; And etching the gate conductive film and the hard mask so as to remain in the horn-shaped stepped active region and the periphery thereof.
KR1020050053646A 2005-06-21 2005-06-21 Method for forming step gate of semiconductor device KR20060133803A (en)

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