KR20090090712A - Merhod of manufacturing semiconductor device - Google Patents

Merhod of manufacturing semiconductor device Download PDF

Info

Publication number
KR20090090712A
KR20090090712A KR1020080016121A KR20080016121A KR20090090712A KR 20090090712 A KR20090090712 A KR 20090090712A KR 1020080016121 A KR1020080016121 A KR 1020080016121A KR 20080016121 A KR20080016121 A KR 20080016121A KR 20090090712 A KR20090090712 A KR 20090090712A
Authority
KR
South Korea
Prior art keywords
film
gate
forming
layer
etching
Prior art date
Application number
KR1020080016121A
Other languages
Korean (ko)
Inventor
김종만
김현수
서원준
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080016121A priority Critical patent/KR20090090712A/en
Publication of KR20090090712A publication Critical patent/KR20090090712A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an isolation layer in an isolation region of a semiconductor substrate, etching an upper end of the isolation layer, and performing an etching process using the hard mask pattern. Forming a recess region in an active region of the semiconductor substrate, forming a gate insulating film, a gate conductive film, a gate electrode film, and a hard mask film on the entire structure including the recess region, the hard mask film, Etching the gate electrode layer and the gate conductive layer to form a gate pattern, forming a spacer on sidewalls of the gate pattern, and forming a contact by filling a conductive material in a space between the spacers; do.

Description

Method of manufacturing a semiconductor device {Merhod of manufacturing semiconductor device}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recess gate structure.

As the degree of integration of integrated circuit semiconductor devices increases and design rules rapidly decrease, the difficulty in securing stable operation of transistors is increasing. For example, as the design rule of the integrated circuit device is reduced, the width of the gate decreases, and thus the channel length of the transistor decreases rapidly. Accordingly, a short channel effect frequently occurs.

Due to this short channel effect, punch-through occurs seriously between the source and the drain of the transistor, which is recognized as a major cause of malfunction of the transistor device. In order to overcome this short channel effect, various methods have been studied to secure the channel length even though the design rule is reduced. In particular, the structure extends the channel length while maintaining the limited gate line width. The recess recesses the semiconductor substrate and the recess region is adopted as the gate structure to further extend the effective channel length. A semiconductor device having a gate has been proposed.

1 and 2 are a plan view and a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device having a recess gate according to the prior art.

1 and 2, a parallel recess gate pattern 13 is formed on the semiconductor substrate 10 divided into the active region 11 and the device isolation region 12 of the semiconductor substrate.

In this case, the recess gate pattern 13 formed on the isolation region 12 may be in electrical contact with the adjacent recess gate pattern 13 during a subsequent bit line node contact forming process. After etching the recess region in the semiconductor substrate 10, the opening of the recess pattern of the device isolation region 12 may be widened during the cleaning process to remove the abnormal oxide layer, and thus may be electrically connected to the adjacent gate.

This occurs because the degree of hardening (SiO 2 ) of the SOD material constituting the device isolation region 12 varies depending on the depth of the device isolation region, making it difficult to control the amount of recess.

The technical problem to be achieved by the present invention is to etch the upper end of the isolation layer in the recess gate formation process of the semiconductor device more than the depth of the recess gate to be subsequently etched to block the electrical contact with the gate during the subsequent contact formation process There is provided a method of manufacturing a semiconductor device capable of reducing defects.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an isolation layer in an isolation region of a semiconductor substrate, etching an upper end of the isolation layer, and performing an etching process using the hard mask pattern. Forming a recess region in an active region of the semiconductor substrate, forming a gate insulating film, a gate conductive film, a gate electrode film, and a hard mask film on the entire structure including the recess region, and forming the hard mask. Etching a layer, the gate electrode layer, and the gate conductive layer to form a gate pattern, forming a spacer on sidewalls of the gate pattern, and forming a contact by filling a conductive material in a space between the spacers It includes.

The etching of the upper end of the device isolation layer may be performed such that the upper end of the device isolation layer is lower than the bottom of the recess region.

After etching the upper end of the device isolation layer, forming a buffer film on the upper end of the device isolation layer further comprises reducing the step with the active region.

The buffer film is formed of a photoresist film.

The contact is formed at an upper end of the device isolation layer, and is formed to be electrically spaced apart from the adjacent gate pattern by the spacer.

The gate insulating film is formed of an oxide film, the gate conductive film is formed of a polysilicon film, and the gate electrode film is formed of a tungsten film.

According to an embodiment of the present invention, during the recess gate forming process of the semiconductor device, the upper end portion of the isolation layer is etched more than the depth of the recess gate which is subsequently etched to block electrical contact with the gate during the subsequent contact forming process. It can reduce the defect of.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3A to 3G are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a device isolation trench 101 is formed by etching the device isolation region B of the semiconductor substrate 100 including the active region A and the device isolation region B of the semiconductor device to a predetermined depth. do. After that, the insulating film for element isolation 102 is formed over the entire structure. In this case, it is preferable that the isolation film 102 for element isolation be formed of an SOD film.

Referring to FIG. 3B, an etching process is performed to leave the insulating film 102 for device isolation on the bottom of the trench 101 for device isolation. In this case, it is preferable to control the thickness of the isolation layer 102 to be etched to be larger than the depth of the recess gate to be subsequently formed. That is, the upper end of the remaining isolation layer insulating film 102 is formed to be lower than the bottom of the recess gate formed subsequently.

Thereafter, after forming the screen oxide film 103 for the ion implantation process performed to adjust the threshold voltage on the entire structure including the element isolation insulating film 102, the ion implantation process is performed.

Referring to FIG. 3C, a buffer film 104 is formed on the screen oxide film 103 formed in the device isolation region B. Referring to FIG. This is to reduce the level difference between the upper end portion of the device isolation trench 101 and the active region A so as to form subsequent films. The buffer film 104 is preferably formed of a photoresist film.

Thereafter, the hard mask film 105 and the antireflection film 106 are formed over the entire structure including the buffer film 104. Thereafter, the photoresist pattern 107 is formed on the antireflection film 106. The hard mask film 105 is preferably formed of an amorphous carbon film.

Referring to FIG. 3D, an antireflection film and a hard mask film are patterned by an etching process using a photoresist pattern. Thereafter, an etching process using the patterned hard mask layer as an etching mask is performed to etch the active region A to a predetermined depth to form a recess gate. At this time, the insulating film 102 for device isolation is not etched by the buffer film.

Thereafter, a washing process is performed to remove the buffer film and the screen oxide film. Thereafter, the gate insulating film 108 is formed. The gate insulating film 108 is preferably formed of an oxide film. In this case, the screen oxide layer may be removed and the thickness of the screen oxide layer may be increased to form the gate insulating layer 108.

Referring to FIG. 3E, the gate conductive layer 109, the metal barrier layer 110, the gate electrode layer 111, the first hard mask layer 112, and the second hard layer are formed on the entire structure including the gate insulating layer 108. The mask film 113, the antireflection film 114, and the photoresist pattern 115 are formed.

The gate conductive film 109 is preferably formed of a polysilicon film. The gate electrode film 111 is preferably formed of a tungsten film. The first hard mask film 112 is preferably formed of a nitride film. The second hard mask film 113 is preferably formed of an amorphous carbon film.

Referring to FIG. 3F, an etching process using a photoresist pattern is performed to pattern the second hard mask film and the first hard mask film. Thereafter, an etching process using the patterned first hard mask layer is performed to pattern the gate electrode layer 111, the metal barrier layer 110, and the gate conductive layer 109 to form the gate patterns 112, 111, 110, and 109. ).

Referring to FIG. 3G, spacer layers 116 are formed on sidewalls of the gate patterns 112, 111, 110, and 109. Thereafter, a contact material is formed on the entire structure including the spacer 116 to form a contact 117 (source contact). In this case, the contact 117 formed in the device isolation region B is formed on the device isolation insulating film 102 having a flat top surface, and the sidewall is protected by the spacer 116 so that the contact 117 is not in contact with the adjacent gate.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 and 2 are a plan view and a cross-sectional view of a device for explaining a method of manufacturing a semiconductor device having a recess gate according to the prior art.

3A to 3G are cross-sectional views of devices for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of Signs for Main Parts of Drawings>

100 semiconductor substrate 101 trench for device isolation

102 insulating film for device isolation 103 string oxide film

104: buffer film 105: hard mask film

106: antireflection film 107: photoresist pattern

108: gate insulating film 109: conductive film for gate

110 metal barrier layer 111 gate electrode film

112: first hard mask film 113: second hard mask film

114: antireflection film 115: photoresist pattern

116: spacer 117: contact

Claims (8)

Forming an isolation layer in the isolation region of the semiconductor substrate; Etching the upper end of the device isolation layer; Forming a recessed region in an active region of the semiconductor substrate by performing an etching process using the hard mask pattern; Forming a gate insulating film, a gate conductive film, a gate electrode film, and a hard mask film on the entire structure including the recess region; Etching the hard mask layer, the gate electrode layer, and the gate conductive layer to form a gate pattern; Forming a spacer on sidewalls of the gate pattern; And Forming a contact by filling a conductive material in a space between the spacers. The method of claim 1, And etching the upper end of the device isolation layer so that the upper end of the device isolation layer is lower than a bottom surface of the recess region. The method of claim 1, And etching the upper end of the device isolation layer, thereby forming a buffer layer on the upper end of the device isolation layer to reduce the step difference with the active region. According to claim 3, And the buffer film is formed of a photoresist film. The method of claim 1, The contact is formed on an upper end of the device isolation layer, and the semiconductor device manufacturing method of the spaced apart from the adjacent gate pattern by the spacer. The method of claim 1, And the gate insulating film is formed of an oxide film. The method of claim 1, And the gate conductive film is formed of a polysilicon film. The method of claim 1, And the gate electrode film is formed of a tungsten film.
KR1020080016121A 2008-02-22 2008-02-22 Merhod of manufacturing semiconductor device KR20090090712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080016121A KR20090090712A (en) 2008-02-22 2008-02-22 Merhod of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080016121A KR20090090712A (en) 2008-02-22 2008-02-22 Merhod of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20090090712A true KR20090090712A (en) 2009-08-26

Family

ID=41208461

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080016121A KR20090090712A (en) 2008-02-22 2008-02-22 Merhod of manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20090090712A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478548B2 (en) 2014-08-04 2016-10-25 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9478548B2 (en) 2014-08-04 2016-10-25 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing semiconductor devices

Similar Documents

Publication Publication Date Title
KR100720232B1 (en) Method for forming semiconductor device having fin structure
KR100700332B1 (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
KR100744658B1 (en) Method for fabricating the same of semiconductor device with recess gate of flask shape
US7833861B2 (en) Semiconductor device having recess channel structure and method for manufacturing the same
KR100762912B1 (en) Semiconductor device having asymmetry bulb type recess gate and method of manufacturing the same
KR100744691B1 (en) Semiconductor device with bulb type recess gate and method for fabricating the same
KR101078726B1 (en) Semiconductor device and method of manufacturing the same
KR20060030717A (en) Manufacturing method for semiconductor device
KR20090090712A (en) Merhod of manufacturing semiconductor device
KR20070047042A (en) Method for fabrication the same of semiconductor device with recess gate of flask shape
KR100733228B1 (en) Semiconductor device and method for fabricating the same
KR100951568B1 (en) Transistor in semiconductor device and method for forming the same
KR100608375B1 (en) Method for forming gate in semiconductor device
KR20070003068A (en) Method of fabricating the semiconductor device having recessed channel
KR20080029660A (en) Semiconductor device and manufacturing of method the same
KR100672763B1 (en) Method of forming gate for semiconductor device
KR100880838B1 (en) Method for manufacturing semiconductor device with recess gate
KR100939429B1 (en) Semiconductor device and manufacturing method thereof
KR100675887B1 (en) Trench isolation in semiconductor device and method of fabricating the same
KR100771536B1 (en) Method of fabricating the semiconductor device having recessed channel
KR20090098290A (en) Saddle fin transistor and method for manufacturing the same
KR100784082B1 (en) Semiconductor memory device and method for manufacturing the same
KR20080061998A (en) Method for forming the semiconductor device
KR20100003174A (en) Method for manufacturing semiconductor device
KR20090067439A (en) Merhod of manufacturing semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination