KR20060079030A - Apparatus of liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device that can minimize the electromagnetic interference (EMI) problem that occurs during data transmission.

The liquid crystal display according to the present invention comprises a control signal generator for generating control signals, a data alignment unit for aligning and supplying pixel data, a pixel memory for storing pixel data of a previous frame, and pixel data of a current frame. And a data control unit including a data latch unit for comparing the pixel data of the previous frame and the pixel data of the current frame, and the data comparison unit compares the data of the previous frame with the data of the current frame. In this case, the data of the current frame is held and the data of the previous frame is applied to the data driver.

Description

Liquid Crystal Display {APPARATUS OF LIQUID CRYSTAL DISPLAY}

1 is a view showing a driving device of a conventional liquid crystal display.

FIG. 2 is a diagram illustrating in detail a data transmission bus between a timing controller and a data driver shown in FIG. 1.

3 is a view showing a liquid crystal display device according to the present invention.

4 is a diagram illustrating a timing controller according to the present invention.

5 is a timing diagram showing a comparison operation in the data comparison section.

<Brief description of the main parts of the drawing>

2, 32: timing controller 4, 34: data driver

6, 36: gate driver 8, 38: gamma circuit

10, 40: liquid crystal panel 12, 42: liquid crystal cell

14: data transmission bus

16: data control signal transmission bus

18: gate control signal transmission bus

22, 52: control signal generator

24, 53: data alignment unit

141: RO data transmission bus

142: GO data transfer bus

143: BO data transmission bus

144: RE data transmission bus

145: GE data transfer bus

146: BE data transmission bus

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of minimizing an electromagnetic interference (EMI) problem that occurs during data transmission.

In recent years, video data transmitted through a transmission medium has been increased in order to satisfy a user's desire for high quality images, and is being transmitted at a high speed so that the user can use it at an appropriate time. Accordingly, the transmission frequency of the video data is increased and the number of transmission lines for transmitting the video data is inevitably increased. In this case, as the video data having a high frequency is synchronously transmitted through the increased data transmission lines, electromagnetic interference (hereinafter, referred to as EMI) may appear severely.

Liquid crystal displays (hereinafter, referred to as LCDs) employ a method of reducing the number of transitions of data by a data modulation method or a transmission frequency by a 6 bus method in order to reduce EMI.

1 illustrates a conventional LCD driver.

1 shows a liquid crystal panel 10 in which liquid crystal cells 12 are arranged in a matrix, and a data driver 4 for driving data lines D1 to Dm of the liquid crystal panel 10. ), A gate driver 6 for driving the gate lines G0 to Gn of the liquid crystal panel 10, and a timing controller 2 for controlling the driving of the data driver 4 and the gate driver 6. And a gamma circuit 8 for supplying a gamma voltage to the data driver 4.

The liquid crystal panel 10 includes gate lines G0 to Gn, data lines D1 to Dm intersecting while insulated from the gate lines G0 to Gn, and gate lines G0 to Gn. Liquid crystal cells 12 are formed for each region provided at the intersection of the lines D1 to Dm. Each of the liquid crystal cells 12 has a common electrode and a pixel electrode facing each other with a liquid crystal interposed therebetween and is equivalently represented by a liquid crystal capacitor Clc. Each of the liquid crystal cells 12 further includes a storage capacitor Cst for stably maintaining the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged. Each of the liquid crystal cells 12 is driven by a thin film transistor (TFT) which is a switching element. The thin film transistor TFT receives the scan signal from any one of the gate lines G1 through Gn, that is, the pixel voltage signal from any one of the data lines D1 through Dm in response to the gate signal. To feed. Accordingly, the liquid crystal panel 10 displays an image by adjusting the light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal in units of the liquid crystal cell 12.

In response to the gate control signal from the timing controller 2, the gate driver 6 supplies the gate lines G1 to Gn of the liquid crystal panel 10 by the scan signal, that is, the gate high voltage, to drive the gate lines. . The gate driver 6 supplies the gate low voltage to the gate lines G1 through Gn when the gate high voltage is not supplied. In addition, the gate driver 6 supplies a gate low voltage to the dummy gate line GL0 for forming the storage capacitor Cst.

The data driver 4 applies the data lines D1 to each time a scan signal is supplied from the gate driver 6 to any one of the gate lines G1 to Gn in response to the data control signal from the timing controller 2. Dm) Supply a pixel voltage signal to each. In particular, the data driver 4 converts and supplies the digital pixel data input from the timing controller 2 into an analog pixel voltage signal. In this case, the data driver 4 converts the digital pixel data into an analog pixel voltage signal using the gamma voltages supplied for each gray from the gamma circuit 8.

The timing controller 2 generates gate control signals and data control signals for driving control of the data driver 4 and the gate driver 6, and supplies pixel data to the data driver 4. Specifically, the timing controller 2 generates gate control signals such as a gate start pulse GSC, a gate shift clock signal GSC, a gate output enable signal GOE, and the like through the gate control signal transmission bus 18. Supply to gate driver 6. In addition, the timing controller 2 generates data control signals such as a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL to generate a data control signal. It is supplied to the data driver 4 via the transmission bus 16. At the same time, the timing controller 2 aligns the input pixel data and supplies it to the data driver 4 via the data transmission bus 14.

To this end, the timing controller 2 includes a control signal generator 22 for generating control signals and a data alignment unit 24 for aligning and supplying pixel data as shown in FIG. 2.

Referring to FIG. 2, the control signal generator 22 uses the main clock signal MCLK and horizontal and vertical synchronization signals H and V input from the outside to control the gate control signals GSC, GSP, and GOE. ) And data control signals (SSC, SSP, SOE, POL, etc.). The data control signals SSC, SSP, SOE, and POL generated in this way are supplied to the data driver 4 through respective transmission lines included in the data control signal bus 16.

The data alignment unit 24 aligns the pixel data R, G, and B input from the outside to the data driver 4 in a manner suitable for the bus transfer method. The data sorter 24 employs a six-bus data bus 14 to reduce the data transmission frequency to reduce EMI. Accordingly, the data alignment unit 24 separates the pixel data R, G, and B into odd pixel data RO, GO, and BO and even pixel data RE, GE, and BE. The sorted odd pixel data (RO, GO, BO) and even pixel data (RE, GE, BE) as shown in FIG. 2 through the first to sixth data buses 141 to 146, respectively, as shown in FIG. 2. It is supplied to the data driver 4 in synchronization with the signal SSC. Here, when each of the odd pixel data RO, GO, BO, and even pixel data RE, GE, BE has a size of 6-bit data, each of the first to sixth data transfer buses 141 to 146 is provided in six pieces. It consists of a data transmission line. As a result, the data transmission bus 14 includes a total of 36 data transmission lines.

Thus, the driving device of the conventional LCD is to reduce the EMI by reducing the transmission frequency as the pixel data is transmitted in a 6-bus method. However, although the data transmission frequency is reduced compared to the conventional three-bus method, EMI is reduced, but there is still a problem of EMI generation due to data transition during data transmission.

Accordingly, an object of the present invention is to provide a liquid crystal display device which can effectively reduce EMI.

In order to achieve the above object, the liquid crystal display according to the present invention includes a control signal generator for generating control signals, a data alignment unit for aligning and supplying pixel data, a pixel memory for storing pixel data of a previous frame, And a data control unit for holding pixel data of the current frame, and a data control unit for comparing the pixel data of the previous frame with the pixel data of the current frame, and comparing the data of the previous frame with the data comparison unit. If the data of the current frame is the same, the data of the current frame is held and the data of the previous frame is applied to the data driver.

The data comparison unit compares the R, G, and B pixel data of the previous frame with each of the R, G, and B pixel data of the current frame, and holds the data of the current frame applied to the data latch unit when all the pixel data are the same. Let's do it.

The data comparison unit compares two input values by using one pixel data of the R, G, and B pixel data of the previous frame and the corresponding R, G, and B pixel data of the current frame as input values. If the same, a plurality of first comparison unit for generating a first comparison signal, and if the first comparison signal is all the same, a second for generating a second comparison signal to generate a non-inverted signal for holding the data of the current frame A comparison unit is provided.

The first comparator includes an EX-NOR gate having R, G, B odd pixel data of the previous frame, even pixel data, and pixel data pairs of respective current frames corresponding thereto as input values.

The second comparator includes one AND gate having all of the first comparison signals as input values.

The data alignment unit divides the 6-bit R, G, and B data into 12-bit R, G, and B pixel data and even pixel data.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 5.

Referring to FIG. 3, the liquid crystal display according to the present invention is configured to drive the liquid crystal panel 40 in which the liquid crystal cells 42 are arranged in a matrix and to drive the data lines D1 to Dm of the liquid crystal panel 40. Timing for controlling the data driver 34, the gate driver 36 for driving the gate lines G0 to Gn of the liquid crystal panel 40, and the driving of the data driver 34 and the gate driver 36. A gamma circuit 38 for supplying a gamma voltage to the control unit 32 and the data driver 34 is provided. In particular, the timing controller 32 includes a control signal generator 52, a data alignment unit 53 for aligning and supplying pixel data, a pixel memory 54 for storing data of a previous frame, and data of a previous frame. And a data comparator 60 for comparing the data of the current frame and a data latch 56 for holding data transfer while comparing the data of the previous frame and the data of the current frame.

The liquid crystal panel 40 includes gate lines G0 to Gn, data lines D1 to Dm intersecting while insulated from the gate lines G0 to Gn, and gate lines G0 to Gn. Liquid crystal cells 42 are formed for each region provided at the intersection of the lines D1 to Dm. Each of the liquid crystal cells 42 has a common electrode and a pixel electrode facing each other with a liquid crystal interposed therebetween and is equivalently represented by a liquid crystal capacitor Clc. Each of the liquid crystal cells 42 further includes a storage capacitor Cst for stably maintaining the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged. Each of the liquid crystal cells 42 is driven by a thin film transistor (TFT) which is a switching element. The thin film transistor TFT receives a scan signal from one of the gate lines G1 through Gn, that is, a pixel voltage signal from one of the data lines D1 through Dm in response to the gate signal. Supplies). Accordingly, the liquid crystal panel 40 displays an image by adjusting the light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal in units of the liquid crystal cell 42.

In response to the gate control signals from the timing controller 32, the gate driver 36 supplies the gate lines G1 to Gn of the liquid crystal panel 40 by driving a scan signal, that is, a gate high voltage, in line units. do. The gate driver 36 supplies a gate low voltage in a period when the gate high voltage is not supplied to the gate lines G1 to Gn. In addition, the gate driver 36 supplies a gate low voltage to the dummy gate line GL0 for forming the storage capacitor Cst.

The data driver 34 applies the data lines D1 to each time a scan signal is supplied from the gate driver 36 to any one of the gate lines G1 to Gn in response to the data control signal from the timing controller 32. Dm) Supply a pixel voltage signal to each. In particular, the data driver 34 converts the digital pixel data input from the timing controller 32 into an analog pixel voltage signal and supplies the same. In this case, the data driver 34 converts the digital pixel data into an analog pixel voltage signal using gamma voltages supplied for each gray from the gamma circuit 38.

The timing controller 32 generates gate control signals and data control signals necessary for driving control of the data driver 34 and the gate driver 36, and supplies pixel data to the data driver 34. Specifically, the timing controller 32 generates gate control signals such as a gate start pulse GSC, a gate shift clock signal GSC, a gate output enable signal GOE, and the like to generate a gate driver (eg, a gate driver) through a gate control signal transmission bus. 36). In addition, the timing controller 32 generates data control signals such as a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and transmits the data control signal. Supply to data driver 34 via a bus. At the same time, the timing controller 32 aligns the input pixel data and supplies it to the data driver 34 through the data transfer bus.

To this end, the timing controller 32 includes a control signal generator 52 for generating control signals, a data alignment unit 53 for aligning and supplying pixel data, and a previous frame (N−) as shown in FIG. 1) a pixel memory 54 for storing the pixel data of the first pixel, a data latch unit 56 for holding the N-th pixel data of the current frame, and a data comparator for comparing the pixel data of the previous frame with the pixel data of the current frame. 60 is provided.

The control signal generator 52 uses the main clock signal MCLK inputted from the outside and the horizontal and vertical synchronization signals H and V to control the gate control signals GSC, GSP, GOE, and the like. (SSC, SSP, SOE, POL, etc.) The data control signals (SSC, SSP, SOE, POL, etc.) generated in this way are supplied to the data driver 34 through respective transmission lines included in the data control signal bus.

The data alignment unit 53 aligns the pixel data R, G, and B inputted from the outside to the data driver 34 in a manner suitable for a bus transfer method. The data aligning unit 53 is adopted by a six-bus data bus to reduce the data transmission frequency to reduce EMI. Accordingly, the data alignment unit 53 separates the pixel data R, G, and B into odd pixel data RO, GO, and BO and even pixel data RE, GE, and BE. The aligned pixel data RO, GO, and BO and even pixel data RE, GE, and BE are synchronized with the source shift clock signal SSC through each of the first to sixth data buses 141 to 146. It is supplied to the data driver 34. Here, when each of the odd pixel data RO, GO, BO, and even pixel data RE, GE, BE has a size of 6-bit data, each of the first to sixth data transfer buses 141 to 146 is divided into six pieces. It consists of a data transmission line. As a result, the data transmission bus includes a total of 36 data transmission lines.

The pixel memory 54 stores R, G, and B data of the previous frame via the timing controller 32.

The data latch unit 56 holds the R, G, and B data of the current frame without directly supplying the data driver 34 directly.

The R, G, B data of the previous frame is compared with the R, G, B data of the current frame, and the R, G, B data of the current frame is compared with the R, G, B data of the previous frame. If, R, G, B data of the previous frame is transmitted to the data driver 34.

The following is a diagram illustrating a circuit for comparing data of a previous frame and a current frame according to an embodiment of the present invention.

Referring to FIG. 4, an operation process of a timing controller for displaying an image of an nth frame is as follows.

First, the (n-1) -th data, which is the previous frame, is passed through the data alignment unit 53, divided into 12-bit pixel data of odd pixel data and even pixel data, and divided into 12-bit pixel data in the pixel memory. Stored.

The 6-bit R, G, and B data of the n-th frame pass through the data alignment unit 53 and are divided into 12-bit pixel data of odd pixel data and even pixel data.

The 12-bit pixel data of the nth frame is transmitted to the data latching unit and the data comparing unit.

The data latch unit 56 latches the 12-bit R, G, and B data passed through the data alignment unit 53.

The data comparator 60 includes first and second comparators, and compares pixel data of the (n−1) -th frame stored in the pixel memory with n-th pixel data branched from the data alignment unit 53.

This will be described in detail as follows.

The pixel data of the (n-1) th frame of the pixel memory and the nth pixel data branched from the data alignment unit 53 are input to the first comparator.

The first comparator includes six EX-NOR gates (three EX-NOR gates are shown in the drawing for the sake of simplicity), and each EX-NOR gate is an odd pixel data and even each of R, G, and B. Compare the pixel data. The EX-NOR gate produces a high signal output if the inputs are the same. That is, when the R, G, B odd pixel data and the even pixel data of the (n-1) th frame and the nth frame are the same, an output value of a high signal is generated.

The output values of all the EX-NOR gates are input as input values of the second comparator. The second comparator includes an AND gate to generate a high pulse when all input values of the first comparator are high pulses. That is, if the R, G, B odd pixel data and even pixel data of the (n-1) th frame and the n th frame compared in the first comparator are equal to each other, the second comparator generates a high pulse output value.

The output value of the high signal of the second comparator holds the pixel data of the n-th frame applied to the data latch as a non-inverted signal. Therefore, the liquid crystal display displays the pixel data of the (n-1) th frame as it is.

5 is a timing diagram illustrating an operation of comparing a pixel data applied to a previous frame and a current frame by the data comparator.

For simplicity, only the comparison between the odd pixel data and the even pixel data of R applied to the previous frame and the current frame is shown.

The first comparator compares the two signals using the odd pixel data of R of the previous frame and the current frame as input signals.

The second comparator compares the two signals using the even pixel data of R of the previous frame and the current frame as an input signal.

The output value of the first comparator becomes a high pulse when the input values of the first comparators are the same as the first, second, fifth, and six pixels.

The output value of the second comparator becomes a high pulse when the input values of each second comparator are the same as the second pixel.

Output signals of the first and second comparators are applied to the second comparator, and the second comparator generates a high signal when the input signals are all high signals like the second pixel. Actually, the third to sixth comparators (not shown) included in the first comparator generate an output signal by the same operation as the first and second comparators, and the second comparator inputs the output signals of the first to sixth comparators. The output value is generated as a signal.

When the output signal of the second comparator is a high signal, this signal is applied to the data latch portion as a non-inverted signal. When a non-inverting signal is applied to the data latch unit, the data latch unit holds the pixel data of the current frame. Therefore, the pixel data of the previous frame is applied to the data driver.

As such, when the data controller compares the data of the previous frame with the data of the current frame and transmits the data of the previous frame to the data driver when the pixel data of the consecutive frames are all the same, the data transition can be reduced. Accordingly, the occurrence of EMI due to the data transition is reduced.

As described above, the liquid crystal display according to the present invention can reduce the number of data transitions to reduce the occurrence of EMI.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A control signal generator for generating control signals; A data alignment unit for aligning and supplying pixel data; A pixel memory for storing pixel data of a previous frame; A data latch unit for holding pixel data of the current frame; A timing controller including a data comparison unit for comparing pixel data of a previous frame and pixel data of a current frame, And comparing the data of the previous frame with the data of the current frame by holding the data of the current frame and applying the data of the previous frame to a data driver. The method of claim 1, The data comparison unit compares the R, G, and B pixel data of the previous frame with each of the R, G, and B pixel data of the current frame, and holds the data of the current frame applied to the data latch unit when all the pixel data are the same. And a liquid crystal display device. The method of claim 1, The data comparison unit When two input values are equal by comparing two input values by using one pixel data among the R, G, and B pixel data of the previous frame and the corresponding R, G, B pixel data of the current frame as input values. A plurality of first comparison units generating a first comparison signal; And a second comparator for generating a second comparison signal when all of the first comparison signals are the same. The method of claim 3, wherein The first comparator includes a plurality of EX-NOR gates having R, G, B odd pixel data of the previous frame, even pixel data, and pixel data pairs of respective current frames corresponding thereto as input values. Liquid crystal display device. The method of claim 4, wherein And the second comparator includes one AND gate that takes all of the first comparison signals as an input value. The method of claim 1, And the data alignment unit divides the 6-bit R, G, and B data into 12-bit R, G, and B pixel data and even pixel data.

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