KR20060072519A - Method of forming a contact hole in a semiconductor device - Google Patents

Method of forming a contact hole in a semiconductor device Download PDF

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KR20060072519A
KR20060072519A KR1020040111181A KR20040111181A KR20060072519A KR 20060072519 A KR20060072519 A KR 20060072519A KR 1020040111181 A KR1020040111181 A KR 1020040111181A KR 20040111181 A KR20040111181 A KR 20040111181A KR 20060072519 A KR20060072519 A KR 20060072519A
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contact hole
forming
width
insulating film
interlayer insulating
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KR1020040111181A
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Korean (ko)
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안명규
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 콘택홀을 형성하는 과정에서 콘택홀의 하부 폭을 넓히기 위하여 식각 공정을 과도하게 실시함에 따라 층간 절연막의 상부 폭이 좁아지거나 낮아지는 것을 보상하기 위하여, 콘택홀을 형성한 후 폭이 좁아진 층간 절연막의 상부에 스텝 커버리지(step coverage) 특성이 열악한 물질을 추가로 증착하여 감소된 폭을 보상함으로써, 콘택홀의 하부 폭을 증가시킴과 동시에 상부 폭과 하부 폭이 동일한 콘택홀을 형성할 수 있다.
The present invention relates to a method of forming a contact hole in a semiconductor device, and to compensate for the narrowing or lowering of an upper width of an interlayer insulating layer by excessively performing an etching process in order to increase a lower width of a contact hole in forming a contact hole. After forming the contact hole, the lower width of the contact hole is increased by compensating for the reduced width by further depositing a material having poor step coverage characteristics on the upper part of the interlayer insulating film that has been narrowed, thereby increasing the upper width and the lower width of the contact hole. Contact holes having the same width may be formed.

콘택홀, 스텝커버리지, PE-Nitride, PE-OxynitrideContact Holes, Step Coverage, PE-Nitride, PE-Oxynitride

Description

반도체 소자의 콘택홀 형성 방법{Method of forming a contact hole in a semiconductor device} Method of forming a contact hole in a semiconductor device             

도 1은 콘택 플러그 형성 시 발생되는 문제점을 보여주는 단면도이다.1 is a cross-sectional view illustrating a problem occurring when a contact plug is formed.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도들이다.
2A through 2D are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101, 201 : 반도체 기판 202 : 질화막101, 201: semiconductor substrate 202: nitride film

102, 203 : 층간 절연막 103, 204 : 콘택홀102, 203: interlayer insulating film 103, 204: contact hole

205 : 절연막 104, 206 : 콘택 플러그205: insulating film 104, 206: contact plug

105 : 심 106 : 콘택 플러그 연결 영역
105: shim 106: contact plug connection area

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 하부 폭을 넓혀 콘택 저항을 감소키기 위한 반도체 소자의 콘택홀 형성 방법에 관한 것이다.
The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device for reducing a contact resistance by widening a lower width thereof.

디자인 룰이 70nm보다 작은 반도체 소자에서 콘택 플러그를 형성하는 경우, 콘택 저항을 낮추기 위하여 콘택홀 하부의 폭을 넓혀야 한다. 콘택홀 하부의 폭을 넓히기 위하여 콘택홀 형성하는 식각 공정을 과도하게 진행하는데, 콘택홀 상부의 폭도 상당하게 증가한다. 즉, 콘택홀 사이의 층간 절연막 폭이 감소하게 된다. 이후, 세정 공정에서는 콘택홀의 상부 폭이 더욱 더 증가하면서 층간 절연막의 폭은 감소하게 된다. If the design rule forms a contact plug in a semiconductor device smaller than 70 nm, the width of the lower portion of the contact hole should be widened to lower the contact resistance. In order to increase the width of the lower portion of the contact hole, the etching process of forming the contact hole is excessively performed, and the width of the upper portion of the contact hole also increases considerably. That is, the width of the interlayer insulating film between the contact holes is reduced. Subsequently, in the cleaning process, the width of the interlayer insulating layer decreases while the upper width of the contact hole increases further.

도 1은 콘택 플러그 형성 시 발생되는 문제점을 보여주는 단면도이다.1 is a cross-sectional view illustrating a problem occurring when a contact plug is formed.

도 1을 참조하면, 콘택홀 하부의 폭을 조금이라도 더 넓히기 위하여 반도체 기판(101) 상부의 층간 절연막(102)에 콘택홀(103)을 형성하기 위한 식각 공정을 과도하게 실시한 후 세정공정을 실시하면, 콘택홀(103)의 상부 폭이 증가하게 된다. 그리고, 후속 공정으로 세정 공정을 실시하게 되면, 콘택홀(103) 상부의 폭은 보다 증가한다. 심한 경우에는, 층간 절연막(102) 상부가 식각되어 일부 영역에서 층간 절연막(102)의 높이가 낮아지게 된다. Referring to FIG. 1, an excessively etched process for forming the contact hole 103 in the interlayer insulating film 102 on the semiconductor substrate 101 is performed after the etching process in order to further widen the width of the lower contact hole. In this case, the upper width of the contact hole 103 is increased. When the cleaning process is performed in a subsequent process, the width of the upper portion of the contact hole 103 increases. In severe cases, the upper portion of the interlayer insulating layer 102 is etched to lower the height of the interlayer insulating layer 102 in some regions.

이 상태에서, 콘택홀(103)에 콘택 플러그(104)를 형성하면, 일부 영역에서는 심(seam; 105)이 발생되기도 하며, 층간 절연막(102) 상부가 식각된 영역에서는 서로 인접한 콘택 플러그(104)의 상부가 연결(106)되어 불량이 발생될 수 있다.
In this state, when the contact plug 104 is formed in the contact hole 103, a seam 105 may be generated in some regions, and contact plugs 104 adjacent to each other in the region where the upper portion of the interlayer insulating layer 102 is etched. The top of the) is connected 106 may cause a defect.

이에 대하여, 본 발명이 제시하는 반도체 소자의 콘택홀 형성 방법은 콘택홀을 형성하는 과정에서 콘택홀의 하부 폭을 넓히기 위하여 식각 공정을 과도하게 실시함에 따라 층간 절연막의 상부 폭이 좁아지거나 낮아지는 것을 보상하기 위하여, 콘택홀을 형성한 후 폭이 좁아진 층간 절연막의 상부에 스텝 커버리지(step coverage) 특성이 열악한 물질을 추가로 증착하여 감소된 폭을 보상함으로써, 콘택홀의 하부 폭을 증가시킴과 동시에 상부 폭과 하부 폭이 동일한 콘택홀을 형성할 수 있다.
In contrast, the method for forming a contact hole of a semiconductor device according to the present invention compensates that the upper width of the interlayer insulating layer is narrowed or lowered by excessively performing an etching process to increase the lower width of the contact hole in the process of forming the contact hole. In order to compensate for the reduced width by further depositing a material having poor step coverage characteristics on top of the interlayer insulating film that has been narrowed after forming the contact hole, the lower width of the contact hole is increased and the upper width thereof is increased. A contact hole having the same width as the bottom may be formed.

본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법은 반도체 기판 상에 층간 절연막을 형성하는 단계와, 층간 절연막에 콘택홀을 형성하는 단계, 및 층간 절연막의 상부에 절연막을 형성하여, 콘택홀의 경사진 식각면에 의해 좁아진 층간 절연막의 상부 폭을 보상하는 단계를 포함한다. A method of forming a contact hole in a semiconductor device according to an embodiment of the present invention includes forming an interlayer insulating film on a semiconductor substrate, forming a contact hole in the interlayer insulating film, and forming an insulating film on the interlayer insulating film, thereby forming a contact hole. Compensating for the upper width of the interlayer insulating film narrowed by the inclined etching surface.

상기에서, 층간 절연막 하부에는 볼더리스 콘택이나 자기정렬 콘택 공정을 위한 질화막이 더 형성될 수 있다. In the above, a nitride film for a boulderless contact or a self-aligned contact process may be further formed below the interlayer insulating film.

절연막은 스텝 커버리지 특성을 낮추어 층간 절연막 상부에만 형성되도록 PECVD 공정으로 형성하며, 절연막은 산화막, 질화막 및 산화 질화막 중 어느 하나로 형성할 수 있다. PECVD 공정 시 스텝 커버지리를 5% 내지 50%로 조절하며, 절연막으로 콘택홀의 상부 폭을 5% 내지 70% 정도 감소시킨다. The insulating film is formed by a PECVD process so that the step coverage characteristics are lowered and formed only on the interlayer insulating film, and the insulating film may be formed of any one of an oxide film, a nitride film, and an oxynitride film. Step cover geography is adjusted to 5% to 50% during the PECVD process, and the top width of the contact hole is reduced by 5% to 70% with an insulating film.

절연막을 형성한 후, 콘택홀 저면에 형성된 절연막을 제거하는 단계를 더 포 함할 수 있다.
After forming the insulating film, the method may further include removing the insulating film formed on the bottom of the contact hole.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. 또한 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면 상에서 동일 부호는 동일한 요소를 지칭한다.On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위한 소자의 단면도들이다.2A through 2D are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 트랜지스터나 플래시 메모리 셀과 같이 반도체 소자를 형성하기 위한 여러 요소(도시되지 않음)가 형성된 반도체 기판(201) 상에 층간 절연막(203)을 형성한다. 이때, 층간 절연막(203)을 형성하기 전에, 볼더리스 콘택이나 SAC(Self align contact) 공정을 위하여 질화막(202)을 형성할 수도 있다. Referring to FIG. 2A, an interlayer insulating film 203 is formed on a semiconductor substrate 201 in which various elements (not shown) for forming a semiconductor device, such as a transistor or a flash memory cell, are formed. In this case, before the interlayer insulating layer 203 is formed, the nitride layer 202 may be formed for a boulderless contact or a self alignment contact (SAC) process.

도 2a를 참조하면, 콘택홀 마스크를 이용한 식각 공정으로 층간 절연막(203) 및 질화막(202)을 순차적으로 식각하여 콘택홀(204)을 형성한다. 콘택홀(204)을 통해 반도체 기판(201)에 형성된 소오스/드레인과 같은 접합 영역(도시되지 않음)이 노출된다.Referring to FIG. 2A, a contact hole 204 is formed by sequentially etching the interlayer insulating layer 203 and the nitride layer 202 by an etching process using a contact hole mask. A junction region (not shown), such as a source / drain, formed in the semiconductor substrate 201 is exposed through the contact hole 204.

한편, 집적도가 높아짐에 따라 콘택홀(204)의 폭이 감소하면서 종횡비가 증가하여 콘택홀(204)의 측벽이 경사지게 된다. 따라서, 콘택홀(204)의 상부 폭보다 하부 폭이 좁아진다. 이 경우, 콘택 저항이 높아지기 때문에, 식각 공정을 과도하게 식각하여 콘택홀(204) 하부의 폭을 증가시킨다. 콘택홀(204)의 하부 폭이 증가하는 만큼 상부 폭도 증가하며, 이로 인해, 층간 절연막(203)이 상부 폭이 감소하게 된다.On the other hand, as the degree of integration increases, the width of the contact hole 204 decreases and the aspect ratio increases, so that the sidewall of the contact hole 204 is inclined. Therefore, the lower width is narrower than the upper width of the contact hole 204. In this case, since the contact resistance increases, the etching process is excessively etched to increase the width of the lower portion of the contact hole 204. As the bottom width of the contact hole 204 increases, the top width also increases. As a result, the top width of the interlayer insulating layer 203 decreases.

도 2c를 참조하면, 좁아진 층간 절연막(203)의 상부 폭을 보상하기 위하여 절연물질을 추가로 증착하여 층간 절연막(203) 상부에 절연막(205)을 형성한다. 이때, 절연 물질이 층간 절연막(203)의 상부에만 주로 증착되도록 PECVD(Plasma Enhanced Chemical Vapor Deposition)법으로 절연 물질을 증착하여 절연막(205)을 형성하며, 질화물, 산화물 또는 산화질화물을 증착할 수 있다. 이때, PECVD 공정 시 스텝 커버리지를 2% 내지 50% 정도로 조절한다. 스텝 커버리지는 공정 조건을 조절하면 제어가 가능하며, 이는 당업자에게는 널리 알려진 기술이므로 자세한 설명은 생략하기로 한다. Referring to FIG. 2C, in order to compensate for the upper width of the narrowed interlayer insulating layer 203, an insulating material is further deposited to form an insulating layer 205 on the interlayer insulating layer 203. In this case, the insulating material may be deposited by using a plasma enhanced chemical vapor deposition (PECVD) method so that the insulating material is mainly deposited only on the interlayer insulating film 203, thereby forming the insulating film 205 and depositing nitride, oxide, or oxynitride. . At this time, the step coverage during the PECVD process is adjusted to about 2% to 50%. Step coverage can be controlled by adjusting the process conditions, which are well known to those skilled in the art, so a detailed description thereof will be omitted.

절연막(205)은 낮은 스텝 커버리지 특성으로 인하여 층간 절연막(203)의 상부에 가장 두껍게 형성되며, 하부로 갈수록 얇게 형성된다. 따라서, 콘택홀(204) 하부의 폭이 감소되는 것을 방지하면서, 좁아진 층간 절연막(203)의 상부 폭을 보 상할 수 있다. 절연막(205)을 형성하여 콘택홀(204)의 상부 폭을 5% 내지 70% 정도 감소시킨다. 이를 통해, 콘택홀(204)의 상부와 하부 폭이 거의 동일해진다. The insulating film 205 is formed thickest on the upper portion of the interlayer insulating film 203 due to the low step coverage characteristic, and becomes thinner toward the bottom. Accordingly, the upper width of the narrowed interlayer insulating layer 203 can be compensated for while preventing the width of the lower portion of the contact hole 204 from being reduced. The insulating film 205 is formed to reduce the upper width of the contact hole 204 by about 5% to about 70%. As a result, the upper and lower widths of the contact holes 204 become substantially the same.

한편, 절연막(205)을 형성하는 과정에서 콘택홀(204) 저면에도 절연물질이 증착되므로, 콘택홀(204) 저면에 증착된 절연물질을 제거하기 위하여 식각 공정을 실시한다. 이때, 식각 공정을 과도하게 실시하면 층간 절연막(203) 상부에 형성된 절연막(205)이 식각되므로, 콘택홀(204) 저면에 증착된 절연물질이 제거될 정도로만 식각 공정을 실시하는 것이 바람직하다.Meanwhile, since an insulating material is deposited on the bottom of the contact hole 204 in the process of forming the insulating film 205, an etching process is performed to remove the insulating material deposited on the bottom of the contact hole 204. In this case, if the etching process is excessively performed, the insulating film 205 formed on the interlayer insulating film 203 is etched. Therefore, the etching process may be performed only to remove the insulating material deposited on the bottom of the contact hole 204.

도 2b에서 콘택홀(204) 형성 시 질화막(202)을 식각하지 않고 절연막(205)을 형성한 후 질화막(202)을 식각한다면, 콘택홀(204) 저면에 증착된 절연 물질도 함께 제거할 수 있다. 이 경우, 공정 단계를 감소시킬 수 있다. In FIG. 2B, when the insulating film 205 is formed without etching the nitride film 202 when the contact hole 204 is formed, the nitride film 202 is etched, and the insulating material deposited on the bottom of the contact hole 204 may also be removed. have. In this case, process steps can be reduced.

도 2d를 참조하면, 콘택홀(204) 내부에 콘택 플러그(206)를 형성한다. 이때, 절연막(205)에 의해 서로 인접한 콘택 플러그(204)의 상부가 서로 연결되는 것을 방지할 수 있다. Referring to FIG. 2D, a contact plug 206 is formed in the contact hole 204. In this case, it is possible to prevent the upper portions of the contact plugs 204 adjacent to each other from being connected to each other by the insulating layer 205.

상술한 바와 같이, 본 발명은 콘택홀을 형성하는 과정에서 콘택홀의 하부 폭을 넓히기 위하여 식각 공정을 과도하게 실시함에 따라 층간 절연막의 상부 폭이 좁아지거나 낮아지는 것을 보상하기 위하여, 콘택홀을 형성한 후 폭이 좁아진 층간 절연막의 상부에 스텝 커버리지(step coverage) 특성이 열악한 물질을 추가로 증착하여 감소된 폭을 보상함으로써, 콘택홀의 하부 폭을 증가시킴과 동시에 상부 폭과 하부 폭이 동일한 콘택홀을 형성할 수 있다.As described above, the present invention provides a contact hole for compensating that the upper width of the interlayer insulating layer is narrowed or lowered by excessively performing an etching process to widen the lower width of the contact hole in the process of forming the contact hole. Afterwards, by further depositing a material having poor step coverage characteristics on top of the narrower interlayer insulating layer to compensate for the reduced width, the lower width of the contact hole is increased, and at the same time, a contact hole having the same upper width and lower width is formed. Can be formed.

Claims (7)

반도체 기판 상에 층간 절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간 절연막에 콘택홀을 형성하는 단계; 및Forming a contact hole in the interlayer insulating film; And 상기 층간 절연막의 상부에 절연막을 형성하여, 상기 콘택홀의 경사진 식각면에 의해 좁아진 상기 층간 절연막의 상부 폭을 보상하는 단계를 포함하는 반도체 소자의 콘택홀 형성 방법.Forming an insulating film on the interlayer insulating film, and compensating for the upper width of the interlayer insulating film narrowed by the inclined etching surface of the contact hole. 제 1 항에 있어서, The method of claim 1, 상기 층간 절연막 하부에는 볼더리스 콘택이나 자기정렬 콘택 공정을 위한 질화막이 더 형성되는 반도체 소자의 콘택홀 형성 방법.And a nitride film is further formed below the interlayer insulating film for a boulderless contact or a self-aligned contact process. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 스텝 커버리지 특성을 낮추어 상기 층간 절연막 상부에만 형성되도록 PECVD 공정으로 형성되는 반도체 소자의 콘택홀 형성 방법.And the insulating layer is formed by a PECVD process to lower the step coverage characteristics so as to be formed only on the interlayer insulating layer. 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 절연막은 산화막, 질화막 및 산화 질화막 중 어느 하나로 형성되는 반도체 소자의 콘택홀 형성 방법.And the insulating film is formed of any one of an oxide film, a nitride film, and an oxynitride film. 제 3 항에 있어서,The method of claim 3, wherein 상기 PECVD 공정 시 상기 스텝 커버지리를 5% 내지 50%로 조절하는 반도체 소자의 콘택홀 형성 방법.The method for forming a contact hole in a semiconductor device to adjust the step cover geography to 5% to 50% during the PECVD process. 제 1 항에 있어서, The method of claim 1, 상기 절연막에 의해 상기 콘택홀의 상부 폭이 5% 내지 70% 정도 감소하는 반도체 소자의 콘택홀 형성 방법.And forming an upper width of the contact hole by about 5% to about 70% by the insulating layer. 제 1 항에 있어서, 상기 절연막을 형성한 후, The method of claim 1, wherein after forming the insulating film, 상기 콘택홀 저면에 형성된 상기 절연막을 제거하는 단계를 더 포함하는 반도체 소자의 콘택홀 형성 방법.And removing the insulating layer formed on the bottom surface of the contact hole.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8203135B2 (en) 2009-02-06 2012-06-19 Samsung Electronics Co., Ltd. Semiconductor device including uniform contact plugs and a method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8203135B2 (en) 2009-02-06 2012-06-19 Samsung Electronics Co., Ltd. Semiconductor device including uniform contact plugs and a method of manufacturing the same

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