KR100806606B1 - Method for fabricating the same of semiconductor device in contact hole - Google Patents

Abstract

The present invention provides a method for manufacturing a contact hole of a semiconductor device which prevents a loss of a gate hard mask and at the same time prevents contact open problems. The present invention provides an electrode, a nitride film-based first hard mask and carbon on a semiconductor substrate. Forming a pattern in which the second hard masks are sequentially stacked; forming an insulating layer on the entire surface including the pattern; and forming a nitride layer mask pattern on the insulating layer to open a contact hole region. And etching the insulating layer with a self-aligned contact etch using the nitride mask pattern as an etch mask to form a contact hole self-aligned to the pattern. Gate hard remaining after contact hole formation by additional formation of silicon carbide-based hard mask containing carbon with selectivity As well as securing the thickness of the mask and improving the profile, it solves the problem of opening of the contact hole, thereby increasing the margin of the subsequent process and improving the reliability of the device.

 Self-aligned contacts, etch selectivity, planarization, gate pattern, silicon carbide

Description

METHOOD FOR FABRICATING THE SAME OF SEMICONDUCTOR DEVICE IN CONTACT HOLE

1A to 1C are cross-sectional views illustrating a method for manufacturing a contact hole in a semiconductor device according to the prior art;

Figure 2a to 2c is a TEM picture of Figures 1a to 1c,

3A to 3E are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to a preferred embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 gate insulating film

33: gate electrode 34: first hard mask

35: second hard mask 36: spacer

37: insulating layer 38: mask pattern

39: contact hole 40A: landing plug contact

In order to solve the overlay problem and the patterning limit of the mask process during the semiconductor device process, the upper part of the gate is protected by the nitride film using the selectivity of nitride and oxide and the oxide is etched. The Self Aligned Contact (SAC) process of opening a contact is performed.

')형 프로파일을 갖게 된다. Due to the nature of the self-aligned contact recipe, when sufficient polymer is formed in the upper nitride film of the line pattern, the nitride film profile becomes smaller and the open pattern is preferred. Characteristic irregularities when etching alignment contacts ('

You have a ')' profile.

1A to 1C and 2A to 2C are cross-sectional views and TEM photographs for explaining a method of manufacturing a semiconductor device according to the prior art.

As shown in FIGS. 1A and 2A, a gate interlayer insulating film 12 is formed on a semiconductor substrate 11, and a plurality of gate patterns 13 are formed. Here, the gate pattern 13 has a structure in which the gate electrode and the gate hard mask are sequentially stacked.

Subsequently, a spacer 14 is formed on the entire surface including the gate pattern 13, and the interlayer insulating film 15 is formed until the gate patterns 13 are filled. Subsequently, a mask pattern 16 having a predetermined region for self-aligned contact is formed on the interlayer insulating film 15.

1B and 1C, the self-aligned contact hole 17 is formed by etching the interlayer insulating layer 15 between the gate pattern 13 using the mask pattern 16 as an etch mask.

Referring to FIGS. 2B and 2C, it can be seen that a semiconductor device is formed after the process of FIGS. 1B and 1C.

As described above, the prior art is formed by rounding the upper part of the pattern so that the amount of polymer deposited on the shoulder profile is relatively small and structurally weak due to the physical bonding between the spacer nitride and the gate hard mask. Therefore, a problem P occurs in that the gate hard mask is damaged due to insufficient polymer in the shoulder portion of the gate pattern 13.

')자형 프로파일을 개선하기 위해 다량의 폴리머를 발생시키는 선택비가 높은 조건으로 식각을 진행할 경우, 높은 폴리머를 형성시키는 공정(High Polymer Process)은 콘택 오픈(Contact Open)능력이 현저히 떨어지기 때문에 실시하기 어려운 문제점이 있다.Unevenness formed during the self-aligned contact etching ('

If the etching process is performed under the condition of high selectivity that generates a large amount of polymer to improve the shape profile, the high polymer process is performed because the contact open ability is significantly reduced. There is a difficult problem.

In addition, as the degree of integration of devices increases, the line width of the conductor continues to decrease, and the amount of hard mask loss and spacer loss that occurs during etching of the self-aligned contact due to the decrease in the line width and propylene tends to increase. This shape also needs to use the recipe of the conditions to form a large amount of polymer for high selectivity for hard mask protection, but there is a problem that is difficult to improve because it is accompanied by a decrease in the open capacity.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a method for manufacturing a contact hole of a semiconductor device which prevents a loss of a gate hard mask and at the same time prevents a contact open problem.

The method of manufacturing a contact hole of a semiconductor device according to the present invention includes forming a pattern in which an electrode, a nitride-based first hard mask and a carbon-containing second hard mask are sequentially stacked on a semiconductor substrate, and the front surface including the pattern. Forming an insulating layer on the insulating layer, forming a nitride mask pattern for opening a contact hole expected region on the insulating layer, etching the insulating layer with a self-aligned contact etch using the nitride mask pattern as an etch mask, Forming a contact hole that is self-aligned.

In particular, the second hard mask is formed of a silicon carbide-based insulating material containing carbon, but is formed of any one selected from the group of SiC, SiCN, and SiCO.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

As shown in FIG. 3A, a gate insulating film 32 is formed on the semiconductor substrate 31. The semiconductor substrate 31 may include an isolation layer and a well, and the gate insulating layer 32 may be formed of a thermal oxide layer.

Subsequently, a gate pattern G of a line pattern in which the gate electrode 33, the first hard mask 34, and the second hard mask 35 are stacked is formed on the gate insulating layer 32. Here, the gate electrode 33 may be formed of a laminated structure of polysilicon and a metal material. For example, the metal material uses tungsten or tungsten silicide. In addition, the first hard mask 34 is formed of, for example, a silicon nitride film (Si ₃ N ₄ ).

In particular, since the second hard mask 35 serves as a protective layer to prevent loss of the first hard mask 34 when forming the subsequent contact hole, the second hard mask 35 is formed of a material having excellent etching resistance to the oxide film recipe during subsequent etching of the insulating layer. do. In this case, the material forming the second hard mask 35 is formed of an insulating material of silicon carbide (Silicon Carbide) series containing carbon, for example, is formed of any one selected from the group of SiC, SiCN, and SiCO. In addition, the second hard mask 35 may be formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), or molecular beam epitaxy (MBE). .

Subsequently, a spacer 36 is formed on the entire surface including the gate pattern G. Here, the spacer 36 is to protect the gate pattern G, and may be formed of, for example, a nitride film.

As shown in FIG. 3B, the insulating layer 37 is formed on the spacer 36 until the gate pattern G is filled. Here, the insulating layer 37 is for insulating between the gate patterns G and interlayer insulating with subsequent bit lines, and includes all materials applicable to a gap fill process, but is formed of, for example, an oxide film. Is formed of any one of BPSG, SOG or HDP oxide film.

Subsequently, a mask pattern 38 having a predetermined contact hole area is formed on the insulating layer 37. Here, the mask pattern 38 is formed of any one of a mask material such as nitride film, polysilicon, or carbon on the insulating layer 37, and a photoresist film is coated on the mask material, and the contact hole planned area is exposed and developed. After forming the photoresist pattern for opening the photoresist pattern, the photoresist pattern is formed by etching the mask material with an etching mask. At this time, the photoresist pattern is removed with an oxygen strip.

In addition, the contact hole planned area defined by the mask pattern 38 is a landing plug contact hole (LPC Hole) scheduled area.

Subsequently, a self-aligned contact (SAC) etching process is performed using the mask pattern 38 as an etching mask.

As shown in FIG. 3C, the self-aligned contact etching process is performed to form the contact hole 39, that is, the landing plug contact hole. Here, the self-aligned contact etching process is carried out with a fluorine-based plasma, for example, CxFy (x, y is 1 to 10) as a stock angle gas. CxFy gas is carried out by any one selected from the group of C ₃ F ₃ , C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F ₈ and C ₅ F ₁₀ . Further, gas CaHbFc (a, b, c is 1 to 10) gas and O ₂ for generating a polymer in the self-aligned contact etching process are added thereto. CaHbFc gas is carried out with any one selected from the group of CH ₂ F ₂ , C ₃ HF ₅ and CHF ₃ . In this case, any one inert gas selected from the group of He, Ne, Ar, and Xe is used as the carrier gas.

When the formation of the contact hole 39 is completed, the upper portion of the gate pattern G is partially lost ('D'). However, since the second hard mask 35 having a high selectivity with the insulating layer 37 having an oxide film is formed on the uppermost layer of the gate pattern G, the first hard mask even if sufficient etching is performed so as not to cause an open problem. 34 is not lost.

That is, in the case of the silicon carbide-based second hard mask 35, the etching resistance to the oxide film etching recipe is superior to that of the nitride-based first hard mask 34, so the second hard mask 35 may have a first hard mask 34. Etch selectivity is higher than Accordingly, the loss of the first hard mask 34 positioned below the second hard mask 35 is prevented, and the stacked structure of the first and second hard masks 34 and 35 is formed as the gate hard mask to form a nitride film. The loss of the first hard mask 34 and the spacer 36 can be further reduced compared to the conventional gate pattern structure in which only the first hard mask 34 is formed of a single layer.

As shown in FIG. 3D, the conductive material 40 is formed until the contact hole 39 is filled. Here, the conductive material 40 is for forming a contact plug, that is, a landing plug contact (LPC), for example, formed of polysilicon.

As shown in FIG. 3E, planarization is performed on the first hard mask 34 to form the landing plug contact 40A. Here, the planarization may be performed by a chemical mechanical polishing (CMP) process, but the surface of the first hard mask 34 is exposed, that is, the second hard mask 35 above the first hard mask 34. Continue until is removed. In addition, an etching back process for forming a plug may be performed before planarization.

At the time when the planarization is completed, all of the second hard mask 35 is removed at the same time as the landing plug contact 40A is formed, and the gate pattern G ₁ without loss of the first hard mask 34 and the spacer 36 is removed. Is formed. In addition, isolation between each landing plug contact 40A is completed.

According to the present invention, the first hard mask and the spacer are formed by additionally forming a second carbide mask of silicon carbide-based silicon containing carbon having a high selectivity with respect to the oxide film on the uppermost layer of the gate pattern. By preventing the loss of the first hard mask thickness and improvement of the profile and at the same time has the advantage that can solve the problem of opening the contact hole.

In addition, although the preferred embodiment of the present invention has been described with respect to the gate pattern, it can be applied to any structure that applies the recipe of the line pattern and the self-aligned contact (SAC) etching process, such as the bit line pattern. .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a silicon carbide-based hard mask containing carbon having a high selectivity with respect to an oxide film is further formed on the uppermost layer of the gate pattern to secure the thickness of the gate hard mask remaining after forming the contact hole and to improve the profile. At the same time, it solves the problem of opening of contact hole, which is effective in increasing process progress margin and improving device reliability.

Claims (6)

Forming a pattern in which an electrode, a nitride film-based first hard mask, and a carbon-containing second hard mask are sequentially stacked on the semiconductor substrate; Forming an insulating layer on the entire surface including the pattern; Forming a nitride film mask pattern on the insulating layer to open a contact hole region; And Forming a contact hole self-aligned to the pattern by etching the insulating layer with a self-aligned contact etch using the nitride film mask pattern as an etch mask Contact hole manufacturing method of a semiconductor device comprising a. The method of claim 1, The second hard mask containing the carbon is a contact hole manufacturing method of a semiconductor device, characterized in that formed with a silicon carbide series containing carbon. The method of claim 2, The silicon carbide-based contact hole manufacturing method of a semiconductor device, characterized in that formed by any one selected from the group of SiC, SiCN and SiCO. The method of claim 3, The second hard mask is a contact hole manufacturing method of a semiconductor device, characterized in that formed by any one of chemical vapor deposition, physical vapor deposition or molecular beam epitaxy. The method of claim 1, The nitride layer-based first hard mask may be formed of a silicon nitride layer. The method of claim 1, Etching the insulating layer with a self-aligned contact etch to form a contact hole self-aligned in the pattern; Forming a conductive material until the contact hole is filled; And Forming a contact plug by performing a planarization process on the nitride layer-based first hard mask Contact hole manufacturing method of a semiconductor device characterized in that it further comprises.

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