KR100531460B1 - Method for manufacturing semiconductor devcie - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device that can prevent the collapse of the gate electrode pattern and at the same time reduce the parasitic capacitance generated between the adjacent gate electrode pattern, the semiconductor device of the present invention is a semiconductor substrate, the semiconductor substrate A field oxide film having a protrusion formed therein and protruding over the surface of the semiconductor substrate to define a plurality of active regions, a gate oxide film formed on the active region, and covering both the active region and the field oxide film formed on the gate oxide film. Including the gate electrode is embedded between the protrusions of the field oxide film, it is possible to prevent the collapse of the gate pattern by increasing the contact area of the lower area of the gate electrode, and between adjacent gate patterns Reduces parasitic capacitance by reducing overlap area There is an effect that it is possible to improve the operating speed of the transistor.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVCIE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a semiconductor device having a gate electrode.

Recently, as the design rules of MOSFETs are rapidly reduced to the 90 nm level, the line widths of gate electrodes, the thickness of gate oxide films, and the depth of junctions correspondingly decrease. In particular, in view of the gate electrode, there is a need to develop a low resistance gate electrode to solve the RC delay problem.

Therefore, the research on the laminated gate electrode (hereinafter referred to as polycide gate electrode) of the transition metal silicide / polysilicon film that can replace the general polysilicon film gate electrode has been conducted. Tungsten polyside gate electrode is applied to mass production and is produced as a product.

1A and 1B are layout diagrams illustrating cells of a general DRAM and transistors around the cells.

As shown in FIG. 1A, a DRAM cell includes an active region 101a and an isolation region 102 in a wafer 100, and includes a plurality of gate electrode patterns crossing the upper portion of the active region 101a. G1) is formed at predetermined intervals.

As shown in FIG. 1B, in the transistors around the cell, an active region 101b to be a source / drain of the transistor is formed in the wafer 100, and a gate electrode pattern G2 is formed on the active region 101b. Is placed. A contact 103 is formed between the active region 101b and the wiring layer for applying a signal to the gate electrode pattern G2.

2A and 2B are cross-sectional views taken along cut planes A-A ', B-B', C-C ', and D-D' of FIG. 1.

First, referring to FIG. 2A, which shows cross-sectional views along the lines A-A 'and B-B' of FIG. 1, a field oxide film 12, which is an isolation region, is formed on a semiconductor substrate 11, and the field oxide film 12 is formed. ) And a gate electrode pattern G1 stacked in the order of the gate oxide film 13, the polysilicon film 14, the tungsten silicide film 15, and the gate hard mask 16 on the semiconductor substrate 11. Gate spacers 17 are formed on both sidewalls of the gate electrode pattern G1.

The gate electrode pattern G2 of the peripheral transistor is also formed in the same structure as the gate electrode pattern G1 formed in the cell. Here, the wiring layer 19 is connected to the tungsten silicide 15 through the interlayer insulating film 18 and the gate hard mask 16 covering the gate pattern.

In FIG. 2A, the gate electrode patterns G1 and G2 have their long axis directions, and are formed to overlap the semiconductor substrate 11 and the field oxide film 12.

Next, referring to FIG. 2B, which is a cross-sectional view taken along lines C-C ′ and D-D ′ of FIG. 1, similarly to FIG. 2A, a field oxide film 12 as an element isolation region is formed on a semiconductor substrate 11. A gate electrode pattern formed on the field oxide film 12 and the semiconductor substrate 11 in the order of the gate oxide film 13, the polysilicon film 14, the tungsten silicide film 15, and the gate hard mask 16. (G1, G2) are formed. Gate spacers 17 are formed on both sidewalls of the gate electrode pattern G1.

In FIG. 2B, the gate electrode patterns G1 and G2 have their short axis directions, and are formed on the semiconductor substrate 11 and the field oxide layer 12 in the cell, and in the peripheral transistor, the semiconductor substrate 11. ) Is formed on top.

However, as the design rule is reduced when manufacturing a semiconductor device of the related art as shown in FIGS. 2A and 2B, the width reduction 20 of the gate electrode pattern for forming the transistor and the collapse of the gate electrode pattern are caused. have. In addition, in order to prevent the gate electrode from falling, it is advantageous to lower the thickness 21 of the gate electrode pattern, but due to the sheet resistance (Rs) problem, it is necessary to increase the thickness or maintain the level of the previous product. That is, since the semiconductor process proceeds to a structure in which the line width is reduced and the film thickness is increased, the semiconductor process is increasingly weak in terms of pattern collapse.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method of manufacturing the same, which can prevent parasitic capacitance occurring between adjacent gate electrode patterns while preventing the gate electrode pattern from falling down. There is a purpose.

The semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a field oxide film formed in the semiconductor substrate and having a protrusion projecting over the surface of the semiconductor substrate defining a plurality of active regions, a gate oxide film formed on the active region, And a gate electrode formed on the gate oxide film and covering both the active region and the field oxide film, wherein a portion of the gate electrode is buried between the protrusions of the field oxide film. And a first film on the gate oxide film embedded between the protrusions of the oxide film, and a second film covering the surface of the first film and the field oxide film.

In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of forming a field oxide film having a protrusion protruding on the surface of the semiconductor substrate while defining a plurality of active regions on the semiconductor substrate, forming a gate oxide film on the active region, And forming a gate electrode having a portion covering the active region and the field oxide film while a portion of the field oxide film is buried between the protrusions of the field oxide film on the gate oxide film. The method may include forming a device isolation pad pattern on the semiconductor substrate, forming a trench by etching the semiconductor substrate using the pad pattern as an etch barrier, and forming a gap fill insulating layer until the trench fills the trench. Under-gap the gap fill insulating layer until the surface of the pad pattern is exposed. And mechanically polishing (Under CMP), and selectively removing the pad pattern, wherein the forming of the gate electrode is formed on the field oxide layer until it fills between the protrusions of the field oxide layer. Depositing a first film for a gate electrode, chemical mechanical polishing the first electrode for a gate electrode until the surface of the field oxide film is exposed, and forming a second film for the gate electrode on the entire surface including the polished first film And selectively etching the second film in such a manner as to cover both the field oxide film and the second film.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Hereinafter, the left side of the figure is a cross-sectional view of the present invention taken along the line AA ′ of FIG. 1A, and the right side of the figure shows a cross-sectional view of the present invention taken along the line B-B ′ of FIG. 1B, and is cut for convenience of description. Lines will be omitted and are all cross-sectional views of the manufacturing process in the y-axis direction.

As shown in FIG. 3A, after the buffer oxide film 32 is deposited on the semiconductor substrate 31, the hard mask nitride film 33 is deposited on the buffer oxide film 32. Here, the buffer oxide film 32 is to relieve stress on the surface of the semiconductor substrate 31 when the hard mask nitride film 33 is deposited, and the hard mask nitride film 33 is used for etching etching and chemical mechanical polishing during subsequent ISO etching. It acts as a pad.

Next, an ISO mask (not shown) is formed on the hard mask nitride film 33 and patterned by exposure and development to define an isolation region, and then the ISO mask is used as an etching mask. 33) and the buffer oxide film 32 are sequentially etched.

Next, after the ISO mask is removed, the trench 34 is formed by etching the exposed semiconductor substrate 31 to a predetermined depth using the hard mask nitride film 33 as an etching mask after etching the buffer oxide film 32.

As shown in FIG. 3B, an insulating film for separating an element, for example, a high density plasma oxide layer 35, is deposited to sufficiently fill the trench 34 on the semiconductor substrate 31. At this time, the high-density plasma oxide film 35 uses a plasma deposition method using a silicon source and oxygen gas, preferably a chemical vapor deposition method (CVD) using a high density plasma (High Density Plasma).

Next, the high density plasma oxide film 35 is subjected to chemical mechanical polishing (CMP) until the surface of the hard mask nitride film 33 is exposed. At this time, the polishing target T1 during chemical mechanical polishing is set as a target for which the hard mask nitride film 33 is partially lost. That is, instead of introducing an excessive CMP process in which the hard mask nitride film 33 is consumed in a large amount, an under CMP process in which the hard mask nitride film 33 is consumed in a small amount or hardly consumed is applied.

As shown in FIG. 3C, after the chemical mechanical polishing of the high density plasma oxide film 35, a field oxide film 35a made of a high density plasma oxide film is formed in the trench 34. The field oxide film 35a and the hard mask nitride film 33 around the field oxide film 35a are flat without a step.

As shown in FIG. 3D, a cleaning process using a phosphoric acid solution (H ₃ PO ₄ ) is performed to remove the hard mask nitride layer 33.

Here, after the hard mask nitride film 33 is removed, a height difference of 'd1' occurs between the semiconductor substrate 31 and the field oxide film 35a.

Next, an implantation process 36 for controlling the well and the threshold voltage is performed. Here, the ion implantation process is performed in a state in which the buffer oxide film 32 remaining after the hard mask nitride film 33 is left as it is, or a separate oxide film (commonly referred to as a screen oxide film) after removing the buffer oxide film 32 is removed. Proceed after forming again. On the other hand, when the buffer oxide film 32 is removed, a cleaning process using an HF or BOE solution is performed.

As shown in FIG. 3E, after the buffer oxide film 32 or the screen oxide film is removed, the gate oxide film 37 is formed on the surface of the semiconductor substrate 31.

Next, a first gate electrode film to be used as the gate electrode is deposited on the gate oxide film 37. Here, the polysilicon film 38 is used for the first gate electrode film.

After the deposition of the polysilicon film 38, the surface is uneven due to the step caused by the height difference existing between the surface of the semiconductor substrate 31 and the field oxide film 35a. That is, the step coverage of the polysilicon film 38 is poor.

A chemical mechanical polishing (CMP) process is performed to remove the poor step coverage of the polysilicon film 38. At this time, when the chemical mechanical polishing of the polysilicon film 38, the polishing target (T2) is a polysilicon film 38 is left to a part thickness on the target or the field oxide film 35a is exposed to the surface of the field oxide film (35a) Proceed to the target.

Hereinafter, the case where the surface of the field oxide film 35a is polished with the target exposed will be described.

3F shows the results after chemical mechanical polishing of the polysilicon film 38.

As shown in FIG. 3F, the surface of the polysilicon film 38a and the field oxide film 35a are planarized by planarizing the polysilicon film 38 through a chemical mechanical polishing process until the surface of the field oxide film 35a is exposed. There is no step between the surfaces.

Next, as illustrated in FIG. 3G, a tungsten silicide layer WSi ₂ , 39 is deposited on the planarized product, that is, on the entire surface including the polysilicon layer 38a as a second gate electrode layer. Subsequently, a gate hard mask 40 is formed on the tungsten silicide film 39.

As shown in FIG. 3H, a gate mask (not shown) for defining a gate electrode pattern is formed on the gate hard mask 40, and then the gate hard mask 40 and the tungsten silicide layer are formed as an etch mask. The 39 is etched to form a gate pattern.

Next, after forming the gate spacer 41 in contact with both side walls of the gate pattern, an interlayer insulating film 42 is formed on the entire surface, and the interlayer insulating film 42 is etched to form a contact hole, and a semiconductor is formed through the contact hole. The wiring layer 43 connected to the substrate is buried.

4 is a cross-sectional view of the result of FIG. 3H in the x-axis direction. That is, hereinafter, the left side of the figure is a cross-sectional view of the present invention taken along the line AA ′ of FIG. 1A, and the right side of the figure shows a cross-sectional view of the present invention taken along the line B-B ′ of FIG. 1B, and is cut for convenience of description. Lines will be omitted.

As described above, in order to solve the gate pattern collapse problem, the polysilicon film of the polysilicon film except for the portion used as the gate electrode of the transistor is removed. This increases the contact area. In addition, the polysilicon film 38a having a relatively high resistance among the gate electrodes is left only in the active region. In other words, the thickness of the tungsten silicide film which has the greatest influence on Rs of the gate electrode is maintained, and the polysilicon film having a relatively low influence on Rs increases contact number by removing all portions other than the transistor.

The parasitic capacitance is reduced by 15 to 35% by reducing the overlap area with adjacent patterns.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of preventing the gate pattern from falling down by increasing the contact area of the lower area of the gate electrode.

In addition, the parasitic capacitance is reduced by reducing the overlap area between adjacent gate patterns, thereby improving the operation speed of the transistor.

1A and 1B are layout diagrams illustrating cells of a general DRAM and transistors around the cells;

2A and 2B are cross-sectional views taken along cut planes A-A ', B-B', C-C ', and D-D' of FIG. 1;

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention;

4 is a cross-sectional view of the result of FIG. 3H in the x-axis direction.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 buffer oxide film

33 hard mask nitride film 34 trench

35a: field oxide film 37: gate oxide film

38, 38a: polysilicon film 39: tungsten silicide film

40: gate hard mask nitride film

Claims (7)

Semiconductor substrates; A field oxide film formed in the semiconductor substrate and having a protrusion projecting over the surface of the semiconductor substrate while defining a plurality of active regions; A gate oxide film formed on the active region; And A gate electrode formed on the gate oxide layer and covering both the active region and the field oxide layer, wherein a portion of the gate electrode is buried between the protrusions of the field oxide layer. Semiconductor device comprising a. The method of claim 1, The gate electrode, A first film on the gate oxide film buried between the protrusions of the field oxide film; And A second film covering the surface of the first film and the field oxide film A semiconductor device comprising a. The method of claim 2, The first film is a polysilicon film, and the second film is a tungsten silicide film. Forming a field oxide film on the semiconductor substrate, the field oxide film having a protrusion protruding from the surface of the semiconductor substrate while defining a plurality of active regions; Forming a gate oxide film on the active region; And Forming a gate electrode having a portion covering the active region and the field oxide layer while a portion of the field oxide layer is buried between the protrusions of the field oxide layer on the gate oxide layer; Method for manufacturing a semiconductor device comprising a. The method of claim 4, wherein Forming the field oxide film, Forming a device isolation pad pattern on the semiconductor substrate; Etching the semiconductor substrate using the pad pattern as an etch barrier to form a trench; Forming a gapfill insulating film until the trench is filled; Under chemical mechanical polishing (Under CMP) the gap fill insulating layer until the surface of the pad pattern is exposed; And Selectively removing the pad pattern Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Forming the gate electrode, Depositing a first film for a gate electrode on the field oxide layer until the gap between the protrusions of the field oxide layer is filled; Chemical mechanical polishing the first film for the gate electrode until the surface of the field oxide film is exposed; Forming a second film for a gate electrode on the entire surface including the polished first film; and Selectively etching the second layer to cover both the field oxide layer and the second layer Method for manufacturing a semiconductor device comprising a. The method of claim 6, And the first film is formed of a polysilicon film, and the second film is formed of a tungsten silicide film.