KR20060046363A - 반도체 집적회로 장치 - Google Patents

반도체 집적회로 장치 Download PDF

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Publication number
KR20060046363A
KR20060046363A KR1020050046640A KR20050046640A KR20060046363A KR 20060046363 A KR20060046363 A KR 20060046363A KR 1020050046640 A KR1020050046640 A KR 1020050046640A KR 20050046640 A KR20050046640 A KR 20050046640A KR 20060046363 A KR20060046363 A KR 20060046363A
Authority
KR
South Korea
Prior art keywords
state
output
signal
terminal
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020050046640A
Other languages
English (en)
Korean (ko)
Inventor
후미키 카와카미
나오키 야다
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20060046363A publication Critical patent/KR20060046363A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356165—Bistable circuits using complementary field-effect transistors using additional transistors in the feedback circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020050046640A 2004-06-07 2005-06-01 반도체 집적회로 장치 Withdrawn KR20060046363A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2004-00168127 2004-06-07
JP2004168127 2004-06-07
JPJP-P-2005-00055707 2005-03-01
JP2005055707A JP2006024886A (ja) 2004-06-07 2005-03-01 半導体集積回路装置

Publications (1)

Publication Number Publication Date
KR20060046363A true KR20060046363A (ko) 2006-05-17

Family

ID=35446996

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050046640A Withdrawn KR20060046363A (ko) 2004-06-07 2005-06-01 반도체 집적회로 장치

Country Status (4)

Country Link
US (2) US20050270064A1 (enExample)
JP (1) JP2006024886A (enExample)
KR (1) KR20060046363A (enExample)
TW (1) TW200612547A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101205323B1 (ko) * 2006-09-28 2012-11-27 삼성전자주식회사 리텐션 입/출력 장치를 이용하여 슬립모드를 구현하는시스템 온 칩
US7839016B2 (en) * 2007-12-13 2010-11-23 Arm Limited Maintaining output I/O signals within an integrated circuit with multiple power domains
JP6283237B2 (ja) * 2013-03-14 2018-02-21 株式会社半導体エネルギー研究所 半導体装置
US9417640B2 (en) * 2014-05-09 2016-08-16 Macronix International Co., Ltd. Input pin control
CN108322211B (zh) * 2017-01-18 2021-04-02 中芯国际集成电路制造(上海)有限公司 一种i/o接口电路输出状态的检测电路和电子系统
JP2019053656A (ja) * 2017-09-19 2019-04-04 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3218103B2 (ja) * 1992-12-25 2001-10-15 三菱電機株式会社 半導体記憶装置
JP3567601B2 (ja) * 1995-03-30 2004-09-22 セイコーエプソン株式会社 入出力バッファ回路及び出力バッファ回路
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US6448812B1 (en) * 1998-06-11 2002-09-10 Infineon Technologies North America Corp. Pull up/pull down logic for holding a defined value during power down mode
US6624656B1 (en) * 1999-10-15 2003-09-23 Triscend Corporation Input/output circuit with user programmable functions
JP3674488B2 (ja) * 2000-09-29 2005-07-20 セイコーエプソン株式会社 表示コントロール方法、表示コントローラ、表示ユニット及び電子機器
JP2003187593A (ja) * 2001-12-19 2003-07-04 Toshiba Corp 半導体装置及び不揮発性半導体記憶装置
JP3607262B2 (ja) * 2002-05-28 2005-01-05 沖電気工業株式会社 半導体装置の静電破壊防止保護回路
US6795369B2 (en) * 2002-11-22 2004-09-21 Samsung Electronics Co., Ltd. Address buffer and semiconductor memory device using the same

Also Published As

Publication number Publication date
JP2006024886A (ja) 2006-01-26
US20050270064A1 (en) 2005-12-08
TW200612547A (en) 2006-04-16
US20080303548A1 (en) 2008-12-11

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20050601

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid