KR20060004472A - Stack package - Google Patents

Abstract

The present invention discloses a stack package to which the center pad-type semiconductor chips are applied. The disclosed stack package includes a substrate having a circuit pattern including an electrode pad, a center pad type first semiconductor chip attached to the substrate in a face-up type via an adhesive layer, A dummy substrate attached to the first semiconductor chip to expose its bonding pads, the dummy substrate having a solder resistor and first and second bond fingers disposed on both sides thereof, a first bond finger and a first semiconductor of the dummy substrate; A first metal wire connecting the bonding pads of the chip, a second metal wire connecting the second bond finger of the dummy substrate and the electrode pad of the dummy substrate, and a face-up type on the dummy substrate via an adhesive layer. A second semiconductor chip of a center pad type attached thereto, a third metal wire connecting the bonding pad of the second semiconductor chip to the substrate electrode pad, and the first and second semiconductor chips including the dummy substrate and the first and third chips. On substrates with metal wires An encapsulant for sealing the lower surface, and a solder ball attached to the lower surface of the substrate.

Description

Stack package

1 is a cross-sectional view showing a conventional stack package.

Figure 2 is a cross-sectional view showing another conventional stack package.

3 is a cross-sectional view illustrating a stack package according to the present invention.

Explanation of symbols on the main parts of the drawings

30: stack package 31: substrate

31a: electrode pads 32a, 32b, 32c: WBL tape

33: first semiconductor chip 33a: bonding pad

34: second semiconductor chip 34a: bonding pad

35 dummy substrate 35a solder resistor

35b, 35c: Bond finger 37a, 37b, 37c: Metal wire

38: sealing agent 39: solder ball

The present invention relates to a stack package, and more particularly, to a stack package in which both center pad semiconductor chips are stacked in a face-up type.

As is well known, packaging techniques have been advanced in the direction of mounting a larger number of packages on a limited size substrate, i.e., reducing the size of the package. For example, a chip scale package has been proposed in which a semiconductor chip occupies about 80% of the total size of the package.

However, although the chip scale package has an advantage of increasing the number of packages that can be mounted by reducing its size, there is a limit in increasing its capacity since one semiconductor chip is mounted in one package as in a typical semiconductor package. So, there is a difficulty in implementing a large capacity system.

Accordingly, research has been actively conducted on stack packages in which two or three semiconductor chips are mounted in one package to reduce the size of the package and increase the capacity of the package.

According to the stack package, two 64M DRAM chips can be stacked to form a 128M DRAM class, and two 128M DRAM chips can be stacked to be 256M DRAM class. It is easy. In addition, stack packages have advantages in terms of mounting density and efficiency of mounting area utilization.

Here, a method of stacking two semiconductor chips includes a method of embedding two stacked chips into one package and a method of stacking two packaged packages.

The stack method of the former method is easy to manufacture, but has a disadvantage in that the overall thickness is thick, while the stack package of the latter method is somewhat difficult to manufacture, but the overall thickness is thin, which can advantageously meet the needs of thin and light products. There is an advantage.

Hereinafter, a conventional stack package will be described with reference to the accompanying drawings.

1 and 2 are cross-sectional views showing conventional stack packages. As shown, the conventional stack packages 10 and 20 have an edge pad type first and second semiconductor chips 3 and 4 face-up on a substrate 1. up), the bonding pads 3a and 4a of the chips 3 and 4 and the electrode pads 1a of the substrate circuit pattern are interconnected by metal wires 7a and 7b. The upper surface of the substrate 1 including the first and second semiconductor chips 3 and 4 and the metal wires 7a and 7b is sealed with an encapsulant 8 such as EMC, and the The lower surface is made of a structure attached to the solder ball 9, which is a mounting means to the external circuit.

Here, the first semiconductor chip 3 disposed below is attached on the substrate 1 by an adhesive 2, and in particular, between the first semiconductor chip 3 and the second semiconductor chip 4. In order to secure the wire loop height of the first metal wire 7a connecting the first semiconductor chip 3 and the substrate electrode pad 1a, as shown in FIG. ) Is interposed with an adhesive 5, or as shown in FIG. 2, a dummy die 16 with an adhesive 15 attached to the upper and lower surfaces thereof is interposed.

However, the above-described conventional stack package can only stack edge pad-type semiconductor chips structurally with respect to stacking two semiconductor chips in a face-up type, and a center pad type in which bonding pads are arranged at the center of the chip. (center pad type) semiconductor chips are difficult to apply.                         

Accordingly, an object of the present invention is to provide a stack package to which the center pad type semiconductor chips are applicable.

In order to achieve the above object, the present invention, a substrate having a circuit pattern including an electrode pad; A center pad type first semiconductor chip attached to the substrate in a face-up type via an adhesive layer; A dummy substrate attached to the first semiconductor chip to expose a bonding pad of the first semiconductor chip and having a solder resistor and first and second bond fingers disposed on both sides thereof; A first metal wire connecting the first bond finger of the dummy substrate and the bonding pad of the first semiconductor chip; A second metal wire connecting the second bond finger of the dummy substrate and the substrate electrode pad; A second semiconductor chip of a center pad type attached to the dummy substrate in a face-up type via an adhesive layer; A third metal wire connecting the bonding pad of the second semiconductor chip and the substrate electrode pad; An encapsulant sealing the first and second semiconductor chips including the dummy substrate and the upper surface of the substrate including the first and third metal wires; And a solder ball attached to the lower surface of the substrate.

Here, the first bond finger and the second bond finger of the dummy substrate are internally interconnected, and the solder resistor is higher than the bond finger to secure the wire loop height.

In addition, the adhesive layer is preferably a WBL (Wafer Back side Lamination) tape, and may be composed of an adhesive.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing a stack package according to the present invention.

As shown, the stack package 30 according to the present invention includes a dummy substrate 35 having a wafer back side lamination (WBL) tape 32a attached to a rear surface thereof on a center pad-type first semiconductor chip 33. By attaching to secure the height of the wire loop, the center pad-type second semiconductor chip 34 is stacked on the face-up type.

In more detail, the stack package 30 according to the present invention is provided with an adhesive layer, preferably, WBL tape 32a, attached to a rear surface of a substrate 31 having a circuit pattern (not shown) including an electrode pad 31a. A center pad type first semiconductor chip 33 is attached in a face-up type, and a WBL tape (on the back surface) is exposed to expose its bonding pad 33a on the bonding pad forming surface of the first semiconductor chip 33. 32b) is attached to a dummy substrate 35 having solder resistors 35a and bond fingers 35b and 35c on the front surface thereof, and the bonding pads 33a of the exposed first semiconductor chip 33 are adjacent to the bonding pads 33a. The bond fingers 35b of the dummy substrate 35 are interconnected by the first metal wire 37a, and the bond electrodes 35c of the dummy substrate 35 adjacent to the substrate electrode pad 31a are connected to each other. The center pad is interconnected by a metal wire 37b, and a WBL tape 32c is attached to the rear surface of the dummy substrate 35. Type second semiconductor chip 34 is attached to the face-up type, and the bonding pad 34a and the substrate electrode pad 31a of the second semiconductor chip 34 are interconnected with the third metal wire 37c. The upper surface of the substrate including the structures is sealed with an encapsulant 38 such as EMC, and the solder ball 39 attached to an external circuit, for example, a printed circuit board (PCB), is attached to the rear surface of the substrate. to be.

In this structure, the dummy substrate 35 is a wire of metal wires 35a and 35b connecting the bonding pad 33a of the first semiconductor chip 33 and the electrode pad 31a of the substrate 31. In order to secure the loop height, the center pad-type semiconductor chips 33 and 34 can be stacked in a face-up type according to the interposition of the dummy substrate 35.

In the dummy substrate 35, the solder resistor 35a is a member for covering the remaining circuit wiring portions except for the bond fingers 35b and 35c, and therefore, the bond fingers are disposed on both sides of the solder resistor 35a, respectively. The fields 35b and 35c are internally interconnected. In particular, the solder resistor 35a is formed to have a height higher than the bond fingers 35b and 35c to secure the wire loop height.

The stack package 30 according to the present invention having the structure as described above can secure the wire loop height very easily by interposing the dummy substrate 35 between the semiconductor chips 33 and 34. Type semiconductor chips 33 and 34 are applied, but a chip stack in a face-up type is possible.

On the other hand, in the stack package according to the present invention described above, WBL tape is used as the adhesive layer, but it is also possible to use a conventional adhesive instead.

Hereinafter, the manufacturing process of the stack package according to the present invention as described above will be briefly described.

First, an adhesive layer, preferably WBL tape, is attached to the back side of the center pad-type semiconductor chips in the wafer state. Then, the wafer to which the WBL tape is attached is sawed and separated into individual semiconductor chips.

Next, after the circuit board is provided on the front surface and a strip level dummy substrate having a solder resist is formed to cover the remaining circuit wiring portions except the bond finger, an adhesive layer, preferably, WBL, is formed on the rear surface of the dummy substrate. Attach the tape. The strip level dummy substrate to which the WBL tape is attached is then sawed and separated into individual dummy substrates.

Next, after preparing a substrate having a circuit pattern including an electrode pad, a first semiconductor chip of a center pad type is attached to the substrate through a WBL tape attached to a rear surface of the substrate.

Subsequently, the dummy substrate is attached to the first semiconductor chip in such a manner as to expose its bonding pad. Then, the bonding pad of the first semiconductor chip and the bond finger of the dummy substrate adjacent thereto are connected with the first metal wire through a wire bonding process, and subsequently, the electrode pad of the substrate and the bond finger of the dummy substrate adjacent thereto are connected. Connect with the second metal wire.

Subsequently, the second semiconductor chip of the center pad type is attached in the face-up type via the WBL tape attached to the rear surface on the dummy substrate. Then, a wire bonding process connects the bonding pads of the second semiconductor chip and the substrate electrode pads with a third metal wire.

Next, the upper surface of the substrate including the semiconductor chips and the metal wires having the dummy substrate interposed therebetween is molded with an encapsulant such as EMC. Then, the solder ball is attached to the back of the substrate, thereby completing the fabrication of the stack package of the present invention.

As described above, the present invention can facilitate the fabrication of the stack package while applying the center pad type semiconductor chips as well as the edge pad type by securing the height of the wire loop using the dummy substrate. Therefore, the present invention can not only enable the application of the center pad-type semiconductor chips when manufacturing the stack package, but also ensure the reliability of the package itself.

In addition, the present invention proceeds with die sawing and die attaching with the WBL tape attached to the back side of the wafer, thereby reducing cracking of semiconductor chips during die pick up. Can be.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (5)

A substrate having a circuit pattern including an electrode pad; A center pad type first semiconductor chip attached on the substrate in a face-up type via an adhesive layer; A dummy substrate attached to the first semiconductor chip to expose a bonding pad of the first semiconductor chip, the dummy substrate having a solder resistor and first and second bond fingers disposed on both sides thereof; A first metal wire connecting the first bond finger of the dummy substrate and the bonding pad of the first semiconductor chip; A second metal wire connecting the second bond finger of the dummy substrate and the substrate electrode pad; A second semiconductor chip of a center pad type attached to the dummy substrate in a face-up type via an adhesive layer; A third metal wire connecting the bonding pad of the second semiconductor chip and the substrate electrode pad; An encapsulant sealing the first and second semiconductor chips including the dummy substrate and the upper surface of the substrate including the first and third metal wires; And And a solder ball attached to the lower surface of the substrate. The stack package of claim 1, wherein the first bond finger and the second bond finger of the dummy substrate are interconnected internally. The stack package of claim 1, wherein the solder resistor of the dummy substrate is higher than the bond finger to secure a wire loop height. The stack package of claim 1, wherein the adhesive layer is a wafer back side lamination (WBL) tape. The stack package of claim 1, wherein the adhesive layer is an adhesive.

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