KR100842915B1 - Stack package and manufacturing method of the same - Google Patents

Stack package and manufacturing method of the same Download PDF

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Publication number
KR100842915B1
KR100842915B1 KR1020070005364A KR20070005364A KR100842915B1 KR 100842915 B1 KR100842915 B1 KR 100842915B1 KR 1020070005364 A KR1020070005364 A KR 1020070005364A KR 20070005364 A KR20070005364 A KR 20070005364A KR 100842915 B1 KR100842915 B1 KR 100842915B1
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South Korea
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package
substrate
pads
semiconductor chip
manufacturing
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KR1020070005364A
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Korean (ko)
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권진호
정영희
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A stack package and a manufacturing method thereof are provided to improve a degree of freedom in a design process by forming connective patterns using copper on a connective pad. A plurality of first pads(218) are formed on an edge region of a first substrate(202). A plurality of ball lands are formed below the first substrate. A first semiconductor chip(200) is attached to the first substrate. A plurality of first bonding pads(220) are electrically connected to the first pads by using first metal wires(204). The upper surface of the first substrate is sealed with a first sealant(206). A lower wafer level package is formed by attaching first solder balls(208) to ball lands of the lower surface of the first substrate. A plurality of holes are formed at a first sealant part. A plurality of connective patterns(212) are formed at the holes and the first sealant part. A plurality of second solder balls(208a) are attached to the connective patterns. A second substrate(202a) includes second pads(218a), second ball lands, a second semiconductor chip(200a) having second bonding pads(220a), second metal wires(204a) for connecting electrically the second bonding pads with the second pads. An upper wafer level package is formed by sealing an upper surface of the second substrate by using a second sealant(206a). The upper wafer level package is mounted on the lower level package.

Description

스택 패키지 및 그의 제조 방법{Stack package and manufacturing method of the same}Stack package and manufacturing method thereof

도 1은 종래 스택 패키지를 도시한 단면도.1 is a cross-sectional view showing a conventional stack package.

도 2a 및 도 2b는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도.2A and 2B are cross-sectional views illustrating a stack package according to an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 스택 패키지를 구현하기 위한 접속패드 및 연결 패턴의 구조를 설명하기 위하여 도시한 평면도.3 is a plan view illustrating the structure of a connection pad and a connection pattern for implementing a stack package according to an embodiment of the present invention.

도 4a 내지 도 4e는 본 발명의 실시예에 따른 스택 패키지의 제조 과정을 설명하기 위한 공정별 단면도.Figures 4a to 4e is a cross-sectional view for each process for explaining the manufacturing process of the stack package according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

200 : 제1반도체 칩 200a : 제2반도체 칩 200: first semiconductor chip 200a: second semiconductor chip

202 : 제1기판 202a : 제2기판202: first substrate 202a: second substrate

204 : 제1금속와이어 204a : 제2금속와이어204: first metal wire 204a: second metal wire

206 : 제1봉지제 206a : 제2봉지제206: first encapsulation agent 206a: second encapsulation agent

208 : 제1솔더볼 208a : 제2솔더볼208: first solder ball 208a: second solder ball

210 : 접속패드 212 : 연결 패턴210: connection pad 212: connection pattern

218 : 제1패드 218a : 제2패드218: first pad 218a: second pad

220 : 제1본딩패드 220a : 제2본딩패드220: first bonding pad 220a: second bonding pad

A : 하부 패키지 B : 상부 패키지A: lower package B: upper package

본 발명은 스택 패키지 및 그의 제조 방법에 관한 것으로서, 보다 상세하게는, 스택 패키지 제조 공정을 단순화시키고, 신뢰성을 향상시킬 수 있는 스택 패키지 및 그의 제조 방법에 관한 것이다.The present invention relates to a stack package and a method for manufacturing the same, and more particularly, to a stack package and a method for manufacturing the same that can simplify the stack package manufacturing process and improve reliability.

전자산업의 발전으로 거의 대부분의 전자제품에서 반도체를 사용하게 되면서 다양한 크기와 형태의 패키지가 필요하게 되었고, 반도체 소자의 고용량화, 고집적화 및 빠른 처리 속도에 대한 수요가 증가하고 있는바 반도체 패키지 공정에서 적층에 의해 메모리 밀도(Memory density)를 높일 수 있는 스택 패키지(Stack package)가 각광받고 있다. With the development of the electronics industry, the use of semiconductors in almost all electronic products requires packages of various sizes and shapes, and the demand for higher capacity, higher integration and faster processing speed of semiconductor devices is increasing. As a result, a stack package that can increase a memory density has been in the spotlight.

일반적으로 스택 패키지는 두 개 또는 그 이상의 독립된 패키지를 적층하기 위해 하부에 위치한 패키지의 인쇄회로 기판의 가장자리에 솔더볼을 실장시켜 두 패키지 간을 전기적으로 연결하여 외부로부터 동일한 전기적인 신호를 받게 설계된 패키지 온 패키지(Package on package) 타입의 스택 패키지와 단위 패키지 내에 두께가 얇은 칩(Chip)을 다수 적층하는 칩 스택 패키지로 구별할 수 있다.In general, a stack package is a package on which a solder ball is mounted on the edge of a printed circuit board of a lower package to stack two or more independent packages, and electrically connected between the two packages to receive the same electrical signal from the outside. A package stack type package may be distinguished from a chip stack package in which a plurality of thin chips are stacked in a unit package.

도 1은 종래 스택 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional stack package.

도시된 바와 같이, 종래 패키지 온 패키지 타입의 스택 패키지는 두 개의 하부 및 상부 패키지들(A, B)을 스택한 구조로서, 상부 패키지(B)의 기판(102a)에 부 착된 솔더볼(108a)을 하부 패키지(A)의 기판(102) 상면에 구비된 제1패드(미도시) 또는 재배선에 부착시켜 물리적 및 전기적으로 연결한 구조로 형성되어 있다. As shown, a stack package of a conventional package on package type has a structure in which two lower and upper packages A and B are stacked, and the solder balls 108a attached to the substrate 102a of the upper package B are stacked. It is attached to a first pad (not shown) or redistribution provided on the upper surface of the substrate 102 of the lower package (A) is formed in a structure that is physically and electrically connected.

여기서, 상기 하부 및 상부 패키지들(A, B)은 상면에 다수의 제1 및 제2본딩 패드(120, 120a)를 구비한 제1 및 제2반도체 칩(100, 100a)이 접착제(미도시)를 매개로 상면과 하면에 각각 다수의 제1 및 제2패드(218. 218a)와 볼랜드(미도시)를 구비한 제1 및 제2기판(102, 102a)의 상면에 부착되어 있다. 그리고, 상기 제1 및 제2반도체 칩(100, 100a)과 제1 및 제2기판(102, 102a) 간의 전기적인 연결을 형성하기 위하여 상기 제1 및 제2본딩 패드(120, 120a)와 제1 및 제2패드(218. 218a) 간에는 제1 및 제2금속와이어(104, 104a)가 형성되어 있다. 또한, 상기 제1 및 제2반도체 칩(100, 100a)을 보호하기 위하여 제1 및 제2기판(102, 102a)의 상면에는 EMC(Epoxy molding compound)로 이루어진 제1 및 제2봉지제(106, 106a)가 형성되어 있고, 제1 및 제2기판(102, 102a)의 하면에는 제1 및 제2솔더볼(108, 108a)이 부착되어 있다.The first and second semiconductor chips 100 and 100a having a plurality of first and second bonding pads 120 and 120a on an upper surface of the lower and upper packages A and B may be adhesives (not shown). The upper and lower pads are attached to the upper and lower surfaces of the first and second substrates 102 and 102a each having a plurality of first and second pads 218.218a and borland (not shown). In addition, the first and second bonding pads 120 and 120a and the first bonding pads 120 and 120a may be formed to form an electrical connection between the first and second semiconductor chips 100 and 100a and the first and second substrates 102 and 102a. First and second metal wires 104 and 104a are formed between the first and second pads 218 and 218a. In addition, in order to protect the first and second semiconductor chips 100 and 100a, first and second encapsulants 106 made of an epoxy molding compound (EMC) are formed on upper surfaces of the first and second substrates 102 and 102a. And 106a are formed, and the first and second solder balls 108 and 108a are attached to the lower surfaces of the first and second substrates 102 and 102a.

그러나, 상기 패키지 온 패키지 타입의 스택 패키지는 하부 패키지(A)의 제1반도체 칩(100)이 실장되는 공간을 상부 패키지(B)의 솔더볼(108a)의 높이를 통해 확보하는 방식으로, 하부 패키지(A)의 높이에 따라 상부 패키지(B)의 솔더볼(108a)의 높이도 같이 높아지게 된다. 따라서, 상기 상부 패키지(B)의 솔더볼(108a) 높이가 높아질수록 구 형태의 솔더볼(108a) 부피가 솔더볼 높이의 세제곱에 비례하여 증가하기 때문에 상부 패키지(B)의 솔더볼(108a) 높이를 무한정 크게 할 수는 없다.However, the stack package of the package-on-package type secures a space in which the first semiconductor chip 100 of the lower package A is mounted through the height of the solder ball 108a of the upper package B. According to the height of (A), the height of the solder ball 108a of the upper package B is also increased. Therefore, as the height of the solder ball 108a of the upper package B increases, the volume of the spherical solder ball 108a increases in proportion to the cube of the solder ball height, thereby increasing the height of the solder ball 108a of the upper package B indefinitely. You can't.

또한, 상부 패키지(B)의 제2기판(102a) 가장자리 영역에서만 형성되어 있는 제2솔더볼(108a)로 인해 하부 패키지(A)의 제1봉지제(106) 면의 크기가 상부 패키지(B)보다 작아야만 상부 패키지(B)의 가장자리에 형성되어 있는 제2솔더볼(108a)의 안쪽 공간에 실장될 수 있다. 이러한 점은 패키지 온 패키지 타입의 스택 패키지의 설계에 있어 제한을 두어야만 한다는 한계를 가진다.In addition, the size of the surface of the first encapsulant 106 of the lower package A is increased due to the second solder ball 108a formed only at the edge region of the second substrate 102a of the upper package B. Only smaller than it can be mounted in the inner space of the second solder ball (108a) formed on the edge of the upper package (B). This has the limitation that the design of the stack package of the package on package type must be limited.

그리고, 제2솔더볼이 상기 스택된 패키지들 간에 고르게 형성되지 않아서, 패키지 신뢰성 테스트에서 나쁜 결과가 초래되고, 단순히 패키지의 신뢰성을 높이기 위한 수단으로 더미 솔더볼을 스택 패키지의 중앙부 공간에 실장해야 하는 경우도 발생한다.In addition, since the second solder balls are not evenly formed between the stacked packages, bad results may occur in the package reliability test, and a dummy solder ball should be mounted in the center space of the stack package as a means for simply increasing the reliability of the package. Occurs.

본 발명은 스택 패키지 제조 공정을 단순화시키고, 신뢰성을 향상시킬 수 있는 스택 패키지 및 그의 제조 방법을 제공한다.The present invention provides a stack package and a method of manufacturing the same that can simplify the stack package manufacturing process and improve reliability.

일 실시예에 있어서, 스택 패키지의 제조 방법은, 상면의 가장자리 영역에 다수의 제1패드가 구비되고, 하면에 다수의 제1볼랜드가 구비된 제1기판을 준비하는 단계; 상기 제1기판 상에 패드 재배열로 상면의 가장자리 영역에 구비된 다수의 제1본딩패드와 전기적으로 연결되는 접속패턴을 구비한 제1반도체칩을 접착제를 매개로 부착시키는 단계; 상기 제1본딩패드와 제1패드를 제1금속와이어로 전기적 연결을 시키는 단계; 상기 제1금속와이어 및 제1반도체 칩을 포함한 제1기판의 상면을 제1봉지제로 봉지하는 단계; 상기 제1기판 하면의 볼랜드에 다수의 제1솔더볼을 부착시켜 하부 웨이퍼 레벨 패키지를 형성하는 단계; 상기 제1반도체 칩의 접속패드들이 외부로 노출되도록 상기 제1봉지제 부분에 다수의 홀을 형성하는 단계; 상기 홀 및 이에 인접한 제1봉지제 부분에 연결 패턴을 형성하는 단계; 상기 연결 패턴 상에 제2솔더볼을 부착시키는 단계; 및 상기 하부 웨이퍼 레벨 패키지의 제2솔더볼 상에 상면의 가장자리 영역에 다수의 제2패드가 구비되고, 하면에 상기 하부 패키지의 제2솔더볼과 부착되는 다수의 제2볼랜드가 구비된 제2기판 상에 상면의 가장자리 영역에 구비된 다수의 제2본딩패드가 구비된 제2반도체칩이 부착되어 있고, 제2본딩패드와 제2패드를 전기적으로 연결하는 제2금속와이어가 구비되어 있고, 상기 제2금속와이어 및 제2반도체 칩을 포함한 제2기판의 상면을 제2봉지제로 밀봉하여 제조된 상부 웨이퍼 레벨 패키지를 실장시키는 단계를 포함하는 것을 특징으로 한다. In one embodiment, a method of manufacturing a stack package may include: preparing a first substrate having a plurality of first pads in an edge region of an upper surface thereof, and having a plurality of first borlands provided on a lower surface thereof; Attaching a first semiconductor chip having a connection pattern electrically connected to a plurality of first bonding pads provided in an edge region of an upper surface by rearranging pads on the first substrate through an adhesive; Electrically connecting the first bonding pad and the first pad to a first metal wire; Encapsulating an upper surface of the first substrate including the first metal wire and the first semiconductor chip with a first encapsulant; Attaching a plurality of first solder balls to the ball lands on the lower surface of the first substrate to form a lower wafer level package; Forming a plurality of holes in the portion of the first encapsulant such that the connection pads of the first semiconductor chip are exposed to the outside; Forming a connection pattern in the hole and a portion of the first encapsulant adjacent thereto; Attaching a second solder ball on the connection pattern; And a plurality of second pads formed at an edge area of an upper surface of the second solder ball of the lower wafer level package, and a plurality of second borlands attached to the second solder balls of the lower package on a lower surface of the second substrate. A second semiconductor chip is provided with a plurality of second bonding pads provided in the edge region of the upper surface, and a second metal wire for electrically connecting the second bonding pad and the second pad is provided. And mounting an upper wafer level package manufactured by sealing an upper surface of a second substrate including a bimetallic wire and a second semiconductor chip with a second encapsulant.

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상기 홀은 레이져 드릴링(Laser drilling) 공정으로 형성되는 것을 특징으로 한다.The hole is characterized in that formed by a laser drilling (Laser drilling) process.

상기 연결패턴은 도금 공정으로 형성되는 것을 특징으로 한다. The connection pattern may be formed by a plating process.

상기 연결패턴은 구리(Cu)로 형성되는 것을 특징으로 한다.The connection pattern is characterized in that formed of copper (Cu).

상기 하부 패키지와 상부 패키지는 동일 타입으로 형성된 것을 특징으로 한다.The lower package and the upper package is characterized in that formed in the same type.

상기 하부 패키지와 상부 패키지는 서로 다른 타입으로 형성된 것을 특징으로 한다.The lower package and the upper package is characterized in that formed in different types.

(실시예)(Example)

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 간략하게 설명하면, 본 발명은 두 개 또는 그 이상의 독립된 패키지를 스택하기 위한 스택 패키지에 관한 것으로서, 본딩패드와 연결되는 접속패드를 포함하는 하부 패키지의 반도체칩 상에 레이저 드릴링 공법 및 도금 공법에 의해 다수의 연결패턴이 형성되고, 상기 연결패턴 상에 각각의 솔더볼이 실장되면서 상기 하부 패키지와 상부 패키지를 스택하는 것을 특징으로 한다.First, the technical principle of the present invention will be briefly described. The present invention relates to a stack package for stacking two or more independent packages, wherein the present invention relates to a semiconductor package of a lower package including a connection pad connected to a bonding pad. A plurality of connection patterns are formed by a laser drilling method and a plating method, and each of the solder balls is mounted on the connection patterns to stack the lower package and the upper package.

이와 같이, 상기 접속 패드 상에 다수의 연결패턴이 구비되고, 상기 연결패턴 상에 각각의 솔더볼이 실장된 구조를 갖게 됨에 따라, 스택 된 패키지간의 중앙부 공간을 포함하여 고르게 지지하는 솔더볼이 구비되면서 스택 패키지의 신뢰성을 기대할 수 있게 된다.As such, a plurality of connection patterns are provided on the connection pads, and as each solder ball is mounted on the connection pattern, solder balls are evenly supported including a central space between stacked packages. The reliability of the package can be expected.

또한, 상기 솔더볼이 연결패턴 상에 각각 실장됨에 따라, 스택 패키지를 구현하기 위하여 패키지 간의 전기적인 연결 수단이 솔더볼이 가장자리에만 형성해야 한다는 제약에서 벗어날 수 있어 설계의 자유도를 향상시킬 수 있다.In addition, as the solder balls are respectively mounted on the connection pattern, the electrical connection means between the packages may be freed from the constraint that the solder balls should be formed only at the edges to implement the stack package, thereby improving design freedom.

자세하게는, 도 2a 및 도 2b는 본 발명의 실시예에 따른 스택 패키지를 도시한 단면도로서, 도시된 바와 같이, 하부 패키지(A)는, 먼저, 상면에 다수의 제1패드(218)가 구비되고, 하면에 다수의 제1볼랜드(미도시)를 구비한 제1기판(202)이 배치되어 있고, 상기 제1기판(202) 상에, 상면에 다수의 제1본딩패드(220) 및 각 제1본딩패드(220)와 연결된 접속패드(210)를 구비한 패드 재배열이 이루어진 제1반도체칩(200)이 부착되어 있다.2A and 2B are cross-sectional views illustrating a stack package according to an exemplary embodiment of the present invention. As illustrated, the lower package A has a plurality of first pads 218 on an upper surface thereof. The first substrate 202 having a plurality of first borland (not shown) is disposed on the lower surface, and the plurality of first bonding pads 220 and the upper surface of the first substrate 202 are disposed on the first substrate 202. The first semiconductor chip 200 having the rearrangement of the pads having the connection pads 210 connected to the first bonding pads 220 is attached thereto.

그리고, 상기 각 접속패드(210) 상에 구리(Cu)로 형성된 연결패턴(212)과, 상기 제1패드(218)와 제1본딩패드(220)간을 전기적으로 연결시키는 제1금속와이어(204)와, 상기 연결패턴(212)의 상면이 노출되도록 상기 제1금속와이어(204)와 상기 제1반도체칩(200)을 포함한 제1기판(202)의 상면을 봉지하는 제1봉지제(206) 및 상기 제1기판의 제1볼랜드 상에 부착된 제1솔더볼(208)과, 상기 연결패턴(212) 상에 부착되며, 후속의 상부 패키지와 하부 패키지를 전기적으로 연결하는 제2솔더볼(208a)을 포함한다.In addition, a first metal wire electrically connecting the connection pattern 212 formed of copper (Cu) on the connection pads 210 and the first pad 218 and the first bonding pad 220. 204 and a first encapsulant encapsulating an upper surface of the first substrate 202 including the first metal wire 204 and the first semiconductor chip 200 to expose the upper surface of the connection pattern 212 ( 206 and a first solder ball 208 attached to the first borland of the first substrate, and a second solder ball attached to the connection pattern 212 and electrically connecting a subsequent upper package and lower package ( 208a).

상부 패키지(B)는, 상면에 다수의 제2패드(218a)가 구비되고 하면에 상기 하부 패키지(A)의 제2솔더볼(208a)과 부착되는 다수의 제2볼랜드(미도시)를 구비한 제2기판(202a)이 배치되어 있고, 상기 제2기판(202a) 상에, 상면에 다수의 제2본딩패드(220a)를 구비한 제2반도체칩(200a)이 부착되어 있다.The upper package B includes a plurality of second pads 218a on the upper surface and a plurality of second borlands (not shown) attached to the second solder balls 208a of the lower package A on the lower surface. The second substrate 202a is disposed, and on the second substrate 202a, a second semiconductor chip 200a having a plurality of second bonding pads 220a is attached.

그리고, 상기 제2패드와(218a) 제2본딩패드(220a)간을 전기적으로 연결시키는 제2금속와이어(204a)와, 상기 제2금속와이어(204a) 및 제2반도체칩(200a)을 포함한 제2기판(202a)의 상면을 봉지하는 제2봉지제(206a)를 포함한다.And a second metal wire 204a electrically connecting the second pad 218a and the second bonding pad 220a, and the second metal wire 204a and the second semiconductor chip 200a. A second encapsulant 206a encapsulating the upper surface of the second substrate 202a is included.

여기서, 상기 하부 패키지(A)와 상부 패키지(B)는, 도 2a에 도시된 바와 같이, 동일 타입의 패키지로 이루어지며, 도 2b에 도시된 바와 같이, 서로 다른 타입의 패키지로 이루어질 수 있다.Here, the lower package (A) and the upper package (B), as shown in Figure 2a, made of the same type of package, as shown in Figure 2b, may be made of different types of packages.

전술한 바와 같이, 본 발명은, 하부 패키지를 구성하고 있는 제1반도체 칩이 재배열로 이루어져 있고, 이에 따라, 제1본딩패드와 연결되는 접속패드 상에 구리로 형성된 연결패턴이 고르게 구비하게 되고, 상기 연결패턴 상에 각각의 제2솔더볼이 실장하게 되면서, 하부 패키지와 상부 패키지 간의 중앙부 공간을 포함하여 고르게 지지하는 솔더볼을 확보할 수 있게 되므로, 이에 따라, 패키지 신뢰성 테스트에서 우수한 결과를 얻을 수 있다.As described above, in the present invention, the first semiconductor chip constituting the lower package is rearranged, and thus the connection pattern formed of copper is evenly provided on the connection pad connected to the first bonding pad. Since each of the second solder balls is mounted on the connection pattern, it is possible to secure solder balls that are evenly supported including the center space between the lower package and the upper package, thereby obtaining excellent results in the package reliability test. have.

또한, 상기 제2솔더볼이 하부 패키지의 연결패턴과 각각 실장됨에 따라, 스택 패키지를 구현하기 위하여 패키지 간의 전기적인 연결 수단이 솔더볼을 가장자리에만 형성해야 한다는 제약에서 벗어날 수 있어 설계의 자유도가 향상된다.In addition, as the second solder balls are respectively mounted with the connection patterns of the lower package, electrical connection means between the packages may be removed from the constraint that the solder balls should be formed only at the edges in order to implement the stack package, thereby improving design freedom.

도 3은 본 발명의 실시예에 따른 하부 패키지에서 패드 재배열이 이루어진 반도체칩과 기판 간의 전기적 연결을 나타내는 평면도로서, 도시된 바와 같이, 패드 재배열이 이루어진 제1반도체 칩(300)의 상면에 형성된 접속패드(310)는 제1반도체 칩(300)의 가장자리 영역에 형성된 다수의 제1본딩패드(320)와 재배선(310a)를 통하여 전기적으로 연결되고, 상기 제1반도체칩(300)의 제1본딩패드(320)는 제1기판(302)의 가장자리 영역에 형성된 제1패드(318)와 제1금속와이어를(304) 통하여 전기적으로 연결된다.3 is a plan view illustrating an electrical connection between a semiconductor chip and a substrate on which pad rearrangement is performed in a lower package according to an exemplary embodiment of the present invention. As illustrated, the upper surface of the first semiconductor chip 300 on which pad rearrangement is performed is shown. The connection pad 310 formed is electrically connected to the plurality of first bonding pads 320 formed at the edge region of the first semiconductor chip 300 through the redistribution 310a, and the first semiconductor chip 300 The first bonding pad 320 is electrically connected to the first pad 318 and the first metal wire 304 formed at the edge region of the first substrate 302.

도 4a 내지 도 4e는 본 발명의 실시예에 따른 스택 패키지의 제조 과정을 설명하기 위한 공정별 단면도이다.4A through 4E are cross-sectional views illustrating processes of manufacturing a stack package according to an exemplary embodiment of the present invention.

도 4a를 참조하면, 상면의 가장자리 영역에 다수의 제1패드(418)가 구비되고, 하면에 다수의 제1볼랜드(미도시)가 구비된 제1기판(402) 상에, 패드 재배열이 이루어져 있고, 이에 따라, 상면의 가장자리 영역에 구비된 다수의 제1본딩패드(420)와 전기적으로 연결되는 접속패턴(410)을 구비한 제1반도체칩(400)을 접착제(미도시)를 매개로 부착시킨다.Referring to FIG. 4A, a rearrangement of pads may be performed on a first substrate 402 having a plurality of first pads 418 disposed at an edge of an upper surface thereof, and a plurality of first borland (not shown) disposed at a lower surface thereof. Accordingly, the first semiconductor chip 400 having a connection pattern 410 electrically connected to the plurality of first bonding pads 420 provided at the edge region of the upper surface is formed by using an adhesive (not shown). To be attached.

그런다음, 상기 제1본딩패드(420)와 제1패드(418)를 제1금속와이어(404)로 전기적 연결을 시킨 후, 상기 제1금속와이어(404) 및 제1반도체 칩(400)을 포함한 제1기판(402)의 상면을 몰딩 공정을 통해 제1봉지제(406)로 밀봉한다.Thereafter, the first bonding pad 420 and the first pad 418 are electrically connected to the first metal wire 404, and then the first metal wire 404 and the first semiconductor chip 400 are connected to each other. The upper surface of the first substrate 402 is sealed with the first encapsulant 406 through a molding process.

다음으로, 상기 제1기판(402) 하면의 볼랜드(미도시)에 다수의 제1솔더볼(408)을 부착한다. Next, a plurality of first solder balls 408 are attached to a ball land (not shown) on the bottom surface of the first substrate 402.

도 4b를 참조하면, 상기 제1반도체 칩(400)의 접속패드(410)들이 외부로 노출되도록 상기 제1봉지제(406) 부분에 레이져 드릴링(Laser drilling) 공정을 이용하여 홀(T)을 형성한다.Referring to FIG. 4B, holes T are formed in a portion of the first encapsulant 406 using a laser drilling process so that the connection pads 410 of the first semiconductor chip 400 are exposed to the outside. Form.

도 4c를 참조하면, 상기 홀(T)이 형성되어 있는 제1봉지제(406) 상에 상기 홀 및 이에 인접한 봉지제 부분을 노출시키는 마스크패턴(미도시)을 형성한 후, 도금 공정을 실시하여 상기 홀(T) 및 이에 인접한 제1봉지제(406) 부분에 구리(Cu)로 이루어진 연결 패턴(412)을 형성한다.Referring to FIG. 4C, after forming a mask pattern (not shown) exposing the hole and the portion of the encapsulant adjacent to the first encapsulant 406 on which the hole T is formed, a plating process is performed. As a result, a connection pattern 412 made of copper Cu is formed in the hole T and the portion of the first encapsulant 406 adjacent thereto.

도 4d를 참조하면, 상기 마스크패턴이 제거된 상태에서 상기 연결 패턴(412) 상에 상부 패키지와 하부 패키지를 전기적으로 연결시키기 위한 제2솔더볼을 부착시켜, 이를 통해, 하부 웨이퍼 레벨 패키지(A)를 제조한다. Referring to FIG. 4D, a second solder ball for electrically connecting an upper package and a lower package is attached to the connection pattern 412 in a state where the mask pattern is removed, thereby lower wafer level package A To prepare.

도 4e를 참조하면, 상면의 가장자리 영역에 다수의 제2패드(418b)가 구비되고, 하면에 상기 하부 패키지의 제2솔더볼(408a)과 부착되는 다수의 제2볼랜드(미도시)가 구비된 제2기판(402b) 상에 상면의 가장자리 영역에 구비된 다수의 제2본딩패드(420b)가 구비된 제2반도체칩(400b)이 부착되어 있고, 제2본딩패드(420b)와 제2패드(418b)를 전기적으로 연결하는 제2금속와이어(406b)가 구비되어 있고, 상기 제2금속와이어(406b) 및 제2반도체 칩(400b)을 포함한 제2기판(402b)의 상면을 제2 봉지제(406b)로 밀봉하여 제조된 상부 웨이퍼 레벨 패키지(B)를 마련한 후, 상기 상부 웨이퍼 레벨 패키지(B)를 상기 제2솔더볼(408b) 상에 실장시켜 본 발명의 실시예에 따른 스택 패키지를 제조한다.Referring to FIG. 4E, a plurality of second pads 418b are provided in an edge region of an upper surface thereof, and a plurality of second borlands (not shown) attached to the second solder balls 408a of the lower package are provided on the lower surface thereof. On the second substrate 402b, a second semiconductor chip 400b having a plurality of second bonding pads 420b provided on the edge region of the upper surface is attached, and the second bonding pad 420b and the second pad are attached. A second metal wire 406b is provided to electrically connect the 418b, and a second encapsulation is formed on the top surface of the second substrate 402b including the second metal wire 406b and the second semiconductor chip 400b. After preparing the upper wafer level package B manufactured by sealing with the 406b, the upper wafer level package B is mounted on the second solder ball 408b to prepare a stack package according to an embodiment of the present invention. Manufacture.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명에서는 하부 패키지를 구성하고 있는 반도체 칩 상에 패드 재배열을 통해 형성된 접속 패드 상에 구리로 이루어진 연결패턴의 형성으로 인해, 하부 패키지와 상부 패키지 간이 전기적으로 연결되는 솔더볼이 기판의 가장자리에만 형성해야 한다는 제약에서 벗어날 수 있어 설계의 자유도를 향상시킬 수 있다.As described above, in the present invention, due to the formation of a connection pattern made of copper on the connection pad formed by rearranging the pads on the semiconductor chip constituting the lower package, the solder ball is electrically connected between the lower package and the upper package. Freedom from the constraint of having to be formed only at the edge of the substrate can improve the freedom of design.

또한, 본 발명은, 상기 솔더볼이 연결패턴 각각에 형성됨에 따라, 스택된 패키지들 간의 전기적 연결 및 중앙부 공간을 포함하여 고르게 지지해줄 수단이 형성되어 스택 패키지를 구현하기 위하여 별도의 전기적 및 물리적 연결 수단을 사용할 필요가 없고, 간단한 공정으로 패키지 온 패키지 타입의 스택 패키지를 제조할 수 있으며, 패키지 신뢰성 테스트에서 우수한 결과를 얻을 수 있다. In addition, according to the present invention, as the solder balls are formed in each of the connection patterns, a means for evenly supporting an electrical connection between the stacked packages and a central space is formed, so that separate electrical and physical connection means are implemented to implement the stack package. There is no need to use, it is possible to manufacture a stack-on package type stack package in a simple process, and excellent results are obtained in the package reliability test.

Claims (11)

삭제delete 삭제delete 삭제delete 삭제delete 삭제delete 상면의 가장자리 영역에 다수의 제1패드가 구비되고, 하면에 다수의 제1볼랜드가 구비된 제1기판을 준비하는 단계;Preparing a first substrate having a plurality of first pads in an edge region of an upper surface thereof, and having a plurality of first ball lands in a lower surface thereof; 상기 제1기판 상에 패드 재배열로 상면의 가장자리 영역에 구비된 다수의 제1본딩패드와 전기적으로 연결되는 접속패턴을 구비한 제1반도체칩을 접착제를 매개로 부착시키는 단계; Attaching a first semiconductor chip having a connection pattern electrically connected to a plurality of first bonding pads provided in an edge region of an upper surface by rearranging pads on the first substrate through an adhesive; 상기 제1본딩패드와 제1패드를 제1금속와이어로 전기적 연결을 시키는 단계;Electrically connecting the first bonding pad and the first pad to a first metal wire; 상기 제1금속와이어 및 제1반도체 칩을 포함한 제1기판의 상면을 제1봉지제로 봉지하는 단계;Encapsulating an upper surface of the first substrate including the first metal wire and the first semiconductor chip with a first encapsulant; 상기 제1기판 하면의 볼랜드에 다수의 제1솔더볼을 부착시켜 하부 웨이퍼 레벨 패키지를 형성하는 단계;Attaching a plurality of first solder balls to the ball lands on the lower surface of the first substrate to form a lower wafer level package; 상기 제1반도체 칩의 접속패드들이 외부로 노출되도록 상기 제1봉지제 부분에 다수의 홀을 형성하는 단계;Forming a plurality of holes in the portion of the first encapsulant such that the connection pads of the first semiconductor chip are exposed to the outside; 상기 홀 및 이에 인접한 제1봉지제 부분에 연결 패턴을 형성하는 단계;Forming a connection pattern in the hole and a portion of the first encapsulant adjacent thereto; 상기 연결 패턴 상에 제2솔더볼을 부착시키는 단계;Attaching a second solder ball on the connection pattern; 상기 하부 웨이퍼 레벨 패키지의 제2솔더볼 상에 상면의 가장자리 영역에 다수의 제2패드가 구비되고, 하면에 상기 하부 패키지의 제2솔더볼과 부착되는 다수의 제2볼랜드가 구비된 제2기판 상에 상면의 가장자리 영역에 구비된 다수의 제2본딩패드가 구비된 제2반도체칩이 부착되어 있고, 제2본딩패드와 제2패드를 전기적으로 연결하는 제2금속와이어가 구비되어 있고, 상기 제2금속와이어 및 제2반도체 칩을 포함한 제2기판의 상면을 제2봉지제로 밀봉하여 제조된 상부 웨이퍼 레벨 패키지를 실장시키는 단계;를On the second substrate provided with a plurality of second pads on the upper edge area of the lower solder level package of the lower wafer level package, and having a plurality of second borland attached to the lower solder balls of the lower package. A second semiconductor chip having a plurality of second bonding pads attached to an edge region of the upper surface is attached, and a second metal wire electrically connecting the second bonding pad and the second pad is provided. Mounting an upper wafer level package manufactured by sealing an upper surface of a second substrate including a metal wire and a second semiconductor chip with a second encapsulant; 포함하는 것을 특징으로 하는 스택 패키지의 제조 방법.Method for producing a stack package, characterized in that it comprises a. 제 6 항에 있어서,The method of claim 6, 상기 홀은 레이져 드릴링(Laser drilling) 공정으로 형성되는 것을 특징으로 하는 스택 패키지의 제조 방법.The hole is a method of manufacturing a stack package, characterized in that formed by a laser drilling (Laser drilling) process. 제 6 항에 있어서,The method of claim 6, 상기 연결패턴은 도금 공정으로 형성되는 것을 특징으로 하는 스택 패키지의 제조 방법.The connection pattern is a manufacturing method of a stack package, characterized in that formed by a plating process. 제 6 항에 있어서,The method of claim 6, 상기 연결패턴은 구리(Cu)로 형성되는 것을 특징으로 하는 스택 패키지의 제조 방법.The connection pattern is a method of manufacturing a stack package, characterized in that formed of copper (Cu). 제 6 항에 있어서, The method of claim 6, 상기 하부 패키지와 상부 패키지는 동일 타입으로 형성된 것을 특징으로 하는 스택 패키지의 제조 방법.The lower package and the upper package is a manufacturing method of the stack package, characterized in that formed in the same type. 제 6 항에 있어서, The method of claim 6, 상기 하부 패키지와 상부 패키지는 서로 다른 타입으로 형성된 것을 특징으로 하는 스택 패키지의 제조 방법.The lower package and the upper package is a manufacturing method of a stack package, characterized in that formed in different types.
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