CN117246976B - On-chip integrated structure and forming method thereof - Google Patents
On-chip integrated structure and forming method thereof Download PDFInfo
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- CN117246976B CN117246976B CN202311533163.1A CN202311533163A CN117246976B CN 117246976 B CN117246976 B CN 117246976B CN 202311533163 A CN202311533163 A CN 202311533163A CN 117246976 B CN117246976 B CN 117246976B
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 348
- 229910052751 metal Inorganic materials 0.000 claims abstract description 154
- 239000002184 metal Substances 0.000 claims abstract description 154
- 239000000463 material Substances 0.000 claims description 39
- 238000007789 sealing Methods 0.000 claims description 24
- 238000004544 sputter deposition Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 210000001503 joint Anatomy 0.000 claims description 5
- 238000003475 lamination Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 239000011324 bead Substances 0.000 claims 1
- 238000012545 processing Methods 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000012530 fluid Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000017525 heat dissipation Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00119—Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
Abstract
The present disclosure relates to on-die integrated structures and methods of forming the same. The method for forming the on-chip integrated structure comprises the following steps: forming a keyhole structure on the first substrate, wherein the step of forming the keyhole structure comprises the following steps: forming a bonding groove extending into the substrate from the bonding surface of the substrate; forming a plurality of bonding holes extending from the bonding groove into the substrate; forming a metal layer structure sunk in the bonding groove; forming a convex latch structure on the second substrate, wherein the step of forming the convex latch structure comprises the following steps: forming a metal pad laminated on the substrate, wherein the periphery of the metal pad is matched with the groove wall of the corresponding bonding groove; forming a plurality of metal bumps laminated on the metal pad, wherein the positions of the metal bumps at the metal pad are matched with the positions of bonding holes in the corresponding bonding grooves; forming a runner structure extending into the substrate; abutting the metal pads into the bonding grooves; and bonding the latch structure to the keyhole structure. The method is simple to execute. In addition, the method can firmly and reliably connect two substrates.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to an on-die integrated structure and a method of forming the same.
Background
With the rapid development of chip technology, the influence of high integration and high heat dissipation of circuit integration is getting more and more attention. The heat radiation structure is added to the chip or the electronic component in operation, so that the heat generated by the chip or the electronic component is released by the heat radiation structure, and the chip or the electronic component is ensured to work in a stable state.
The micro-channel heat radiation plate is a liquid circulation heat radiation device with the channel size at the micron level or the sub-millimeter level, and can take away heat generated by the operation of a chip or an electronic component through liquid flow. The micro flow channel heat dissipation plate may be formed as follows: and etching a channel on the surface of one wafer substrate, bonding the cover plate and the etched wafer substrate together, and reserving a water inlet and a water outlet on two sides respectively.
Common cover plates are silicon wafers, glass sheets and the like. The bonding mode of the glass sheet and the silicon-based micro-channel substrate is generally anodic bonding, the glass sheet and the silicon-based substrate are required to be bonded by applying heat and voltage, and the micro-channel heat dissipation plate manufactured in this way has weakened bonding effect and reduced air tightness along with long service time. The silicon wafer can be directly bonded on the silicon-based micro-channel substrate, and bonding between the silicon wafers is realized by applying high temperature (more than 800 ℃). The bonding strength of the direct bonding of silicon and silicon can reach more than 12MPa, but the bonding process has extremely high requirements on temperature conditions, flatness and cleanliness of the surface of the silicon wafer and the like.
At present, the manufacturing process of the micro-channel cooling plate is difficult.
Disclosure of Invention
Accordingly, it is necessary to provide an on-die integrated structure and a method for forming the same, which address the problem of difficulty in manufacturing the micro flow channel heat sink.
Embodiments of the present disclosure provide a method for forming an integrated structure on a die, the method comprising: forming a keyhole structure on a first substrate of the two substrates, the step of forming the keyhole structure comprising: forming a bonding groove extending into the substrate from the bonding surface of the substrate; forming a plurality of bonding holes extending from the bonding groove into the substrate; forming a metal layer structure sunk in the bonding groove; forming a latch structure on a second substrate of the two substrates, the step of forming the latch structure comprising: forming a metal pad laminated on the substrate, wherein the periphery of the metal pad is matched with the groove wall of the corresponding bonding groove; forming a plurality of metal bumps laminated on the metal pad, wherein the positions of the metal bumps at the metal pad are matched with the positions of bonding holes in the corresponding bonding grooves; forming a runner structure extending into the substrate on at least one of the two substrates; abutting the metal pads into the bonding grooves; and bonding the latch structure to the keyhole structure.
The method for forming the on-chip integrated structure provided by the embodiment of the disclosure is simple to execute. In addition, the method can firmly and reliably connect two substrates.
In some embodiments, the method for forming an integrated structure on a die further comprises: forming other convex latch structures on the first substrate; and forming other keyhole structures on the second substrate.
The arrangement is favorable for accurate matching and improves the firmness of the connection of the first substrate and the second substrate.
In some embodiments, the step of bonding the latch structure to the keyhole structure comprises: applying pressure to the first substrate and the second substrate in the lamination direction; the first substrate and the second substrate are heated, wherein the first bonding temperature is 350 ℃ to 450 ℃.
So set up, can realize the bonding of protruding bolt structure and lockhole structure.
In some embodiments, in the step of bonding the male latch structure to the female latch structure, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min.
So set up, can guarantee bonding strength, ensure on the crystal integrated structure's performance and life.
In some embodiments, the height of the metal pad is equal to the depth of the metal layer structure in the bonding groove, and the inner diameter of the bonding hole is larger than the outer diameter of the metal bump; the inner diameter of the bonding groove is millimeter level or micron level, the depth of the bonding groove is micron level or nanometer level, the inner diameter of the bonding hole is micron level, and the depth of the bonding hole is nanometer level.
So set up, compact structure, size are little, when guaranteeing bonding strength, can guarantee the accuracy nature of bonding, and then first base plate and second base plate can be accurately aligned.
In some embodiments, the step of forming a metal layer structure includes: sputtering to form a first connecting layer, wherein the material of the first connecting layer comprises titanium; and sputtering to form a first bonding layer laminated on the first connecting layer; the step of forming the metal pad includes: sputtering to form a second connecting layer, wherein the material of the second connecting layer comprises titanium; and sputtering to form a second bonding layer laminated on the second connecting layer, wherein the material of the second bonding layer, the material of the metal bump and the material of the first bonding layer comprise the same metal material, and the metal material comprises copper, gold, nickel or platinum.
So set up, can promote bonding strength, can reduce the bonding degree of difficulty through homogeneous metal material in addition.
In some embodiments, the runner structure is located at the bonding surface, the substrate provided with the runner structure has a working surface facing away from the bonding surface, the method further comprising: forming a mounting groove extending into the substrate from the working surface for at least one substrate provided with a flow channel structure; mounting the chip in the mounting groove; and forming a dielectric layer or an interconnection layer covering the chip.
The arrangement is convenient for processing and manufacturing the substrate, and the chip can be well radiated by the flow channel structure during working.
In some embodiments, a conductive channel is formed through the substrate, wherein the conductive channel in the substrate with the runner structure is electrically connected to the chip; and butting and electrically connecting the conductive channels of the first substrate with the conductive channels of the second substrate.
By the arrangement, the utilization modes of the substrate can be enriched, and more power connection modes are realized by the on-chip integrated structure.
In some embodiments, the method for forming an integrated structure on a die further comprises: etching a bonding surface of one of the two substrates to form a sealing groove; forming a first metal seal layer recessed within the seal groove; forming a second metal seal layer laminated on the other substrate; abutting the second metal seal layer within the seal groove; and bonding a second metal sealing layer with the first metal sealing layer before the step of bonding the convex latch structure with the lock hole structure to obtain a sealing structure surrounding the runner structure along the bonding surface of the substrate, wherein the second bonding temperature is 380 ℃, and the second bonding pressure is 10% 4 Pa to 10 5 Pa, and vacuum degree 0.1Pa.
By the arrangement, the isolation capability of the flow channel structure and the circuit in the on-chip integrated structure can be improved, and the connection strength between the substrates can also be improved.
In some embodiments, a method for forming an integrated structure on a die, further comprising: forming an alignment mark on a bonding surface of one of the two substrates; forming an alignment section on the periphery of the other of the two substrates, wherein the alignment section is used for aligning with the alignment mark so as to enable the metal pad to be butted in the bonding groove; and bonding or hermetically packaging the bonding surface of the first substrate and the bonding surface of the second substrate.
By the arrangement, the alignment accuracy of the first substrate and the second substrate can be improved, and the first substrate and the second substrate can be well distinguished.
The disclosed embodiments also provide an on-die integrated structure, the on-die integrated structure comprising: a first substrate having a bonding groove extending from a first bonding surface of the first substrate into the first substrate, and a plurality of bonding holes extending from the bonding groove into the first substrate; the latch structure is filled in the bonding groove and the bonding hole; and a second substrate laminated on one side of the first substrate where the bonding groove is provided, the second substrate being connected to the first substrate by a latch structure, at least one of the second substrate and the first substrate being provided with a flow path structure.
The on-chip integrated structure provided by the embodiment of the disclosure comprises a first substrate and a second substrate which are connected together, and each substrate can be subjected to heat dissipation through a flow channel structure. The on-chip integrated structure has long service life and simple manufacture.
Illustratively, the on-die integrated structure is obtained by a method for forming an on-die integrated structure as previously described.
By the arrangement, a firm and reliable latch structure can be realized, and the connection strength of the first substrate and the second substrate is ensured.
Drawings
FIG. 1 is a schematic flow diagram of a method for forming an on-die integrated structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic flow chart of processing a first substrate;
FIG. 3 is a schematic diagram of a first substrate structure after forming a metal layer structure;
FIG. 4 is an enlarged view of FIG. 3 at A;
FIG. 5 is a schematic view of the first substrate structure after forming the latch structure;
FIG. 6 is an enlarged view at B in FIG. 5;
fig. 7 is a schematic structural view of a first substrate structure of an embodiment of the present disclosure;
FIG. 8 is a schematic top view of a first substrate structure of an embodiment of the present disclosure;
FIG. 9 is a schematic top view of a male latch structure;
FIG. 10 is a schematic flow chart of processing a second substrate in an embodiment of the present disclosure;
FIG. 11 is a schematic top view of a second substrate structure of an embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a bonding step in a method for forming an integrated structure on a die according to an embodiment of the present disclosure;
FIG. 13 is a schematic top view of an on-die integrated structure of an embodiment of the present disclosure;
FIG. 14 is a schematic flow chart of processing a first substrate in an embodiment of the present disclosure;
FIG. 15 is a schematic flow chart of a process second substrate and bonding step in an embodiment of the present disclosure;
FIG. 16 is a schematic diagram of a bonding step in a method for forming an integrated structure on a die according to an embodiment of the present disclosure;
FIG. 17 is a schematic flow chart of processing a first substrate in an embodiment of the disclosure;
FIG. 18 is a schematic top view of a first substrate structure of an embodiment of the present disclosure;
FIG. 19 is a schematic flow chart of a process second substrate and bonding step in an embodiment of the present disclosure;
FIG. 20 is a schematic diagram of a bonding step in a method for forming an integrated structure on a die according to an embodiment of the present disclosure;
FIG. 21 is a schematic structural view of an on-die integrated structure according to an embodiment of the present disclosure;
fig. 22 is a schematic structural diagram of an on-die integrated structure according to an embodiment of the present disclosure.
Reference numerals illustrate: 10. a chip; 100. a first substrate; 101. a first bonding surface; 102. a working surface; 110. a dielectric layer; 120. an interconnect layer;
1. A mounting groove; 2. a marking groove; 21. an alignment mark; 3. a keyhole structure; 31. a bonding groove; 32. a bonding hole; 33. a metal layer structure; 331. a first connection layer; 332. a first bonding layer; 4. a flow channel structure; 41. a first fluid port; 42. a second fluid port; 5. a male latch structure; 51. a metal pad; 511. a second connection layer; 512. a second bonding layer; 52. metal protruding points; 6. a first metal seal layer; 7. a second metal seal layer; 8. a conductive path; 9. a latch structure; 11. a sealing structure;
200. a second substrate; 201. a second bonding surface; 202. aligning the tangential plane; 300. a third substrate; 301. auxiliary alignment of the tangential plane; 400. a fourth substrate; 1000. an on-die integrated structure.
Detailed Description
In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, a detailed description of specific embodiments of the present disclosure is provided below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. The disclosed embodiments may be embodied in many other forms other than described herein and similar modifications may be made by those skilled in the art without departing from the spirit of the disclosed embodiments, so that the disclosed embodiments are not limited to the specific examples of embodiments described below.
In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the embodiments of the present disclosure and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present disclosure.
In the presently disclosed embodiments, unless expressly stated and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intermediary. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. For example, the first substrate may also be referred to as a second substrate, and the second substrate may also be referred to as a first substrate. In the description of the embodiments of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly specified otherwise.
In the presently disclosed embodiments, the terms "connected," "connected," and the like are to be construed broadly and, unless otherwise specifically indicated and defined, as being either fixedly connected, detachably connected, or integrally formed, for example; can be flexible connection or rigid connection along at least one direction; can be mechanically or electrically connected; either directly, indirectly, through intermediaries, or both, or in which case the intermediaries are present, or in which case the two elements are in communication or in which case they interact, unless explicitly stated otherwise. The terms "mounted," "disposed," "secured," and the like may be construed broadly as connected. The specific meaning of the above terms in the embodiments of the present disclosure may be understood by those of ordinary skill in the art according to specific circumstances.
As used herein, the terms "layer," "region" and "regions" refer to portions of material that include regions having a certain thickness. The layers can extend horizontally, vertically and/or along a tapered surface. The layer can be a region of uniform or non-uniform continuous structure, whose thickness perpendicular to the direction of extension may be no greater than the thickness of the continuous structure. The layers can include multiple layers, either stacked or discretely extending. The various regions in the figures, the shapes of the layers and their relative sizes and positional relationships are exemplary only, as may be subject to variations due to manufacturing tolerances or technical limitations, and may be adjusted to actual requirements.
Referring to fig. 1, fig. 1 illustrates a method for forming an integrated structure on a die in an embodiment of the disclosure. The method S100 for forming an on-die integrated structure provided in the embodiments of the present disclosure includes steps S110 to S150. Methods for forming integrated structures on a die provided by embodiments of the present disclosure are described in detail in connection with fig. 2-13.
The method S100 for forming an integrated structure on a die may include: and processing the substrate. For example, the first substrate 100 is processed and the second substrate 200 is processed.
Fig. 2 shows a step of processing the first substrate 100. In some embodiments, the first substrate 100 has a first bonding surface 101 and a working surface 102 facing away from each other in the Z-axis direction, thereby forming a mounting groove 1 extending from the working surface 102 into the first substrate 100. Illustratively, the method S100 further comprises: a marking groove 2 extending from the first bonding surface 101 into the first substrate 100 is formed. The mounting groove 1 and the marking groove 2 may be formed by etching, respectively.
Referring to fig. 2 and 3, step S110 includes: the first substrate 100 of the two substrates forms a keyhole structure 3. Specifically, the step of forming the keyhole structure 3 on the first substrate 100 includes: forming a bonding groove 31 extending into the first substrate 100 from the first bonding surface of the first substrate 100; forming a plurality of bonding holes 32 extending from the bonding grooves 31 into the first substrate 100; and forming a metal layer structure 33 depressed in the bonding groove 31.
As shown in fig. 2, the runner structure 4 extending from the first bonding surface 101 into the first substrate 100 may be formed before the metal layer structure 33 is formed. Further, step S130 includes: the runner structure 4 extending into the substrate is formed for at least one of the two substrates.
Referring to fig. 3 and 4, in some embodiments, the step of forming the metal layer structure 33 may include: sputtering to form a first connection layer 331; and sputtering to form a first bonding layer 332, the first bonding layer 332 being laminated on the first connection layer 331. A first connection layer 331 and a first bonding layer 332 are deposited in the bonding groove 31, and the top surface of the first bonding layer 332 is lower than the first bonding surface 101; a first connection layer 331 and a first bonding layer 332 may be deposited within each bonding hole 32.
Illustratively, a silicon oxide material may be sputtered into the mark trenches 2 to form the alignment marks 21. The alignment mark 21 is located on the outer side of the keyhole structure 3 in the radial direction of the first substrate 100.
The keyhole structure 3 formed at the first substrate 100 is used to mate with the stud structure 5 at the second substrate 200 (fig. 10). Referring to fig. 5 and 6, exemplarily, a latch structure 5 may also be formed at the first substrate 100, and then the latch structure 5 at the first substrate 100 is used to match the latch hole structure 3 at the second substrate 200.
The step of forming the latch structure 5 connected to the first substrate 100 may include: forming a metal pad 51 laminated on the first substrate 100, wherein an outer circumference of the metal pad 51 is matched with a groove wall of the corresponding bonding groove 31 at the second substrate 200; a plurality of metal bumps 52 laminated on the metal pad 51 are formed, and the positions of the metal bumps 52 at the metal pad 51 are matched with the positions of the bonding holes 32 in the corresponding bonding grooves 31. Illustratively, the step of forming the metal pad 51 includes: sputtering to form a second connection layer 511; the second bonding layer 512 stacked on the second connection layer 511 is formed by sputtering.
As shown in fig. 7, the chip 10 may be mounted in the mounting groove 1. The chip 10 may also be configured as other passive devices. Illustratively, a dielectric layer 110 is formed on the side of the working surface 102 that covers the chip 10. The material of dielectric layer 110 may include silicon dioxide.
Fig. 8 shows a schematic top view of a first substrate structure. The first substrate structure includes a first substrate 100 and additional structures connected to the first substrate 100.
The first bonding surface 101 of the first substrate 100 is provided with at least two alignment marks 21, the two alignment marks 21 are spaced apart along the X-axis direction, and the two alignment marks 21 are respectively close to one end of the first substrate 100 and spaced apart. The first bonding surface 101 in fig. 8 is parallel to the XY plane, and the layout manner implemented in the X-axis direction or in the Y-axis direction in fig. 8 is an example.
The flow channel structure 4 comprises a first flow channel opening 41 and a second flow channel opening 42. The flow passage structure 4 extends along the X-axis direction to protrude from the right alignment mark 21, and the first flow passage 41 is positioned on the right side of the alignment mark 21; the flow channel structure 4 extends along the X-axis direction and protrudes from the left alignment mark 21, and the second flow channel opening 42 is located on the left side of the alignment mark 21.
The number of the lock hole structures 3 and the protruding latch structures 5 can be set according to the requirement, and the arrangement positions can be configured according to the design structure. The size and layout of the different keyhole structures 3 may be different; the size and layout of the different latch structures 5 may be different. The keyhole structure 3 and the latch structure 5 may surround the runner structure 4, and the runner structure 4 is disposed substantially centrally on the first substrate 100.
Referring to fig. 9, exemplary stud structure 5 includes a plurality of metal bumps 52 laminated to a second bonding layer 512. The size, number and location of the metal bumps 52 may be set as desired, for example, eight metal bumps 52 are shown in fig. 9 evenly wrapped around. It is understood that eight corresponding key holes 32 are provided in the key grooves 31 of the lock hole structure 3 corresponding to the latch structure 5.
Referring to fig. 10, fig. 10 illustrates a step of processing the second substrate 200. The second substrate 200 may have a second bonding surface 201, and an alignment cut surface 202 is disposed on an outer periphery of the second substrate 200, for example, two alignment cut surfaces 202 are disposed at two ends along the X-axis direction.
Illustratively, a keyhole feature 3 may be formed in the second substrate 200, the keyhole feature 3 at the second substrate 200 being configured to mate with the latch feature 5 at the first substrate 100. Specifically, a bonding groove 31 extending from the second bonding surface 201 into the second substrate 200 may be formed; forming a bonding hole 32 extending from the bonding groove 31 into the second substrate 200; and forming a metal layer structure 33 recessed in the bonding groove 31.
Step S120 includes: the second substrate 200 of the two substrates forms a latch structure 5. The step of forming the latch structure 5 may refer to the step of forming the latch structure 5 on the first substrate 100, and will not be described again.
Referring to fig. 11, at the second bonding surface 201 of the second substrate 200, the arrangement of the latch structures 5 corresponds to the latch hole structures 3 of the first substrate 100; the metal layer structure 33 in the keyhole structure 3 is disposed corresponding to the stud structure 5 of the first substrate 100. Illustratively, there may be a one-to-one correspondence; it is also possible that for example two stud structures correspond to one keyhole structure 3, the number of bond holes 32 being for example twice the number of metal bumps 52.
Referring to fig. 12 and 13, in step S140, the metal pad 51 is butted into the bonding groove 31. Illustratively, the second substrate 200 and the first substrate 100 can be accurately aligned in a desired manner using the alignment cut 202 and the alignment mark 21. The second substrate 200 may substantially cover the flow channel structure 4. The first fluid passage opening 41 and the second fluid passage opening 42 respectively protrude from the alignment section 202 of the second substrate 200, one of the first fluid passage opening 41 and the second fluid passage opening 42 serves as a water inlet, and the other one serves as a water outlet, so that heat exchange is performed.
Step S150, bonding the latch structure 5 to the lock hole structure 3. The male latch structure 5 and the keyhole structure 3 achieve metal bonding.
The method for forming the on-chip integrated structure is easy to execute, the process requirements of the convex latch structure and the keyhole structure are lower than those of silicon-silicon direct bonding, and meanwhile, the convex latch structure and the keyhole structure realize bonding with high strength and long service life.
In some embodiments, for each pair of the latch structure 5 and the keyhole structure 3, the height of the configurable metal pad 51 is equal to the depth of the metal layer structure 33 within the bonding groove 31, thus ensuring that the second bonding layer 512 of the metal pad 51 can contact the first bonding layer 332 of the metal layer structure 33. The height of the metal bump 52 may be substantially equal to the depth of the bond hole 32, thus ensuring that the metal bump 52 contacts the first bonding layer 332 within the bond hole 32. The bonding holes 32 may also be configured to have an inner diameter greater than the outer diameter of the metal bumps 52 to relieve minor thermal expansion of the metal bonding process.
The cross-sectional shape of the bonding hole 32 may be configured as a circle, a square, or the like, and the outer diameter may be referred to as an circumscribed circle diameter, and the inner diameter may be referred to as an inscribed circle diameter. Illustratively, the bond hole 32 is square, and may have a length or width in the XY-plane that is greater than the length and width of the square metal bump 52.
Illustratively, the bonding groove 31 has an inner diameter on the order of millimeters or micrometers, the bonding groove 31 has a depth on the order of micrometers or nanometers, the bonding hole 32 has an inner diameter on the order of micrometers, and the bonding hole 32 has a depth on the order of nanometers. The latch structure 5 and the keyhole structure 3 are small in size and are suitable for forming on a substrate with compact space. By means of the arrangement of the plurality of bonding holes, the convex latch structure 5 and the lock hole structure 3 have larger contact areas, and stronger bonding strength is achieved.
In one embodiment, referring to the on-die integrated structure 1000 shown in fig. 12, the first substrate 100 is a 4-inch wafer, the etching depth of the mark trench 2 is 100nm, the length dimension is 200 μm, the width dimension is 100 μm, and the alignment mark 21 can fill up the mark trench 2. The depth of the channel structures 4 is 150 μm and the width of each strip may be 1mm. The bonding groove 31 had an etching depth of 2 μm and a square shape with a side length of 1mm. The bonding hole 32 was etched to a depth of 2 μm and formed in a square shape having a side length of 100. Mu.m. The thickness of each metal layer structure 33 is 1 μm. The metal pad 51 has a thickness of 1 μm and a square shape with a side length of 1mm. The metal bump 52 has a thickness of 1 μm and a square shape with a side length of 80 μm. In addition to the chip 10, a resistor, capacitor or other sensor device may be mounted in the mounting slot 1.
Illustratively, the material of the first connection layer 331 includes titanium; the material of the second connection layer 511 includes titanium. Titanium material can achieve good connection to the substrate. The material of the second bonding layer 512, the material of the metal bump 52 and the material of the first bonding layer 332 comprise the same metal material, which comprises copper, tin, gold, nickel or platinum, such as copper. The same metal material can ensure bonding strength.
In some embodiments, the step of bonding the latch structure 5 to the keyhole structure 3 comprises: applying pressure to the first substrate 100 and the second substrate 200 in the lamination direction (Z-axis direction); the first substrate 100 and the second substrate 200 are heated, wherein the first bonding temperature is 350 ℃ to 450 ℃. Illustratively, the material of the second bonding layer 512, the material of the metal bump 52 and the material of the first bonding layer 332 are copper, and when bonding, the bonding may be performed by heating under pressure, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min, so that copper-copper bonding may be achieved.
In some embodiments, the alignment mark 21 is formed on the bonding surface of one of the two substrates; an alignment cut surface 202 is formed at the outer periphery of the other of the two substrates, the alignment cut surface 202 being for alignment with the alignment mark 21 so that the metal pad 51 is butted in the bonding groove 31. Then, the first bonding surface 101 of the first substrate 100 and the second bonding surface 201 of the second substrate 200 are bonded or hermetically encapsulated, so that the connection strength and the service life of the first substrate 100 and the second substrate 200 can be further ensured.
Illustratively, after copper-copper bonding is achieved, the temperature is reduced to 300 ℃; the bonding pressure 700N is applied by applying the voltage 1000V, and the surface bonding of the second substrate 200 of glass material and the first substrate 100 of silicon material can be completed. Optionally, the material of the substrate includes glass, semiconductor material, and the like. Illustratively, the material of the substrate is BF33.
Referring to fig. 14 and 15, although the method for forming the on-die integrated structure in the foregoing embodiment includes: forming further latch structures 5 on the first substrate 100; and the other steps of forming the keyhole structures 3 on the second substrate 200, but in this embodiment, it is slightly different, that only the keyhole structures 3 may be formed on the first substrate 100, and only the latch structures 5 may be formed on the second substrate 200.
Referring to fig. 14, the processing steps performed on the first substrate 100 may include: forming a mounting groove 1, forming a mark groove 2, forming a keyhole structure 3 including a metal layer structure 33, forming a runner structure 4, forming an alignment mark 21, mounting a chip 10, and forming a dielectric layer 110.
Referring to fig. 15, the processing steps performed on the second substrate 200 may include: an alignment cut 202 is obtained, forming the stud structure 5. The latch structure 5 can then be docked and bonded within the keyhole structure 3.
The first substrate 100 is illustratively a 4 inch wafer, the etched depth of the mark grooves 2 is 100nm, the length dimension is 200 μm, and the width dimension is 100 μm. The depth of the channel structures 4 is 150 μm and the width of each strip may be 1mm. The bonding groove 31 had an etching depth of 1 μm and a square shape with a side length of 1mm. The bonding hole 32 was etched to a depth of 1 μm and formed in a square shape having a side length of 100. Mu.m. The thickness of each metal layer structure 33 is 0.5 μm. The metal pad 51 has a thickness of 0.5 μm and a square shape with a side length of 1mm. The metal bump 52 has a thickness of 0.5 μm and a square shape with a side length of 80 μm. As can be seen, the outer periphery of the metal pad 51 can abut against the side wall of the bonding groove 31; illustratively, the metal bump 52 may also contact at least a portion of the sidewall of the bond hole 32.
Illustratively, the material of the second bonding layer 512, the material of the metal bump 52 and the material of the first bonding layer 332 are gold, and when bonding, the bonding can be performed under pressure and heat, the first bonding temperature is 380 ℃, and the first bonding pressure is 10 4 Pa to 10 5 Pa, holding time is 10min to 15min, and metal bonding and silicon-gold bonding can be realized. Illustratively, after the silicon gold bonding is achieved, the temperature is reduced to 300 ℃; the voltage of 1000V and the bonding pressure of 700N are applied to complete the anodic bonding of the second substrate 200 and the first substrate 100.
As shown in fig. 16, the step of obtaining the on-chip integrated structure 1000 includes providing one first substrate 100, one second substrate 200, another first substrate 100, and another second substrate 200 stacked in order. The first substrate 100 at the lower side may be provided with a locking hole structure 3, and the second substrate 200 thereon may be provided with a latch structure 5, and the first substrate 100 and the second substrate 200 may be connected by bonding the locking hole structure 3 and the latch structure 5. The first substrate 100 on the upper side may be provided with a locking hole structure 3, and the second substrate 200 thereon may be provided with a latch structure 5, and the first substrate 100 and the second substrate 200 may be connected by bonding the locking hole structure 3 and the latch structure 5. The upper first substrate 100 may be provided with a dielectric layer 110, and the dielectric layer 110 may be fixed with the lower second substrate 200.
The method for forming the on-chip integrated structure provided by the embodiment of the disclosure can stack multiple layers of substrates to realize various heat dissipation layouts and circuit layouts.
Referring to fig. 17 to 20, in the embodiment of the present disclosure, the processing step performed on the first substrate 100 may include: forming the mounting groove 1, forming the mark groove 2, forming the keyhole structure 3 including the metal layer structure 33, forming the runner structure 4, forming the alignment mark 21, and forming the stud structure 5.
Illustratively, etching the bonding surface of the first substrate 100 to form a sealing groove; a first metal seal layer 6 is formed which is recessed within the seal groove. Referring to fig. 18, the first metal seal layer 6 substantially surrounds the runner structure 4, illustratively, each two adjacent runner grooves are separated by the first metal seal layer 6.
In one embodiment, the first substrate 100 is a 4 inch wafer, the etching depth of the mark trench 2 is 100nm, the length dimension is 200 μm, the width dimension is 100 μm, and the alignment mark 21 can fill up the mark trench 2. The depth of the channel structures 4 is 150 μm and the width of each strip may be 1mm. The bonding groove 31 had an etching depth of 2 μm and a square shape with a side length of 1mm. The bonding hole 32 was etched to a depth of 2 μm and formed in a square shape having a side length of 100. Mu.m. The thickness of each metal layer structure 33 is 1 μm. The depth of the seal groove can be 100nm, and the width of the seal groove can also be on the nanometer scale.
The thickness of the first metal sealing layer 6 is illustratively 50nm. The first metal seal layer 6 may include a third connection layer of titanium material and a third bonding layer of gold material laminated on the third connection layer.
A latch structure 5 may be formed on the first substrate 100. The metal pad 51 has a thickness of 1 μm and a square shape with a side length of 1 mm. The metal bump 52 has a thickness of 1 μm and a square shape with a side length of 80 μm.
Referring to fig. 17, the method includes mounting the chip 10 into the mounting groove 1; forming a dielectric layer 110; and, forming an interconnection layer 120. The material of dielectric layer 110 may be silicon dioxide, covering chip 10. Interconnect layer 120 may include a plurality of rewiring layers therein, with interconnect layer 120 electrically connected to die 10 and routed out of dielectric layer 110.
Referring to fig. 19, the processing steps performed on the second substrate 200 may include: an alignment cut 202 is obtained, forming the keyhole structure 3 and the stud structure 5, and forming the second metal seal layer 7. The second metal seal layer 7 includes a fourth connection layer laminated on the second bonding surface 201 of the second substrate 200, and a fourth bonding layer laminated on the fourth connection layer. The material of the fourth bonding layer is the same as that of the third bonding layer, and the thickness of the second metal sealing layer 7 is 50nm.
At least one of the first substrate 100 and the second substrate 200 can be etched to form a sealing groove, and a first metal sealing layer 6 which is sunken in the sealing groove is formed; a second metal seal layer 7 is formed at a corresponding position of the other.
As shown in fig. 19, the latch structure 5 may be docked and bonded within the keyhole structure 3. At the same time, the second metal seal layer 7 may be butted in the seal groove.
Illustratively, in the step of obtaining the on-die integrated structure 1000, the second metal seal layer 7 is bonded to the first metal seal layer 6 at a second bonding temperature of 380 ℃ and a second bonding pressure of 10 prior to the step of bonding the stud structure 5 to the keyhole structure 3 4 Pa to 10 5 Pa, and vacuum degree 0.1Pa. Then the copper-copper bonding can be realized by pressurizing and heating, specifically, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min.
Referring to fig. 20, in an embodiment of the present disclosure, the processing step performed on the first substrate 100 may include: the mounting groove 1, the marking groove 2, the flow channel structure 4, the bonding groove 31 and the bonding hole 32 are formed, and the sealing groove is formed. The first substrate 100 is illustratively a 4 inch wafer, the etched depth of the mark grooves 2 is 100nm, the length dimension is 200 μm, and the width dimension is 100 μm. The depth of the channel structures 4 is 100 μm and the width of each strip may be 1mm. The etching depth of the bonding groove 31 was 2. Mu.m, and the length and width were 1mm. The bonding holes 32 were etched to a depth of 2 μm and a length and width of 100 μm. The depth of the seal groove can be 100nm, and the width of the seal groove can also be on the nanometer scale.
Illustratively, the method of the present embodiment further includes: a conductive via 8 is formed through the first substrate 100. The conductive vias 8 in the first substrate 100 provided with the runner structures 4 are designed to be electrically connected to the chip 10 to be mounted. In particular, a deep silicon etch can be realized between the runner grooves, avoiding the runner structure 4, for example between two sealing grooves. A copper seed layer may then be sputtered in the resulting via and then electroplated to fill the copper pillars, resulting in conductive vias 8 of the first substrate 100.
The method of the embodiment further comprises the following steps: sputtering silicon oxide to form an alignment mark 21 filled in the mark groove 2, and leveling and polishing; the chip 10 is embedded, a silicon dioxide dielectric layer 110 is deposited and an interconnect layer 120 is formed that is electrically connected to the chip 10.
Illustratively, each metal layer structure 33 has a thickness of 1 μm. In the formed stud structure 5, the metal pad 51 has a thickness of 1 μm and a square shape having a side length of 1 mm. The metal bump 52 has a thickness of 1 μm and a square shape with a side length of 80 μm. The thickness of the first metal seal layer 6 formed by sputtering was 50nm. The metal bump 52 is made of copper, and the third bonding layer is made of gold.
Referring to fig. 20, the processing steps performed on the second substrate 200 may include: obtaining an alignment cut surface 202; forming a corresponding keyhole structure 3 and a convex latch structure 5; a second metal seal layer 7 is formed. Illustratively, at the illustrated top surface (also referred to as the working surface) of the second substrate 200 facing away from the second bonding surface 201, a mounting groove is formed and the chip 10 is embedded; dielectric layer 110 and interconnect layer 120 are then also formed over the illustrated top surface of second substrate 200.
It is understood that the first substrate 100 may be referred to as a second substrate, and the second substrate 200 may be referred to as a first substrate. The runner structure 4 extending into the substrate is formed for at least one of the two substrates. Conductive vias 8 are formed through the second substrate 200 in the second substrate 200, the conductive vias 8 of the second substrate 200 being electrically connected to the chip 10 at the second substrate 200. The material of the conductive via 8 comprises copper. The second metal seal layer 7 comprises a fourth connection layer of titanium material and a fourth bonding layer of gold material, the thickness of the second metal seal layer 7 being 50nm.
The conductive vias 8 of the first substrate 100 are butted and electrically connected with the conductive vias 8 of the second substrate 200. At the same time, the corresponding keyhole structure 3 and the latch structure 5 are also in butt joint, and the corresponding first metal seal layer 6 and second metal seal layer 7 are also in butt joint. Exemplary, the second bonding temperature is 380 ℃, and the second bonding pressure is 10% 4 Pa to 10 5 Pa, the vacuum degree is 0.1Pa, and bonding of the second metal sealing layer 7 and the first metal sealing layer 6 is realized; then the copper-copper bonding can be realized by pressurizing and heating, specifically, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min.
In this embodiment, the first substrate 100 and the second substrate 200 are connected together, and the chip 10 at the first substrate 100 may be electrically connected to the chip 10 at the second substrate 200 through the conductive vias 8 of the first substrate 100 and the conductive vias 8 of the second substrate 200. The flow channel structure 4 can be used to dissipate heat from the chips 10 on both sides thereof, and the flow channel structure 4 is well sealed, so that the liquid therein does not leak from between the first substrate 100 and the second substrate 200.
Referring to fig. 21, in an embodiment of the present disclosure, the processing step performed on the first substrate 100 may include: forming a mounting groove 1 extending from a working surface 102 into the first substrate 100 of the first substrate 100 to be provided with the flow path structure 4; the marking grooves 2, the runner structures 4, the bonding grooves 31 and the bonding holes 32, the sealing grooves, and the conductive paths 8 penetrating the first substrate 100 are formed.
Then, the alignment mark 21 filled with the mark groove 2 may be formed; embedding the chip 10 into the mounting groove 1, depositing to form a silicon dioxide dielectric layer 110, and forming an interconnection layer 120 electrically connected to the chip 10; a metal layer structure 33 is formed to be depressed in the bonding groove 31, a latch structure 5 is formed, and a first metal seal layer 6 is formed. The conductive vias 8 in the first substrate 100 provided with the runner structures 4 are designed to be electrically connected to the chip 10 through the interconnect layer 120.
It is understood that the first substrate 100 may be referred to as a second substrate, and the second substrate 200 may be referred to as a first substrate. Referring to fig. 21, the processing steps performed on the second substrate 200 may include: forming a first fluid passage port 41 and a second fluid passage port 42 penetrating the second substrate 200; obtaining an alignment cut surface 202; forming a conductive channel 8 penetrating through the second substrate 200, and forming a corresponding keyhole structure 3 and a corresponding latch structure 5; a second metal seal layer 7 is formed.
The conductive vias 8 of the first substrate 100 are butted and electrically connected with the conductive vias 8 of the second substrate 200. At the same time, the corresponding keyhole structure 3 and the latch structure 5 are also in butt joint, and the corresponding first metal seal layer 6 and second metal seal layer 7 are also in butt joint. The first and second flow passage ports 41 and 42 communicate with the flow passage structure 4 of the first substrate 100, respectively. Illustratively, bonding of the second metal seal layer 7 to the first metal seal layer 6 is achieved, the resulting seal structure 11 of this embodiment completely surrounds the runner structure 4; then, the corresponding keyhole structure 3 and the latch structure 5 are bonded, and in addition, the first substrate 100 and the second substrate 200 may be bonded.
In this embodiment, the first substrate 100 and the second substrate 200 are connected together, and the chip 10 on the first substrate 100 can be led out to the side of the second substrate 200 opposite to the second bonding surface 201 thereof through the interconnection layer 120, the conductive vias 8 of the first substrate 100, and the conductive vias 8 of the second substrate 200. The flow channel structure 4 is communicated to the outside through the first flow channel port 41 and the second flow channel port 42 for heat dissipation to the chip 10, and the flow channel structure 4 is well sealed, and the liquid therein is not leaked from between the first substrate 100 and the second substrate 200. In addition, the latch structure 9 ensures that the first substrate 100 and the second substrate 200 are firmly connected and aligned reliably.
Referring to fig. 22, an on-chip integrated structure 1000 obtained by the method of the present embodiment includes a first substrate 100, a second substrate 200, a third substrate 300, and a fourth substrate 400 stacked in order.
The processing steps performed on the first substrate 100 may include: forming a mounting groove 1 extending from a working surface 102 into the first substrate 100 of the first substrate 100 to be provided with the flow path structure 4; forming a marking groove 2, forming a runner structure 4, forming a bonding groove 31 and a bonding hole 32, and forming a sealing groove; a conductive via 8 is formed through the first substrate 100.
The first substrate 100 is illustratively a 4 inch wafer, the etched depth of the mark grooves 2 is 100nm, the length dimension is 200 μm, and the width dimension is 100 μm. The depth of the channel structures 4 is 100 μm and the width of each strip may be 18mm. The etching depth of the bonding groove 31 was 2. Mu.m, and the length and width were 1mm. The bonding holes 32 were etched to a depth of 2 μm and a length and width of 100 μm. The depth of the seal groove can be 100nm, and the width of the seal groove can also be on the nanometer scale.
Then, the alignment mark 21 filled with the mark groove 2 may be formed; embedding the chip 10 into the mounting groove 1, depositing to form a silicon dioxide dielectric layer 110, and forming an interconnection layer 120 electrically connected to the chip 10; forming a metal layer structure 33 which is sunken in the bonding groove 31, and forming a first metal sealing layer 6 which is sunken in the sealing groove; in addition, a latch structure 5 may also be formed. The conductive vias 8 in the first substrate 100 are designed to be electrically connected to the interconnect layer 120.
Illustratively, the material of the first bonding layer 332 is copper and the material of the third bonding layer is gold. The thickness of the first metal seal layer 6 formed by sputtering was 50nm.
The processing steps performed on the second substrate 200 may include: forming a first fluid passage port 41 and a second fluid passage port 42 penetrating the second substrate 200; obtaining an alignment cut surface 202; forming a conductive via 8 through the second substrate 200; a keyhole structure 3 and a latch structure 5 corresponding to the first substrate 100 are formed on the second bonding surface 201, and a second metal seal layer 7 is formed. On a side of the second substrate 200 facing away from the second bonding surface 201, a lock hole structure 3 and a latch structure 5 corresponding to the third substrate 300 are formed.
Illustratively, the first and second flow ports 41, 42 are through holes each having a cross section of 3mm in length and width. The second metal seal layer 7 has a thickness of 50nm and the fourth bonding layer is gold. The keyhole feature 3 at the second bonding surface 201 of the second substrate 200 can mate with the stud feature 5 at the first substrate 100 and the stud feature 5 at the second bonding surface 201 of the second substrate 200 can mate with the keyhole feature 3 at the first substrate 100. The material of the metal bump 52 is copper.
It is understood that the third substrate 300 may be referred to as a first substrate and the fourth substrate 400 may be referred to as a second substrate. Specifically, the processing step of the third substrate 300 may include the foregoing step of processing the first substrate 100, and further includes the step of forming the auxiliary alignment cut 301, and in the runner structure 4 of the third substrate 300, the first runner port 41 and the second runner port 42 penetrate through the third substrate 300. The processing step of the fourth substrate 400 may include the aforementioned step of processing the second substrate 200.
When the first substrate 100, the second substrate 200, the third substrate 300, and the fourth substrate 400 are stacked in order, the alignment mark 21 of the first substrate 100 and the alignment cut surface 202 of the second substrate 200 are aligned, specifically, the alignment cut surface 202 may be aligned at the outer boundary of the alignment mark 21; the auxiliary alignment section 301 of the third substrate 300 may be aligned with the alignment section 202 of the second substrate 200; the fourth substrate 400 is aligned with the third substrate 300 using the alignment mark 21 of the third substrate 300. In other embodiments, the auxiliary alignment section of the third substrate may be aligned with the alignment mark of the second substrate.
Each conductive via 8 is butted and electrically connected, while the corresponding keyhole structure 3 and the stud structure 5, and the corresponding first metal seal layer 6 and second metal seal layer 7 are butted. Exemplary, the second bonding temperature is 380 ℃, and the second bonding pressure is 10% 4 Pa to 10 5 Pa, the vacuum degree is 0.1Pa, the bonding of the second metal sealing layer 7 and the first metal sealing layer 6 is realized, and the sealing structure 11 obtained in the embodiment completely surrounds the flow passage structure 4; then the copper-copper bonding can be realized by pressurizing and heating, specifically, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min. The latch structure 9 ensures that the first substrate 100 and the second substrate 200 are firmly connected and reliably aligned.
The chip 10 at the first substrate 100 may be electrically connected to the chip 10 at the third substrate 300 through the interconnect layer 120 at the first substrate 100, the conductive vias 8 of the second substrate 200, the interconnect layer 120 at the third substrate 300; the interconnect layer 120 at the third substrate 300 is also led out to the side of the fourth substrate 400 facing away from the third substrate 300 through the conductive via 8 at the third substrate 300 and the conductive via 8 at the fourth substrate 400.
Referring to fig. 12, 15, 16, 19, 20, 21, and 22, embodiments of the present disclosure provide, on the other hand, an on-die integrated structure 1000, the on-die integrated structure 1000 being fabricated using the steps of the aforementioned method.
The on-die integrated structure 1000 includes a first substrate 100, a latch structure 9, and a second substrate 200.
The first substrate 100 has a bonding groove 31 extending from the first bonding surface 101 of the first substrate 100 into the first substrate 100, and a plurality of bonding holes 32 extending from the bonding groove 31 into the first substrate 100.
The latch structure 9 is filled in the bonding groove 31 and the bonding hole 32. The latch structure 9 includes a first connection layer 331, a first bonding layer 332, a second bonding layer 512, and a second connection layer 511 stacked in order, and the latch structure 9 further includes a metal bump 52 extending from the second bonding layer 512 and penetrating the first bonding layer 332 and the first connection layer 331, and another first bonding layer 332 and another first connection layer 331 disposed under the metal bump 52.
The second substrate 200 is laminated on one side of the first substrate 100 where the bonding groove 31 is provided, the second substrate 200 is connected to the first substrate 100 through the latch structure 9, and at least one of the second substrate 200 and the first substrate 100 is provided with the flow path structure 4.
The on-chip integrated structure provided by the embodiment of the disclosure is easy to manufacture and has high yield; firm and reliable connection, stable structure and long service life; the heat dissipation effect is good.
The technical features of the embodiments disclosed above may be combined in any way, and for brevity, all of the possible combinations of the technical features of the embodiments described above are not described, however, they should be considered as the scope of the description provided in this specification as long as there is no contradiction between the combinations of the technical features.
In the embodiments disclosed above, the order of execution of the steps is not limited, and may be performed in parallel, or performed in a different order, unless explicitly stated and defined otherwise. The sub-steps of the steps may also be performed in an interleaved manner. Various forms of procedures described above may be used, and steps may be reordered, added, or deleted as long as the desired results of the technical solutions provided by the embodiments of the present disclosure are achieved, which are not limited herein.
The above disclosed examples represent only a few embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the invention as claimed. The scope of the invention should, therefore, be determined with reference to the appended claims.
Claims (11)
1. A method for forming an integrated structure on a die, comprising:
forming a keyhole structure on a first substrate of the two substrates, wherein the step of forming the keyhole structure comprises the following steps: forming a bonding groove extending into the substrate from a bonding surface of the substrate; forming a plurality of bonding holes extending from the bonding groove into the substrate; forming a metal layer structure which is sunken in the bonding groove;
forming a convex latch structure on a second substrate in the two substrates, wherein the step of forming the convex latch structure comprises the following steps: forming a metal bonding pad laminated on the substrate, wherein the periphery of the metal bonding pad is matched with the groove wall of the corresponding bonding groove, and the height of the metal bonding pad is equal to the depth of the metal layer structure in the bonding groove; forming a plurality of metal bumps laminated on the metal pad, wherein the positions of the metal bumps at the metal pad are matched with the positions of the bonding holes in the corresponding bonding grooves;
Forming a runner structure extending into the substrate on at least one of the two substrates;
abutting the metal pad into the bonding groove; and
and bonding the convex latch structure to the lock hole structure.
2. The method for forming an integrated structure on a die of claim 1, further comprising: forming further said latch structures on said first substrate; and forming other lock hole structures on the second substrate.
3. The method for forming an on-die integrated structure of claim 1, wherein the step of bonding the stud structure to the keyhole structure comprises: applying pressure to the first substrate and the second substrate in a lamination direction; the first substrate and the second substrate are heated, wherein a first bonding temperature is 350 ℃ to 450 ℃.
4. The method for forming an integrated structure on a die of claim 3, wherein in the step of bonding the stud structure to the keyhole structure, the first bonding temperature is 350 ℃, the first bonding pressure is 10MPa to 15MPa, and the holding time is 10min to 15min.
5. The method for forming an on-die integrated structure of claim 1, wherein an inner diameter of the bonding hole is greater than an outer diameter of the metal bump;
The inner diameter of the bonding groove is millimeter level or micrometer level, the depth of the bonding groove is micrometer level or nanometer level, the inner diameter of the bonding hole is micrometer level, and the depth of the bonding hole is nanometer level.
6. The method for forming an integrated structure on a die as recited in claim 1, wherein,
the step of forming the metal layer structure comprises the following steps: sputtering to form a first connecting layer, wherein the material of the first connecting layer comprises titanium; and sputtering to form a first bonding layer laminated on the first connecting layer;
the step of forming the metal pad includes: sputtering to form a second connecting layer, wherein the material of the second connecting layer comprises titanium; and sputtering to form a second bonding layer laminated on the second connecting layer, wherein the material of the second bonding layer, the material of the metal bump and the material of the first bonding layer comprise the same metal material, and the metal material comprises copper, gold, nickel or platinum.
7. The method for forming an integrated structure on a die of claim 1, wherein the runner structure is located at the bonding face, a substrate provided with the runner structure having a working face facing away from the bonding face, the method further comprising:
Forming a mounting groove extending into the base plate from the working surface on at least one base plate provided with the runner structure;
mounting a chip in the mounting groove; and
A dielectric layer or interconnect layer is formed overlying the chip.
8. The method for forming an integrated structure on a die of claim 7, wherein conductive vias are formed through the substrate, the conductive vias in the substrate provided with the runner structure being electrically connected to the chip; and
And butting and electrically connecting the conductive channels of the first substrate with the conductive channels of the second substrate.
9. The method for forming an integrated structure on a die of claim 1, further comprising:
etching the bonding surface to form a sealing groove on one of the two substrates;
forming a first metal seal layer recessed within the seal groove;
forming a second metal seal layer laminated to the other substrate for the other of the two substrates;
abutting the second metal seal layer within the seal groove; and
Bonding the second metal seal layer to the first metal seal layer prior to the step of bonding the tab structure to the keyhole structure to obtain a bead The bonding surface of the substrate surrounds the sealing structure of the flow channel structure, wherein the second bonding temperature is 380 ℃, and the second bonding pressure is 10% 4 Pa to 10 5 Pa, and vacuum degree 0.1Pa.
10. The method for forming an integrated structure on a die of claim 1, further comprising:
forming an alignment mark on a bonding surface of one of the two substrates;
forming an alignment cut surface on the periphery of the other of the two substrates, wherein the alignment cut surface is used for aligning with the alignment mark so as to enable the metal bonding pad to be in butt joint with the bonding groove; and
bonding or hermetically packaging the bonding surface of the first substrate and the bonding surface of the second substrate.
11. The on-chip integrated structure is characterized by comprising:
a first substrate having a bonding groove extending from a first bonding surface of the first substrate into the first substrate, and a plurality of bonding holes extending from the bonding groove into the first substrate;
the latch structure is filled in the bonding groove and the bonding hole and comprises a metal layer structure and a convex latch structure, and the metal layer structure is sunken in the bonding groove; the convex latch structure comprises a metal bonding pad and a plurality of metal convex points which are laminated on the metal bonding pad, the height of the metal bonding pad is equal to the depth of the metal layer structure in the bonding groove, the position of the metal convex point at the metal bonding pad is matched with the position of the bonding hole in the corresponding bonding groove, and the convex latch structure is bonded with the metal layer structure; and
And the second substrate is laminated on one side of the first substrate, which is provided with the bonding groove, and is connected with the first substrate through the latch structure, the second substrate is laminated on the metal bonding pad, and at least one of the second substrate and the first substrate is provided with a runner structure.
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| US10011478B2 (en) * | 2015-05-18 | 2018-07-03 | Innovative Micro Technology | Thermocompression bonding with raised feature |
| KR102497572B1 (en) * | 2018-07-03 | 2023-02-09 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
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