CN102157459A - TSV (through silicon via) chip bonding structure - Google Patents
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- CN102157459A CN102157459A CN201110063943.5A CN201110063943A CN102157459A CN 102157459 A CN102157459 A CN 102157459A CN 201110063943 A CN201110063943 A CN 201110063943A CN 102157459 A CN102157459 A CN 102157459A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81385—Shape, e.g. interlocking features
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Abstract
The invention discloses a TSV (through silicon via) chip bonding structure, belonging to the technical field of micro electronics. The bonding structure comprises a first chip and a second chip, wherein the first chip comprises a first micro bump and first surrounding structures around the first micro bump; the height of the first surrounding structures is more than that of the first micro bump; the second chip comprises a second micro bump; the second micro bump is embedded into the first surrounding structures and the first surrounding structures restrict lateral displacement of the second micro bump; the second chip also comprises second surrounding structures; and the first surrounding structures are embedded into the second surrounding structures and the second surrounding structures restrict lateral displacement of the first surrounding structures. The TSV chip bonding structure can be used in such fields as manufacturing of semiconductor devices and the like.
Description
Technical field
The present invention relates to the three-dimensional integrated technology of chip of TSV (Through Silicon Via, silicon through hole), be specifically related to a kind of TSV bonded layer structure Design, belong to microelectronics technology.
Background technology
Semi-conductor industry circle of today generally believes, based on the three-dimensional integrated technology of the chip of TSV, is to make chip continue one of important technology that advances along the blueprint of Moore's Law.For piling up of TSV chip, one of at present general and reliable method is, carries out intermetallic bonding by scolder between dimpling point (micro bump), forms intermetallic compound (IMC).The fusing point of IMC is higher, can carry out the bonding with other one deck chip again.
As shown in Figure 1,101 and 102 is the TSV chip, and 103 and 104 is conductive through hole, and 105 and 106 are conduction dimpling point.General, 105 and 106 carry out bonding by scolder 107.Bonding needs certain temperature, pressure and time.Scolder 107 can become soft under the bonding temperature, and in the vertical direction adds certain pressure and certain time during bonding.If the amount that dimpling point is highly uneven on dimpling point air spots or the chip surface, dimpling point is gone up scolder has nothing in common with each other, process conditions and environment have deviation slightly, then may produce component of force in the horizontal, make two chips that lateral shift take place in bonding process, cause the deviation of bonding between dimpling point.Along with reducing of dimpling spot size, dimpling point evenness, height consistency and an amount of property of scolder more and more are difficult to control, and it is big that the possibility that lateral shift takes place becomes.Industry is thought, through-hole diameter can narrow down to about 5 microns in the future, dimpling spot size and spacing will reduce thereupon, even several micron-sized lateral shifts also can become the key factor that influences whole laminated chips reliability between dimpling point, it shows the change on electricity and the thermodynamic behaviour.
At present, one of comparatively general method that addresses the above problem is that one of them the dimpling spot size in a pair of dimpling point of bonded layer is done more greatly, thereby even skew is arranged, still can intactly contact between two dimpling points.But along with reducing of dimpling spot size and pitch, larger-size conduction dimpling point means that two nearly steps of adjacent conductive dimpling dot spacing reduce in the bonded layer, and it is big that the possibility of signal cross-talk and short circuit becomes.And the size of dimpling point will be subjected to strict restriction on high density TSV laminated chips, in view of this, big or small dimpling point bonded layer structure is not to be to prevent in the high density TSV laminated chips that lateral shift from causing one of best approach of reliability reduction even component failure.In addition, although high-precision bonding chance reduces deviation, must bring cost rising problem.
In addition, along with chip develops to three-dimensional, the heat radiation of laminated chips becomes very important problem more than three layers.May introduce fluid channel 108 and 109 this moment on laminated chips, by fluid the heat that laminated chips intermediate layer chip produces is shed.As shown in Figure 1, when TSV chip 101 and 102 bondings lateral shift having taken place, thereby caused the through hole in the fluid channel salient point 110 and 111 to depart from, has caused the fluid channel blocked path.If adopt the method for size conduction dimpling point recited above, then can not tackle the problem at its root.Although solved the complete contact problems on the electricity, do not solve the deviation of fluid channel path even the integrity problem that obstruction brings.
As for the blockage problem that solves the fluid channel path by the method that increases the clear size of opening in 110 and 111, then not only can't fundamentally deal with problems, the lateral shift when if bonding has taken place, the fluid channel path can not be linear passages certainly, fluid can be turned round on the path in the bonded layer dimpling point, this can bring another problem, the not smooth fluid velocity that causes that is exactly fluid is slack-off, heat can not in time leave, the fluid gasification problem that thermal conductance causes becomes seriously, and a large amount of gas gets lodged in around the dimpling point through hole, and then causes the obstruction of fluid passage, heat accumulation finally causes chip failure at chip.This is not deal with problems and the result that brings at all.In addition, increase the clear size of opening of fluid channel through hole 108 or 109, form big or small runner through hole and connect, avoid the problem of blocked path to a certain extent, but neither best solution.So lateral shift problem that will when fundamentally solving chip bonding, take place.
Copper-copper Direct Bonding also is one of future development trend, and the bonding between copper-copper belongs to the metal diffusing bonding, and it does not need scolder, but the pressure of having relatively high expectations.Under High Voltage, it is big that the possibility that lateral shift takes place becomes.
Therefore, this area presses for a kind of TSV bonded layer structure and prevent that chip from lateral shift taking place when carrying out bonding, improves alignment precision, is fundamentally dealing with problems.
Summary of the invention
The objective of the invention is to overcome problems of the prior art, a kind of new TSV laminated chips bonded layer structure is provided, improve alignment precision, fundamentally solve problems such as lateral shift.
In order to realize technical purpose of the present invention, the present invention adopts following technical scheme.
A kind of TSV chip bonding structure, as shown in Figure 2, described bonding structure comprises first chip 1 and second chip 2, described first chip 1 comprises first around the first dimpling point 11 and the first dimpling point 11 around structure 12, and described first around the height of structure 12 height greater than the described first dimpling point 11; Described second chip 2 comprises the second dimpling point 21, and the described second dimpling point 21 embeds described first around the structure 12 and described first lateral displacement around the described second dimpling point 21 of structure 12 restrictions.
As shown in Figure 2, described second chip 2 also can comprise second around structure 22 strengthening the crosswise fixed effect, described second around the height of structure 22 height greater than the described second dimpling point 21; In the case, described first around structure 12 embed described second around structure 22 and described second around structure 22 restrictions described first the lateral displacement around structure 12.
Preferably, the cross section of the described second dimpling point is a square, described first the cross section around structure be interband every circular or square.For the lateral displacement (just second chip is with respect to the lateral displacement of first chip) that limits the second dimpling point, the second dimpling point and first should have the size that matches around structure, makes the second dimpling point just in time embed first around structure.Therefore, can there be line contact or face contact between the two, guarantee that second dimpling point can only be movable or stiff fully in very little scope.
Preferably, described first cross section around structure is a square, described second the cross section around structure be interband every circular or square.Equally, in order to limit first the lateral displacement (lateral displacement of the first dimpling point just around structure, first chip is with respect to the lateral displacement of second chip in other words), second should have the size that matches around structure and first around structure, makes first just in time to embed second around structure around structure and the first inner dimpling point thereof.Therefore, two around existing the contact of line contact or face between the structure, guarantees that first can only be movable or stiff fully in very little scope around structure.
Preferably, described second can outwards expand in the horizontal around structure, and then covers chip surface; Be described second can be the material layer that has hollow middle portion that is positioned at described second chip surface around structure, described hollow middle portion holds described first around structure, limits described first lateral displacement around structure.
Preferably, the described first dimpling point can have identical shape of cross section and size with described second dimpling point.
Preferably, described first dimpling point and the described second dimpling point are electrically connected, and separately with described chip in through hole be electrically connected, promptly the through hole in the first dimpling point and first chip is electrically connected, through hole in the second dimpling point and second chip is electrically connected, and constitutes the chip bonding structure that can conduct electricity thus.
Preferably, the described first dimpling point links to each other with the described second dimpling point, and has hollow middle part separately, thus at the inner runner that forms a sealing of whole bonding structure, and the circulation of the fluid that is used to dispel the heat.
In addition, described first chip and/or second chip surface can comprise a plurality of dimpling points, can on several dimpling points therein above-mentioned embedded structure be set, and realize two crosswise fixed between the chip thus; Also can increase more chip by above-mentioned embedded structure on other surface of described first chip and second chip, promptly the chip bonding structure is made up of the chip more than three, but they all do not break away from claim protection range of the present invention.
Compare with prior art, advantage of the present invention is: help to realize that the accurate aligning before the chip bonding contacts; Prevent that chip from carrying out bonding process lateral shift taking place.
Description of drawings
The schematic diagram of the lateral shift that Fig. 1 takes place when representing two TSV chip bondings in the prior art;
Fig. 2 represents the assembling schematic diagram of chip bonding structure of the present invention;
Fig. 3 represents the bonding structure schematic top plan view fixed to one another in the horizontal on the adjacent chips;
Fig. 4 represent on a TSV chip and the chip dimpling point and around structural representation;
Fig. 5 represents the TSV chip bonding structural representation of the embodiment of the invention;
Fig. 6 represents the TSV chip bonding structural representation of the embodiment of the invention;
Fig. 7 represents the TSV chip bonding structural representation of the embodiment of the invention;
Fig. 8 represents the TSV chip bonding structural representation of the embodiment of the invention;
Fig. 9 represents the TSV chip bonding structural representation of the embodiment of the invention;
Figure 10, Figure 11 be on adjacent two chip surfaces of the bonded layer of TSV laminated chips and chip chamber dimpling point and around structural representation.
Embodiment
Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.Need to prove, below the specific embodiment discussed only be specific embodiment in specific environment, be not to scope restriction of the present invention.For the architectural characteristic of every layer of silicon in the laminated chips among the present invention better is described, in the accompanying drawing all is silicon behind the attenuate, the general technology process of lamination is, DRIE carves the hole silicon, electroplate fill, the chip ephemeral key is incorporated into glass, attenuate, persistent key are incorporated into silicon, separate bonding with glass.The present invention can be used on other semiconductor chips, shown is preferably square and circular around structure and dimpling point, but also can be other Any shape, and the size among the embodiment is for better explanation summary of the invention in addition, is not actual ratio.Bonding between the metal dimpling point among the present invention can be the Cu-Sn bonding, it also can be the Cu-Cu bonding, metal dimpling point can directly contact with the TSV conductive through hole, and the mode that also can pass through RDL (Redistribution Layer) forms electricity with conductive through hole and is connected.A face or two faces on the TSV chip can have the RDL layer.
Need to prove that in addition claim of the present invention described " first chip " has relative implication with " second chip ", be intended to be convenient to describe.In specific embodiment, described " first chip " both can be that claim described " first chip " also can be " second chip ", the not flesh and blood of influence technique scheme.
In the following embodiments, the parameter information of some key structures is: the thickness of single chip is about 30 μ m～200 μ m; Through-hole diameter is about 5 μ m～20 μ m; The dimpling spot size is about 5 μ m～30 μ m; Dimpling point highly is about 3 μ m～20 μ m; Around structure height is 5 μ m～40 μ m.
Shown in Fig. 3 a and b, 201 expressions on first chip surface around structure, the structure of the dimpling point on 202 expressions, second chip surface, its shape size is determined according to 201 structure.As can be seen, can block dimpling point 202 in the horizontal among the figure, thereby prevent at the contingent lateral displacement of bonding process chips around structure 201.In Fig. 3 a, there is the line contact between 201 and 202, promptly on each side of 202, two ends of 201 curved surface prop up the side, form two line contacts.In Fig. 3 b, there is the face contact between 201 and 202, promptly on each side of 202,201 inner surface contacts with it, forms and compares better fixed effect with Fig. 3 a.
Shown in Fig. 3 c and d, 203,204 expressions on first chip surface dimpling point and around structure, on 205 expressions, second chip surface around structure, among the figure as can be seen dimpling point 203, around structure 204 and block successively in the horizontal around structure 205.In Fig. 3 c, 205 respectively and have line contact between 203 and 204.In Fig. 3 d, 205 respectively and have face contact between 203 and 204.
By Fig. 3 a-d as can be known, dimpling point and all be not limited to specific shape around the cross section of structure both can be circular, also can be foursquare, even other shape; Contact form between the two both can be the line contact, it also can be the face contact, other perhaps possible way of contact, but its core point all be by one in the horizontal that dimpling point is fixing around structure, can also should be around structure around the structure crosswise fixed by another.
During aligning operating of contacts before specifically carrying out bonding, can after two chip contacts, add appropriate cross force, not realize accurate aligning if it does not move just explanation to top chip, if it moves then explanation and does not accurately aim at, aim at operating of contacts again.Help to realize the accurate contact of aiming at by such structure and mode of operation, just can reduce the lateral alignment skew in the first step.And the more important thing is in the middle of next step bonding process and can prevent lateral shift.
Shown in Fig. 4 a, 301 expression substrates in the TSV chip, transition zone 302 is an oxide layer, 303 is barrier layer.302 can form with PECVD or LPCVD deposit, and 303 can form with PVD or ALD method.The through hole of electric conducting material is filled up in 304 expressions, can fill with electro-plating method.305 and 306 are respectively the passivation layer of chip surface, can form with PECVD or LPCVD deposit, and formation perhaps is heating and curing after the spin coating.307 and 308 is chip 1 lip-deep dimpling point and around structure, and 309 is another lip-deep dimpling point of chip.303 barrier layers are preferably Ti, W, and the electric conducting material in 304 is preferably Cu.Passivation layer 305 and 306 can be organic substances such as silica, silicon nitride, BCB or PI. Dimpling point 307 and 309 can form by first sputtering seed layer re-plating, is preferably Cu.If 308 be metal, then can first sputter or MOCVD deposit Seed Layer, re-plating forms, then the passivation layers such as all right silicon oxide deposition or silicon nitride on the surface; If 308 be organic polymer, then directly deposit or first deposit transition zone and then deposit organic substance.Organic deposition process generally is to be heating and curing in baking oven after the spin coating.Come graphically with the method for plasma etching then, such as materials such as BCB, PI.Its transition zone is the organic substance that can strengthen the organic substance adhesion strength.Need to prove that conduction dimpling point directly contacts with through hole among the figure, the dimpling point can also be by contacting with the top layer metallic layer of device interconnection layer, being connected by contacting with through hole formation electricity with the RDL layer.Also can have around the dimpling point 309 among the figure around structure.
In following accompanying drawing, through hole and transition zone are identical with the situation of Fig. 4 a, and promptly through hole 304, oxide layer 302 and barrier layer 303.
Shown in Fig. 4 b, in the silicon substrate 311,312 is the first surface passivation layer, and 313 is the RDL layer, and 314 is passivation layer, and 315 are conduction dimpling point, and 316 is around structure.317 is passivation layer on the second surface, and 318 are conduction dimpling point, and 319 is around structure.Wherein 312 and 317 can form by PECVD or LPCVD deposit, formation perhaps is heating and curing after the spin coating.313 can form by re-plating after sputter or the MOCVD deposit Seed Layer, and 313 materials are preferably Cu.314 can be oxide, nitride, can form by PECVD or LPCVD deposit, and other 314 also can be organic substance, as BCB etc.315,318 can and then electroplate by first sputter or MOCVD deposit Seed Layer and form.If 316,319 is nonmetal, might as well be organic polymer, then directly deposit or first deposit transition zone and then deposit form; If 316,319 be metal, then can first sputter or MOCVD deposit Seed Layer re-plating formation, then can be at the surface deposition passivation layer.
As shown in Figure 5, a is a longitudinal sectional drawing, and b is a transverse cross-sectional view, and wherein 401 is a TSV chip silicon substrate, and 402 is passivation layer, and 403 are conduction dimpling point, and 404 is around structure.405 is the 2nd TSV chip silicon substrate, and 406 is passivation layer, and 407 are conduction dimpling point.Bonded layer structure 408 comprised the dimpling point on first chip 403 in the bonded layer, around the dimpling point 407 on the structure 404 and second chip.Wherein 402 and 406 can form by PECVD or LPCVD deposit, formation perhaps is heating and curing after the spin coating.403 and 407 can be by first sputter or MOCVD deposit Seed Layer and then plating formation.If 404 is nonmetal, might as well be organic polymer, then directly deposit or first deposit transition zone and then deposit form; If 404 be metal, then can first sputter or MOCVD deposit Seed Layer re-plating formation, then can be at 404 surface deposition passivation layers.408 as can be seen from figure, blocked dimpling point 407 in the horizontal around structure 404, the lateral shift that takes place when preventing bonding.
As shown in Figure 6, a is a longitudinal sectional drawing, and b is a transverse cross-sectional view, and wherein 501 is a TSV chip silicon substrate, and 502 is passivation layer, and 503 are conduction dimpling point, and 504 is around structure.505 is the 2nd TSV chip silicon substrate, and 506 is passivation layer, and 507 are conduction dimpling point, and 508 is around structure.Bonded layer structure 509 has comprised 507,508 on 503,504 and second chip on first chip in the bonded layer.Wherein 502 and 506 can form by PECVD or LPCVD deposit, formation perhaps is heating and curing after the spin coating.503 and 507 can be by first sputter or MOCVD deposit barrier layer and then plating formation.If 504 and 508 is nonmetal, might as well be organic polymer, then directly deposit or first deposit transition zone and then deposit form; If 504 and 508 be metal, then can first sputter or MOCVD deposit Seed Layer re-plating formation, then can be at the surface deposition passivation layer.509 as can be seen from figure, and 508 on 503,504 and second chip on first chip can be fixed to one another be in the horizontal lived.Need to prove as the case may be, can also have more a plurality of around the conduction dimpling point around structure.
As shown in Figure 7, a is a longitudinal sectional drawing, and b, c are transverse cross-sectional view, and wherein 511 is a TSV chip silicon substrate, and 512 is passivation layer, and 513 are conduction dimpling point.514 is around structure, and it can be regarded as among Fig. 6 504 outside expansion, and each becomes one around structural extended on 511 chip surfaces, shown in Fig. 7 (c).515 is the 2nd TSV chip silicon substrate, 516 is passivation layer, 517 layers can with 514 carry out bonding to improve the bond strength of whole bonding structure, 518 are conduction dimpling point, 519 is around structure, and bonded layer structure 520 has comprised 518,519 on 513,514 and second chip on first chip in the bonded layer.Wherein 512 and 516 can form by PECVD or LPCVD deposit, formation perhaps is heating and curing after the spin coating.513 and 518 can be by electroplating or first sputter or MOCVD deposit barrier layer and then plating formation.514,517 can be organic substance or deactivation matter, preferred organic substance, and directly deposit or first deposit transition zone and then deposit form, and 514 and 517 can be carried out bonding.If 519 is nonmetal, might as well be organic polymer, then directly deposit or first deposit transition zone and then deposit form; If 519 be metal, then can first sputter or MOCVD deposit Seed Layer re-plating formation, then can be at the surface deposition passivation layer.520 as can be seen from figure, and 519 on 513,514 and second chip on first chip can be fixed to one another be in the horizontal lived.
As shown in Figure 8, a is a longitudinal sectional drawing, and b is a transverse cross-sectional view, and wherein 601 is a TSV chip silicon substrate, and 602 is the fluid channel through hole, and 603 and 604 are respectively first, second transition zone, and 605 is passivation layer, and 606 is the fluid channel salient point, and 607 is around structure.608 is the 2nd TSV chip silicon substrate, and 609 is the fluid channel through hole, and 610 and 611 are respectively first, second transition zone, and 612 is passivation layer, and 613 is the fluid channel salient point, and 614 is around structure.Bonded layer structure 615 has comprised 613,614 on 606,607 and second chip on first chip in the bonded layer.First transition zone of fluid channel through-hole side wall can be a silica, and available PECVD or LPCVD deposit form; Second transition zone can be a metal, as Ti, can form with PVD or ALD deposit.Passivation layer 605,612 can form with PECVD or LPCVD deposit, and formation perhaps is heating and curing after the spin coating.Fluid channel salient point 606 and 613 is preferably organic polymer, and directly spin-on deposition is solidified again, and plasma etching forms then.Be preferably organic polymer around structure 607 and 614, then directly deposit or first deposit transition zone and then deposit form.Understand some organic substance during spin coating and penetrate into through hole, when carrying out plasma etching after the curing, etch away residual organic in the through hole after graphically finishing again.615 as can be seen from figure, and 614 on 606,607 and second chip on first chip can be fixed to one another be in the horizontal lived.In addition, also can be with 408 bonded layer structure among Fig. 5, promptly only with a dimpling point that blocks another chip around structure.
As shown in Figure 9, a is a longitudinal sectional drawing, and b is a transverse cross-sectional view.621 is a TSV chip silicon substrate, and 622 is the fluid channel through hole, and 623 and 624 are respectively first, second transition zone, and 625 is passivation layer, and 626 is the fluid channel salient point.627 is around structure, and it can be regarded as among Fig. 8 607 outside expansion.628 is the 2nd TSV chip silicon substrate, and 629 is the fluid channel through hole, and 630 and 631 are respectively first, second transition zone, and 632 is passivation layer, and 633 is transition zone, and 634 is the fluid channel salient point, and 635 is around structure.633 layers can with 627 carry out bonding to improve the bond strength of whole bonding structure.Bonded layer structure 636 has comprised 634,635 on 626,627 and second chip on first chip in the bonded layer.First transition zone of fluid channel through-hole side wall can be a silica, and available PECVD or LPCVD deposit form; Second transition zone can be a metal, as Ti, can form with PVD or ALD deposit.Passivation layer 625,632 can form with PECVD or LPCVD deposit, and formation perhaps is heating and curing after the spin coating.633,626 and 634 be preferably organic polymer, directly spin-on deposition is heating and curing again, and plasma etching forms then.Be preferably organic polymer around structure 627 and 635, then available with the direct deposit of quadrat method or first deposit transition zone and then deposit formation.Understand some organic substance during spin coating and penetrate into through hole, when carrying out plasma etching after the curing, etch away residual organic in the through hole after graphically finishing again.636 as can be seen from figure, and 635 on 626,627 and second chip on first chip can be fixed to one another be in the horizontal lived.
As shown in figure 10, TSV laminated chips 701 comprises silicon substrate 702 and 703, elliptical structure 704 and 705 and conductive through hole.704 and 705 can be silicon substrate, TSV chip or homogeneity, heterogeneous TSV laminated chips.702 and 703 bonded layer structure is that the bonded layer structure of 509,702 and 704 shown in Fig. 6 is that the bonded layer structure of 520,703 and 705 shown in Fig. 7 is 408 shown in Fig. 5.The bonded layer structure that need to prove each TSV laminated chips can be according to 408,509 and 520, and any arrangement of other similar structures.
As shown in figure 11, TSV laminated chips 801 comprises silicon substrate 802 and 803, elliptical structure 804 and 805 and conductive through hole and fluid channel through hole.804 and 805 can be silicon substrate, TSV chip or homogeneity, heterogeneous TSV laminated chips.Bonded layer structure between 802 and 803,802 and 804,803 and 805 metal dimpling points is respectively 509,520,408 shown in Fig. 6, Fig. 7, Fig. 5.Bonded layer structure between 802 and 803,803 and 805 fluid channel through holes is that the bonded layer structure between 615,802 and 804 fluid channel through holes shown in Fig. 8 is 636 shown in Fig. 9.
Claims (10)
1. TSV chip bonding structure, described bonding structure comprises first chip and second chip, it is characterized in that described first chip comprises first around the first dimpling point and the first dimpling point around structure, described first around the height of the structure height greater than the described first dimpling point; Described second chip comprises second dimpling point, and the described second dimpling point embeds described first around the structure and described first lateral displacement around the described second dimpling point of structural limitations.
2. TSV chip bonding structure as claimed in claim 1 is characterized in that described second chip also comprises second around structure, and described second around the height of the structure height greater than the described second dimpling point; Described first around structure embed described second around structure and described second around structural limitations described first the lateral displacement around structure.
3. TSV chip bonding structure as claimed in claim 1 or 2 is characterized in that, the cross section of the described second dimpling point is a square, described first the cross section around structure be interband every circular or square.
4. TSV chip bonding structure as claimed in claim 2 is characterized in that, described first cross section around structure is a square, described second the cross section around structure be interband every circular or square.
5. TSV chip bonding structure as claimed in claim 2, it is characterized in that, described first cross section around structure is a square, and described second is the material layer that has hollow middle portion that is positioned at described second chip surface around structure, and described hollow middle portion holds described first around structure.
6. TSV chip bonding structure as claimed in claim 1 or 2 is characterized in that, the described first dimpling point has identical shape of cross section and size with described second dimpling point.
7. TSV chip bonding structure as claimed in claim 1 or 2 is characterized in that, the described first dimpling point and the described second dimpling point are electrically connected, and separately with described chip in through hole be electrically connected.
8. TSV chip bonding structure as claimed in claim 1 or 2 is characterized in that, the described first dimpling point links to each other with the described second dimpling point, and has hollow middle part separately.
9. TSV chip bonding structure as claimed in claim 1 or 2 is characterized in that, described first dimpling point and described second dimpling put each free metal or organic polymer is made.
10. TSV chip bonding structure as claimed in claim 2 is characterized in that, described first makes around each free metal of structure or organic polymer around structure and described second.
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| CN110116984A (en) * | 2018-02-06 | 2019-08-13 | 中芯国际集成电路制造(上海)有限公司 | MEMS device and preparation method thereof |
| CN112992823A (en) * | 2019-12-17 | 2021-06-18 | 中国科学院苏州纳米技术与纳米仿生研究所 | Micro-bump connecting structure |
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| CN117246976A (en) * | 2023-11-17 | 2023-12-19 | 之江实验室 | On-chip integrated structure and forming method thereof |
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