CN108288608A - Chip packing-body and preparation method thereof - Google Patents
Chip packing-body and preparation method thereof Download PDFInfo
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- CN108288608A CN108288608A CN201711438778.0A CN201711438778A CN108288608A CN 108288608 A CN108288608 A CN 108288608A CN 201711438778 A CN201711438778 A CN 201711438778A CN 108288608 A CN108288608 A CN 108288608A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of chip packing-body and preparation method thereof, which includes the first packaging body and the second packaging body being stacked, which includes：First substrate；First chip, for the setting of the first chip on the first substrate between the second packaging body, chip one side is equipped with the first salient point as port, and the first salient point is arranged in the first chip backwards to first substrate side；First plastic-sealed body, plastic-sealed body are arranged in the side that first substrate has the first chip, for encapsulating chip；Wherein, the first salient point is connected to the outside of the first plastic-sealed body, for being connect with element in the second packaging body backwards to first substrate side in the first plastic-sealed body.By the above-mentioned means, the present invention can improve the quality of chip packing-body, reduce the thickness of chip packing-body.
Description
Technical field
The present invention relates to chip encapsulation technology fields, more particularly to a kind of chip packing-body and preparation method thereof.
Background technology
Encapsulation is the integrated circuit die that will be produced the process that integrated circuit assembly is chip final products
It is placed on the substrate that one piece is played the role of carrying, pin is extracted, then fixation is packaged into as an entirety.
As highly dense integrated major way is encapsulated at present, stacked package (package on package, POP) is got over
Carry out more attention.
However, present inventor has found during long-term research invention, in POP structures, lower package body
Chip is usually connected on the substrate in lower package body in a manner of upside-down mounting.Such structure to be molded to lower chip
When need by the way of underfill, to easy to produce hole；Meanwhile the mode of upside-down mounting connection can entirely to encapsulate knot
Structure thickness increases, and it is impossible to meet the demands that Current electronic product is lightening.
Invention content
The invention mainly solves the technical problem of providing a kind of chip packing-bodies and preparation method thereof, can improve chip
The quality of packaging body reduces the thickness of chip packing-body.
In order to solve the above technical problems, one aspect of the present invention is：A kind of chip packing-body is provided, it is described
Chip packing-body includes the first packaging body and the second packaging body being stacked, and first packaging body includes：First substrate；The
One chip, first chip are arranged on the first substrate between second packaging body, the first chip one side
Equipped with the first salient point as port, first salient point is arranged in first chip backwards to the first substrate side；The
One plastic-sealed body, first plastic-sealed body are arranged in the side that the first substrate has first chip, described in encapsulating
First chip；Wherein, first salient point is connected to the outside of first plastic-sealed body, for first plastic-sealed body backwards
The first substrate side is connect with element in second packaging body.
In order to solve the above technical problems, another technical solution that the present invention uses is：A kind of chip packing-body is provided
Preparation method, the chip packing-body include the first packaging body and the second packaging body being stacked, the method includes：By
One chip is arranged on the first substrate, wherein first chip is provided with the first salient point backwards to the first substrate side；It adopts
The first plastic-sealed body is formed backwards to the first substrate side, wherein described first with pressing Shooting Technique in first chip
Salient point is connected to the outside of first plastic-sealed body；Second envelope is set backwards to the substrate side in first plastic-sealed body
Body is filled, so that second packaging body is connect by first salient point with first packaging body, to form the chip
Packaging body.
The beneficial effects of the invention are as follows：The case where being different from the prior art will be arranged the bottom of in chip packing-body of the present invention
The first salient point of the first chip is arranged on the first substrate upward in first packaging body in portion, and such set-up mode makes right
Reduction generates the risk of hole due to the injection molding manner using underfill when first chip carries out plastic packaging, improves chip package
The quality of body；In turn, due in plastic packaging, without asking for the preset space between considering at the top of the first chip and the first packaging body
Topic, so as to reduce the thickness of chip packing-body to a certain extent.
Description of the drawings
Fig. 1 is the structural schematic diagram of one embodiment of control technology chips packaging body；
Fig. 2 is the structural schematic diagram of another embodiment of control technology chips packaging body；
Fig. 3 is the structural schematic diagram of one embodiment of chip packing-body of the present invention；
Fig. 4 is the structural schematic diagram of chovr body in one embodiment of chip packing-body of the present invention
Fig. 5 is the flow diagram of one embodiment of chip package preparation of the present invention；
Fig. 6 is the flow diagram of one embodiment of chip package preparation of the present invention；
Fig. 7 to Figure 12 is the structural schematic diagram in one embodiment of chip package preparation of the present invention.
Specific implementation mode
Before specifically describing present disclosure, first technology contents related to the present invention are simply introduced.
For mainly there are following 2 kinds to POP encapsulating structures as directed, please be tied refering to fig. 1 with Fig. 2, two kinds of encapsulation respectively
In structure, the chip of lower package body is salient point upside-down mounting set-up mode directed downwardly, it is readily appreciated that ground, such as Fig. 1, such setting side
Formula so that when being packaged, need after the completion of each salient point 11 is welded with corresponding pad in structure, then be molded,
There is a certain distance (in referring specifically to Fig. 1 at A) between chip 12 and the substrate 13 of upper packaging body to must assure that,
To ensure that chip 12 can encapsulate well；In addition salient point 11 is arranged downward but also salient point 11 occupies certain thickness, the two
The thickness of entire chip packing-body can be greatly increased by integrating.
Also, due to above-mentioned set-up mode so that generally required when being molded to chip 12 using underfill
Injection molding manner is also easy to produce hole, to reduce the quality of entire chip packing-body.
Simultaneously as chip 12 is arranged at intermediate position, and using the connection for realizing upper lower package body around the chip 12
Mode, so that the salient point or sphere of the sufficient upper lower package body of space setting connection, and be merely able to be arranged
In the surrounding of chip 12, to limit the quantity of interconnection port.
In addition, due in encapsulation process, the coefficient of thermal expansion of each material used by chip packing-body mismatches, and easily produces
Raw part thermal stress, and encapsulation is made to generate surface warp, and the warpage of lower part packaging body can influence final mutual of top packaging body
Folded effect, and excessive warpage not only increases the difficulty such as plastic packaging follow-up process such as rib cutting/forming, is carried out in chip plastic-sealed body finished product
Deficient manufacturing procedure increases when surface mount, leads to component failure to be also easy to produce chip and encapsulation crackle etc..
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes.
Referring to Fig. 3, Fig. 3 is the structural schematic diagram of one embodiment of chip packing-body of the present invention.It should be pointed out that this
Chip packing-body in embodiment can be packaged by stacked package (package on package, POP) technique
Made of.Wherein, which includes the first packaging body 21 and the second packaging body 22 being stacked, certainly, and it is unlimited
Due to this two layers, 2~8 layers can be stacked according to need.
Wherein, the first packaging body 21 includes：First substrate 211, the first chip 212 and the first plastic-sealed body 213.
Carrying platform of the first substrate 211 as the first chip 212, predominantly the first chip 212 provide electrical connection, protect
Shield, support, heat dissipation, assembling etc..Specifically, the base material as first substrate 211 such as PI, PET, PEN can be used.
First chip 212 is arranged on first substrate 211 between the second packaging body 22, and 212 one side of the first chip is equipped with
As the first salient point 214 of port, first salient point 214 setting is in the first chip 212 backwards to 211 side of first substrate.Wherein,
The size of first salient point 214 can be arranged according to demand.Specifically, traditional printing, plating etc. can be used in the formation of the first salient point 214
Mode is formed by the first salient point 214 under different process and highly slightly has difference, can select suitable technique according to demand.In addition,
The material of first salient point 214 can be tin, copper etc., and material of the tin as the first salient point 214 is selected in present embodiment.
Specifically, the first adhesive-layer 215 can be set between the first chip 212 and first substrate 211 so that the first core
Piece 212 can be secured be fixed on first substrate 211, specifically, film-form adhesive, example can be used in the first adhesive-layer 215
Such as EVA adhesive film, PVB glued membranes, are not specifically limited herein.Certainly, since plastic packaging itself can also fix the first chip 212
In first substrate 211, be arranged between the first chip 212 and first substrate 211 can also be saved in other embodiments
One adhesive-layer 215.
It should be pointed out that in present embodiment, the setting of the first plastic-sealed body 213 has the first chip in first substrate 211
212 side, for encapsulating chip.Specifically, since in present embodiment, the setting of the first salient point 214 is carried on the back in the first chip 212
To 211 side of first substrate, therefore, when forming the first plastic-sealed body 213, the mode of pressing injection molding may be used, it specifically can be with
Casting resin is to form first plastic-sealed body 213.
Wherein, the first salient point 214 is connected to the outside of the first plastic-sealed body 213, is used in the first plastic-sealed body 213 backwards to first
211 side of substrate is connect with element in the second packaging body 22.Specifically, the first salient point 214 can directly with the second packaging body 22
Connection, or can also be connect indirectly with the second packaging body 22 by connecting an intermediate member.
Optionally, the first salient point 214 further comprises：Basal part 2141 and extension 2142.Wherein, basal part 2141 is set
Set in the inside of the first plastic-sealed body 213, extension 2142 is at least partially disposed in the outside of the first plastic-sealed body 213, and one end with
Basal part 2141 connects, and the other end with element in the second packaging body 22 for connecting.Specifically, in the system for carrying out chip packing-body
When standby, the first plastic-sealed body encapsulated entire first chip 212 and be highly higher than basal part 2141 is formed on the first chip 212
213, after its formation, the first plastic-sealed body of position pair 213 that laser drilling processes can be used in corresponding first salient point 214 drills, shape
At the hole that can expose 2,141 first salient point 214 of basal part, then handled in such a way that metal injects or prints, shape
At the extension 2142 that the first plastic-sealed body 213 is connect and can exposed with basal part 2141.
In an application scenarios, when forming the first plastic-sealed body 213, first can be less than by controlling the height of mold
Salient point 214 makes the height for the first plastic-sealed body 213 to be formed be less than the first salient point 214, so that the first salient point 214 can be sudden and violent
It is exposed to the outside of the first plastic-sealed body 213；It can also be made to encapsulate entire first chip completely when forming the first plastic-sealed body 213
212 and first salient point 214, and after its formation, it can be moulded backwards to the side pair first of first substrate 211 along the first salient point 214
Envelope body 213 is thinned or is polished so that the first salient point 214 is connected to the outside of the first plastic-sealed body 213.
Optionally, 212 side of the first chip of direction of first substrate 211 is provided with the first pad 216, the first chip
212 are provided with second pad corresponding with the first pad 216 217 backwards to 211 side of first substrate, and the first packaging body 21 is further
Including：Bonding wire 218,218 one end of bonding wire connect the first pad 216, and the other end connects second pad corresponding with the first pad 216
217, to establish connection between chip and substrate.
Wherein, the first pad 216 and the second pad 217 can be copper foil, and spun gold, copper wire, aluminium specifically can be used in bonding wire 218
Line etc., in present embodiment, in order to improve yield and reduce technology difficulty, bonding wire 218 selects spun gold.Specifically, Ke Yi
After first chip 212 is bonded together with first substrate 211 by the first adhesive-layer 215, using high-purity spun gold the first core
Piece 212 is connect with first substrate 211, so as to which the first chip 212 is further passed through first substrate 211 and external device
Connection.
It is noted that by the first face-up setting of chip 212 in present embodiment so that carrying out chip packing-body
Encapsulation when, the first salient point 214 can be arranged in the first chip 212 upward backwards to the side of first substrate 211, to formed
Reduction generates the risk of hole due to the injection molding manner using underfill when the first plastic-sealed body 213, improves chip packing-body
Quality；In turn, in injection molding, without considering the preset space problem between the first chip 212 and the first packaging body and chip,
So as to reduce the thickness of chip packing-body to a certain extent, to reduce the thickness of the first plastic-sealed body 213, be conducive to save
The about space of subsequent product.
Optionally, chip packing-body further includes chovr body 23, which is arranged in the first packaging body 21 and the second envelope
Between filling body 22, for connecting the first packaging body 21 and the second packaging body 22.Wherein, chovr body 23 is by the material with conducting function
Matter is made, such as can be similar with first substrate 211, and metallic conduction piece is arranged inside organic plastics material, to realize the
Being electrically connected between one plastic-sealed body 213 and the second plastic-sealed body.
Wherein, the rigidity or intensity of chovr body 23 are more than the rigidity or intensity of the first plastic-sealed body 21.Since chovr body 23 is set
It sets in the first plastic-sealed body 213 backwards to the side of first substrate 211, enables to the first plastic-sealed body 213 can be in certain journey in this way
By the common protection of first substrate 211 and chovr body 23 on degree, to reduce the probability of 213 warpage of the first plastic-sealed body.
Optionally, chip packing-body further includes：Second adhesive-layer 24, second adhesive-layer 24 setting is in chovr body 23 and the
Side between one plastic-sealed body 213, for chovr body 23 to be mounted on the first plastic-sealed body 213 backwards to the side of first substrate 211,
And the center between chovr body 23 and the first plastic-sealed body 213 is left a blank, the place of leaving a blank 212 position of corresponding first chip.Wherein, second is viscous
Glue-line 24 specifically can be identical as the first adhesive-layer 215, chovr body 23 is firmly fixed to the one of the first plastic-sealed body 213
Side.
Specifically, chovr body 23 is provided with towards 21 side of the first packaging body：Third pad 231, third pad 231 correspond to
First salient point 214 is arranged, for being connected with the first salient point 214.Specifically, between third pad 231 and the first salient point 214
Reflow Soldering can be used and realize connection.
In an application scenarios, the height of the first salient point 214 is higher, in order to realize the frivolous of chip packing-body structure
Change, and prevent entire chovr body 23 correspond to the first chip 212 position height and surrounding it is highly non-uniform, can be by the
Three pads 231 are set as groove type, as shown in figure 4, the third pad 231 of groove type can be used in corresponding accommodating first salient point
The whole of chip packing-body is improved to avoid the generation of the above situation in 214 part being arranged outside the first plastic-sealed body 213
Weight.
Certainly, in application scenes, the first salient point 214 suitably can also be done according to demand it is shorter, for example, being
Ensure the connection between the first salient point 214 and third pad 231, after the formation of first plastic-sealed body 213, by polishing by the
One salient point 214 exposes, with realize with the connection of third pad 231, without using being further formed extension 2142 by the way of and
Third pad connects.Under such circumstances, you can be not required to set third pad 231 to groove type.
Optionally, chip packing-body further includes：Second salient point 25, second salient point 25 setting is in the second packaging body 22 and turns
Between junctor 23.Wherein, the second salient point 25 can be the combination of metallic tin salient point and solder, or can also be solder ball.
Meanwhile second packaging body, 22 side is provided with the 4th pad 232 in chovr body 23, the 4th pad 232 with
Second salient point 25 is correspondingly arranged, and 23 side of chovr body is provided with the 5th pad 221, the 5th pad in the second packaging body 22
221 are correspondingly arranged with the second salient point 25.Wherein, the second salient point 25 is connected with the 4th pad 232, the 5th pad 221 respectively,
So that the second packaging body 22 is connect by chovr body 23 with the first packaging body 21.
Specifically, the second packaging body 22 includes：Second substrate 222, the second chip 223 and the second plastic-sealed body 224, the second core
In second substrate 222 backwards to 21 side of the first packaging body, the setting of the second plastic-sealed body 224 has the setting of piece 223 in second substrate 222
The side of second 223, core, for encapsulating the second chip 223.
Wherein, the setting of the 5th pad in second substrate towards 23 side of chovr body.Second chip 223 and second substrate 222
Between be further provided with third salient point 225, second substrate 222 is provided with and third salient point 225 close to 223 side of the second chip
Corresponding 6th pad 226, third salient point 225 and the 6th pad 226 are connected, so that the second chip 223 and the second base
Plate 222 connects.
Wherein, the 4th pad 232, the 5th pad 221, the 6th pad 226 and the first pad 216 above-mentioned, the second pad
217, third pad 231 etc. is similar and welding manner between the 4th pad 232, the 5th pad 221 and the second salient point 25,
Welding manner between 6th pad 226 and third salient point 225 is also between 231 and first salient point 214 of aforementioned third pad
Welding manner is similar, and related detailed content please refers to above, and details are not described herein again.
It should be pointed out that the platform as the second salient point 25 of carrying, the setting of chovr body 23 increase the second salient point 25
Carrying platform area so that when preparing the chip packing-body, on the one hand, can increase by the second salient point according to demand
25 quantity；On the other hand, the spacing between each second salient point 25 can also be increased, to reduce between each second salient point 25
The probability bridged improves the total quality of chip packing-body.In addition, the setting of chovr body 23 also makes the first plastic-sealed body
213 " clampings " are between first substrate 211 and chovr body 23, to reduce the probability of 213 warpage of the first plastic-sealed body.
Optionally, first substrate 211 is provided with backwards to 212 side of the first chip：7th pad 219, chip packing-body is also
Including the 4th salient point 26 corresponding with the 7th pad 219, the 7th pad 219 and the 4th salient point 26 are connected, and are used for core
Piece packaging body is connect with extraneous device.
It should be pointed out that the electrical components in the second packaging body 22, such as the second chip, by the second salient point 25 and switching
Body 23 connects, and further passes through the first salient point 214, the first chip 212, bonding wire 218 and the 4th salient point 26 and extraneous device
Connection.The circuit pathways that first chip, 212 inside the second packaging body 22 of setting is connect with the 4th salient point 26, and the second packaging body 22
The not direct interconnection between the first chip 212.It certainly, can also be by above-mentioned access by first according to actual use demand
Chip 212 links together with the second chip 223.
Also referring to Fig. 5 to Figure 12, in one embodiment of preparation method of chip packing-body of the present invention, the chip package
Body includes the first packaging body 21 being stacked and the second packaging body 22, this method include：
Step S101：First chip 212 is arranged on first substrate 211, wherein the first chip 212 is backwards to the first base
211 side of plate is provided with the first salient point 214.
Specifically, Fig. 5 is please referred to Fig. 8.First chip 212 is provided, the first salient point 214 is set on the first chip 212,
First pad 216 is set in the side for being provided with the first salient point 214, and setting is right with the first pad 216 on first substrate 211
The second pad 217 answered.
Then side that first chip 212 is not provided with to the first salient point 214 is mounted on first by the first adhesive-layer 215
On substrate 211.After the completion of attachment, bonding wire 218 is used as by the first pad 216 and corresponding second pad by high-purity spun gold
217 connections, to realize the connection of the first chip 212 and first substrate 211, and then to realize that the first chip 212 passes through the first base
Plate 211 and the connection of extraneous device provide access.
Step S102：First plastic packaging is formed backwards to 211 side of first substrate in the first chip 212 using pressing Shooting Technique
Body 213, wherein the first salient point 214 is connected to the outside of the first plastic-sealed body 213；
It should be pointed out that due in step S101, the first chip 212 is mounted away from the side of the first salient point 214
On first substrate 211, that is to say, that the first salient point 214 is located at the first chip 212 backwards to 211 one end of first substrate, at this point,
The first chip of pressing Shooting Technique pair 212 may be used and carry out plastic packaging to encapsulate the first chip 212, to form the first plastic-sealed body
213, referring specifically to Fig. 9.Wherein, the height of the first plastic-sealed body 213 can be higher than, be equal to or less than the first salient point 214, this reality
It applies in mode, the height of the first plastic-sealed body 213 is higher than the first salient point 214.
Step S103：First plastic-sealed body 213 is handled, is formed and is connected to corresponding first salient point, 214 (i.e. the first salient point
214 basal parts 2141) hole, and extension 2142 is formed in hole, one end of extension 2142 connect with basal part 2141, separately
One end is connected to the outside of the first plastic-sealed body 213.
Specifically, it is formed and is connected in the position corresponding to the first salient point 214 (i.e. basal part 2141) using laser drilling processes
Lead to the hole of corresponding first salient point 214.Then it is injected by metal or the modes such as printing forms extension 2142 in hole,
One end of extension 2142 is connect with basal part 2141, and the other end is connected to the outside of the first plastic-sealed body 213, so as into one
Step is connect with the second packaging body, as shown in Figure 10.
It should be pointed out that being handled to the first plastic-sealed body 213 the first salient point 214 is connected to the first plastic-sealed body
When 213 outside, the modes such as polishing, polishing can also be used, are not specifically limited herein.
Step S104：By chovr body 23 by the way that the second adhesive-layer 24 in 213 side of the first plastic-sealed body, and connection is arranged
The first salient point 214 outside to the first plastic-sealed body 213 is mounted and is welded respectively.
Specifically, a chovr body 23 is provided, third pad corresponding with the first salient point 214 is set in 23 side of chovr body
231.Wherein, the sequence for providing the second adhesive-layer 24 of chovr body 23 and setting third pad 231 and setting is not specifically limited.
Welding between first salient point 214 and third pad 231 can be realized by solder reflow process.I.e. by chovr body 23
Third pad 231 and the contraposition of the first salient point 214 after, be put into togerther in reflow ovens and carry out Reflow Soldering, to realize the first salient point
Connection between 214 and third pad 231.Specifically refer to Figure 11.
In an application scenarios, in order to ensure chovr body 23 contacts well with the first salient point 214,23 quilt of chovr body is avoided
Third pad 231 on chovr body 23 can be designed as the third weldering of groove-like by the case where 214 part of the first salient point jacks up
Disk 231, it is specific as shown in Figure 4.In this way when being welded, the top of the first salient point 214 can be accommodated in the groove-like
In third pad 231, to realize that chovr body 23 is contacted with the good of the first solder joint.
Step S105：The second packaging body 22 is set backwards to 211 side of first substrate in the first plastic-sealed body 213, so that the
Two packaging bodies 22 are connect by the first salient point 214 with the first packaging body 21, and chip packing-body is formed.
Specifically, second chip is set by the way of upside-down mounting on the second substrate 222 for constituting the second packaging body 22
223, that is, so that the third salient point 225 being arranged on the second chip 223 is towards 222 side of second substrate, and in first substrate 211
Third salient point 225 is corresponded to towards 223 side of the second chip, the 6th pad 226 is set, and make second using solder reflow process
Chip 223 is welded on by third salient point 225 on second substrate 222, then by injection molding, such as modes such as underfill,
Second substrate 222 forms the second plastic-sealed body 224 towards 223 side of the second chip, encapsulate the second chip 223, to formation the
Two packaging bodies 22, as shown in figure 12.
It should be pointed out that in application scenes, when forming the second packaging body 22, can also use similar to the
The mode of one packaging body 21, by the second chip 223 by the second chip 223 and second substrate 222 in such a way that bonding wire 218 connects
Connection.At this point, when forming the second plastic-sealed body 224, the mode of pressing injection molding can be used.
After forming the second packaging body 22, the second packaging body 22 is connect by the second salient point 25 with connector 23.Specifically
The 5th pad 221 corresponding with the second salient point 25 is set backwards to 223 side of the second chip in second substrate 222, and in connector
23 are arranged the 4th pad 232 corresponding with the second salient point 25 backwards to 21 side of the first packaging body, then pass through solder reflow process
Second salient point 25 is connected with corresponding 4th pad 232 and the 5th pad 221 respectively, to realize the second packaging body 22 and the
The connection of one packaging body 21.
Further, the 7th pad is set backwards to 212 side of the first chip in the first substrate 211 of the first packaging body 21
219, and the 7th pad 219 the 4th salient point 26 of mating connection is further corresponded to, chip packing-body is connect with extraneous device, into
And complete the preparation of chip packing-body.
Wherein, in one embodiment, step S103, step S104 it is not necessary to, specifically can be according to actual demand
It is prepared using method appropriate, is not specifically limited in present embodiment.
It is noted that by the first face-up setting of chip 212 in present embodiment so that carrying out chip packing-body
Encapsulation when, the first salient point 214 can be arranged in the first chip 212 upward backwards to the side of first substrate 211, to formed
Reduction generates the risk of hole due to the injection molding manner using underfill when the first plastic-sealed body 213, improves chip packing-body
Quality；In turn, in injection molding, without considering the preset space problem between the first chip 212 and the first packaging body and chip,
So as to reduce the thickness of chip packing-body to a certain extent, to reduce the thickness of the first plastic-sealed body 213, be conducive to save
The about space of subsequent product.Meanwhile the setting of chovr body 23 increases the area of the carrying platform of the second salient point 25, so that
When preparing the chip packing-body, on the one hand, the quantity of the second salient point 25 can be increased according to demand；It on the other hand, can be with
Increase the spacing between each second salient point 25, to reduce the probability bridged between each second salient point 25, improves chip
The total quality of packaging body.In addition, the setting of chovr body 23 also make the first plastic-sealed body 213 " clamping " first substrate 211 with
Between chovr body 23, to reduce the probability of 213 warpage of the first plastic-sealed body.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, every to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (13)
1. a kind of chip packing-body, the chip packing-body includes the first packaging body and the second packaging body being stacked, special
Sign is that first packaging body includes：
First substrate；
First chip, first chip are arranged on the first substrate between second packaging body, first core
Piece one side is equipped with the first salient point as port, and first salient point is arranged in first chip backwards to the first substrate one
Side；
First plastic-sealed body, first plastic-sealed body are arranged in the side that the first substrate has first chip, for wrapping
Seal first chip；
Wherein, first salient point is connected to the outside of first plastic-sealed body, for described backwards in first plastic-sealed body
First substrate side is connect with element in second packaging body.
2. chip packing-body according to claim 1, which is characterized in that
Direction first chip-side of the first substrate is provided with the first pad；
First chip is provided with the second pad corresponding with first pad backwards to the first substrate side；
First packaging body further comprises：Bonding wire, described bonding wire one end connect first pad, described in other end connection
Second pad is connected with being established between the chip and the substrate.
3. chip packing-body according to claim 1, which is characterized in that first salient point includes：
Basal part, the basal part are arranged in the inside of the plastic-sealed body；
Extension, the extension is at least partially disposed in the outside of the plastic-sealed body, and one end is connect with the basal part, separately
One end with element in second packaging body for connecting.
4. chip packing-body according to claim 1, which is characterized in that first packaging body further comprises：
First adhesive-layer, first adhesive-layer are arranged between the first substrate and first chip, and being used for will be described
First chip attachment is on the first substrate.
5. chip packing-body according to any one of claims 1 to 4, which is characterized in that the chip packing-body is further
Including：
Chovr body, the chovr body are arranged between first packaging body and second packaging body, for connecting described the
One packaging body and second packaging body.
6. chip packing-body according to claim 5, which is characterized in that the chovr body is towards first packaging body one
Side is provided with：
Third pad, the third pad correspond to the first salient point setting, for being connected with first salient point.
7. chip packing-body according to claim 6, which is characterized in that the third pad is groove type, groove type
The third pad is for the corresponding part being arranged outside first plastic-sealed body for housing first salient point.
8. chip packing-body according to claim 5, which is characterized in that the chip packing-body further comprises：
Second salient point, second salient point are arranged between second packaging body and the chovr body；
The chovr body is provided with towards second packaging body side：4th pad, the 4th pad correspond to described second
Salient point is arranged；
Second packaging body is provided with towards the chovr body side：5th pad, the 5th pad correspond to described second
Salient point is arranged；
Wherein, second salient point is connected with the 4th pad, the 5th pad respectively, so that second envelope
Dress body is connect by the chovr body with first packaging body.
9. chip packing-body according to claim 8, which is characterized in that second packaging body includes：Second substrate,
Two chips and the second plastic-sealed body；
Wherein, second chip is arranged in the second substrate backwards to first packaging body side, second plastic-sealed body
It is arranged in the side that the second substrate has second chip, for encapsulating second chip；
5th pad setting is in the second substrate towards the chovr body side；
Third salient point is further provided between second chip and the second substrate, the second substrate is close to described
Two chip-sides are provided with the 6th pad corresponding with the third salient point, and the third salient point connects with the 6th pad cooperation
It connects, so that second chip is connect with the second substrate.
10. chip packing-body according to claim 5, which is characterized in that the chip packing-body further comprises：Second
Adhesive-layer；
The side between the chovr body and first plastic-sealed body is arranged in second adhesive-layer, is used for the chovr body
First plastic-sealed body is mounted on backwards to the side of the first substrate, and between the chovr body and first plastic-sealed body
Center is left a blank, corresponding first chip position in the place of leaving a blank.
11. chip packing-body according to claim 5, which is characterized in that the rigidity or intensity of the chovr body are more than institute
State the rigidity or intensity of the first plastic-sealed body.
12. chip packing-body according to claim 1, which is characterized in that the first substrate is backwards to first chip
Side is provided with：7th pad；
The chip packing-body further includes the 4th salient point corresponding with the 7th pad；
7th pad is connected with the 4th salient point, for the chip packing-body to be connect with extraneous device.
13. a kind of preparation method of chip packing-body, the chip packing-body includes the first packaging body and second being stacked
Packaging body, which is characterized in that the method includes：
On the first substrate by the setting of the first chip, wherein first chip is provided with the backwards to the first substrate side
One salient point；
First plastic-sealed body is formed backwards to the first substrate side in first chip using pressing Shooting Technique, wherein institute
State the outside that the first salient point is connected to first plastic-sealed body；
Second packaging body is set backwards to the substrate side in first plastic-sealed body, so that second packaging body is logical
It crosses first salient point to connect with first packaging body, to form the chip packing-body.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711438778.0A CN108288608B (en) | 2017-12-25 | 2017-12-25 | Chip package and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711438778.0A CN108288608B (en) | 2017-12-25 | 2017-12-25 | Chip package and preparation method thereof |
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| KR100842915B1 (en) * | 2007-01-17 | 2008-07-02 | 주식회사 하이닉스반도체 | Stack package and manufacturing method of the same |
| CN102569275A (en) * | 2011-12-28 | 2012-07-11 | 三星半导体(中国)研究开发有限公司 | Stacking type semiconductor packaging structure and manufacturing method thereof |
| CN103794595A (en) * | 2014-01-24 | 2014-05-14 | 清华大学 | POP packaging structure and packaging method thereof |
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| CN206179848U (en) * | 2016-08-16 | 2017-05-17 | 深圳市中兴微电子技术有限公司 | PoP stacked package structure |
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- 2017-12-25 CN CN201711438778.0A patent/CN108288608B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100842915B1 (en) * | 2007-01-17 | 2008-07-02 | 주식회사 하이닉스반도체 | Stack package and manufacturing method of the same |
| CN102569275A (en) * | 2011-12-28 | 2012-07-11 | 三星半导体(中国)研究开发有限公司 | Stacking type semiconductor packaging structure and manufacturing method thereof |
| CN103794595A (en) * | 2014-01-24 | 2014-05-14 | 清华大学 | POP packaging structure and packaging method thereof |
| CN104465611A (en) * | 2014-12-10 | 2015-03-25 | 华进半导体封装先导技术研发中心有限公司 | Array type solder ball arrangement packaging structure for achieving PoP interconnection and manufacturing method of array type solder ball arrangement packaging structure for achieving PoP interconnection |
| CN206179848U (en) * | 2016-08-16 | 2017-05-17 | 深圳市中兴微电子技术有限公司 | PoP stacked package structure |
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