KR20050094739A - Memory module - Google Patents

Abstract

A memory module is disclosed. A memory module according to an embodiment of the present invention includes a plurality of memory chips, a first module NC pin, and a second module NC pin. The first module NC pin receives a test mode signal and applies it to a first NC (No Connection) pin of each of the memory chips. The second module NC pin receives a test result signal indicating whether the memory chip is a defective chip or a normal chip from the second NC pin of each of the memory chips. Each of the memory chips simultaneously tests different internal memory blocks, outputs the test result signal through the second NC pin, and outputs test data of one of the different memory blocks. Each of the memory chips tests N bits of memory cells and outputs the test data corresponding to N / 2 bits of memory cells. The different memory blocks are arranged in the same bank. The memory module according to the present invention is suitable for a mounting test by rereading the written test data and has an advantage of reducing test time.

Description

Memory module

The present invention relates to a memory module, and more particularly, to a memory module having a memory structure capable of simultaneously testing two or more memory cells in the same bank.

1 is a diagram illustrating a parallel test apparatus of a conventional semiconductor memory device.

The parallel test apparatus 100 of a conventional semiconductor memory device includes a memory bank 10, an amplifier block 20, a global input / output line GIO, a comparison unit 30, and an output buffer unit 40. The amplifier block 20 amplifies data received from each memory cell of the memory bank 10.

The amplified data is applied to the comparator 30 through the global input / output line GIO, and the comparator 30 compares the data and outputs the result. The comparator 30 includes exclusive logical OR means (not shown), and the exclusive logical OR means respectively receive and compare four bits of data selected by the column lines CD0 to CD3.

If the data are all the same, the exclusive OR means output a logic "0", and if any one data is different from the other three data, the exclusive OR means output a logic "1".

The output of the exclusive OR means output from the comparing unit 30 is applied to an external test device (not shown) through the output buffer unit 40, and the test device determines whether the memory cell is defective or normal.

As described above, the conventional parallel test apparatus 100 reads data of a memory cell of a specific bank through a general read operation and performs a test, and the number of data that can be read at a time in a general read operation is limited.

Therefore, there is a problem in that test time and test cost in the package increase as the memory density increases.

In addition, the mounting test in the production department that produces the memory product should read out the test data written in the memory cell for the test as it is and output it simultaneously to all the output pads (not shown). There is a problem that one test data cannot be read as it is.

An object of the present invention is to provide a memory module having a structure capable of simultaneously testing two or more memory cells of the same bank.

In order to achieve the above technical problem, a memory module includes a plurality of memory chips, a first module NC pin, and a second module NC pin.

The first module NC pin receives a test mode signal and applies it to a first NC (No Connection) pin of each of the memory chips. The second module NC pin receives a test result signal indicating whether the memory chip is a defective chip or a normal chip from the second NC pin of each of the memory chips.

Each of the memory chips simultaneously tests different internal memory blocks, outputs the test result signal through the second NC pin, and outputs test data of one of the different memory blocks.

Each of the memory chips tests N bits of memory cells and outputs the test data corresponding to N / 2 bits of memory cells. The different memory blocks are arranged in the same bank.

The test mode signal is generated by a mode register set (MRS). Or the test mode signal is a DC voltage having a constant voltage level.

Each of the memory chips includes first and second memory blocks, a sense amplifier, and a comparator.

The sense amplifier amplifies and outputs test data written to the first and second memory blocks. The comparison unit generates the test result signal by comparing whether the test data of the first memory block and the test data of the second memory block corresponding to the test data are the same or different, and generate the test result signal. Output test data.

The comparing section has first comparing means and second comparing means. First comparing means compares test data of the second memory block corresponding to the test data with any test data of the first memory block.

Second comparison means compare the outputs of the first comparison means to generate the test result signal. The first and second comparing means may be exclusive OR GATE.

If the test result signal is the first level, the memory chip generating the test result signal is a defective chip, and if the test level signal is the second level, the memory chip generating the test result signal is a normal chip.

According to another aspect of the present invention, a memory module includes a plurality of memory chips and a first module NC pin.

The first module NC pin receives a test mode signal and applies it to a first NC (No Connection) pin of each of the memory chips. Each of the memory chips simultaneously tests different memory blocks therein, and if each memory chip is a normal chip, outputs test data of one of the different memory blocks, and outputs a defect signal if the chip is defective. do.

Each of the memory chips includes first and second memory blocks, a sense amplifier, and a comparator.

The sense amplifier amplifies and outputs test data written to the first and second memory blocks. The comparison unit compares the test data of the first memory block with the test data of the second memory block corresponding to the test data, whether the test data is the same or different, and outputs the test data in response to a comparison result, or the defect. Output the signal.

The comparison section includes first comparison means and output sections.

First comparing means compares test data of the second memory block corresponding to the test data with any test data of the first memory block.

Outputs generate the defect signal if the output of the first comparison means is at a first level and generate the test data if the output of the first comparison means is at a second level.

The output units each include PMOS transistors that output the test data in response to the first comparison means, and NMOS transistors that output the defect signal in response to the first comparison means.

The fault signal is a power supply voltage level or a ground voltage level or has a constant voltage level.

According to another aspect of the present invention, a semiconductor memory device may store at least one first memory block, at least one second memory block, and at least one first memory block in a test mode. And a comparison unit configured to generate a test result signal by comparing test data with test data stored in the at least one second memory block.

The comparison unit outputs one of test data stored in the first memory block and test data stored in the second memory block when the test data stored in the first memory block and the test data stored in the second memory block are the same.

According to another aspect of the present invention, a memory module includes a first module NC pin configured to receive a plurality of memory chips and a test mode signal and apply the same to a first NC pin of each of the memory chips. It is provided.

Each of the memory chips simultaneously tests different memory blocks therein and outputs test data of one memory block among the different memory blocks if the tested memory chip is a normal chip.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a diagram illustrating a memory module according to an exemplary embodiment of the present invention.

FIG. 3A is a diagram illustrating a case where the memory chip of FIG. 2 has a pin structure.

FIG. 3B is a diagram illustrating a case in which the memory chip of FIG. 2 has a ball structure.

2 and 3, a memory module 200 according to an embodiment of the present invention may include a plurality of memory chips CP1, CP2 to CPn, a first module NC pin M_NC1, and a second module NC pin M_NC2. ).

The first module NC pin M_NC1 receives the test mode signal TMODE and applies the test mode signal TMODE to the first NC pin No_P1 of each of the memory chips CP1 and CP2 to CPn. The second module NC pin M_NC2 receives a test result signal TRST indicating whether the memory chip is a defective chip or a normal chip from the second NC pin P_NC2 of each of the memory chips CP1, CP2 to CPn.

Each of the memory chips CP1 and CP2 to CPn simultaneously tests different memory blocks (not shown) and outputs a test result signal TRST through the second NC pin P_NC2, among the different memory blocks. Outputs test data of one memory block.

According to the present invention, a memory cell is tested by performing a write and read operation on the memory cells at a time by enabling a word line from two or more memory blocks of the same bank more than twice the normal test method. The test time is reduced by increasing the number of these more than twice as compared to the conventional.

The test mode signal TMODE is a first NC pin P_NC1 of each of the memory chips CP1, CP2 to CPn through the first module NC pin M_NC1 when testing the memory chips mounted in the memory module 200. Is applied. Each of the memory chips CP1 and CP2 to CPn simultaneously tests two or more memory cells (not shown) of different memory blocks within the same bank.

That is, test data is simultaneously written to two or more memory cells (not shown). The written test data is output to an output pin (not shown) of the memory module 200 through an output pin (not shown) of each of the memory chips CP1 and CP2 to CPn by a read operation.

In addition, a test result signal TRST having information on whether the memory chips CP1, CP2 to CPn are defective chips or a normal chip, in addition to outputting the test data is a second NC of the memory chips CP1, CP2 to CPn. It is output to the second module NC pin M_NC2 of the memory module 200 through the pin P_NC2. The test operation of each of the memory chips CP1 and CP2 to CPn will be described later.

The memory module 200 of FIG. 2 performs the aforementioned test operation when the activated test mode signal TMODE is input, and performs a normal test operation in which one memory cell is tested at a time when the test mode signal TMODE is deactivated. do.

The test mode signal TMODE may be generated by a mode register set (MRS). That is, when a preset MRS is generated, the memory module 200 performs the test operation described above.

In addition, the test mode signal TMODE may be a DC voltage having a constant voltage level. That is, when the high level voltage of 5V is applied to the first NC pin P_NC1 of each of the memory chips CP1 and CP2 to CPn, the memory chips CP1 and CP2 to CPn of the memory module 200 are described in the above-described test operation. Do this. When the low level voltage of 0V is applied to the first NC pin P_NC1, the memory chips CP1 and CP2 to CPn perform a normal test operation.

4 is a circuit diagram illustrating an internal structure of the memory chip of FIG. 2 according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the memory chip 400 includes first and second memory blocks 410 and 420, a sense amplifier 430, and a comparator 440.

Since the memory modules 200 of FIG. 2 are equipped with a plurality of memory chips CP1, CP2 to CPn and all have the same internal structure, only the internal structure of one memory chip will be described for convenience of description. The memory chip 400 is one memory chip among the memory chips CP1 and CP2 to CPn.

The memory chip 400 simultaneously tests different memory blocks therein, outputs a test result signal TRST through the second NC pin P_NC2, and tests test data of one memory block among the different memory blocks. Output

The internal memory of the memory chip 400 is divided into a plurality of banks (not shown). One bank has a plurality of memory blocks. 4, only first and second memory blocks 410 and 420 of the plurality of memory blocks are shown.

The memory blocks may be x4 memory blocks that output 4 bits of data at a time, x8 memory blocks that output 8 bits of data at a time, or x16 memory blocks that output 16 bits of data at a time.

The memory blocks in the memory chip 400 according to the embodiment of the present invention include both x4 memory blocks and x8 memory blocks or x16 memory blocks. The first and second memory blocks 410 and 420 illustrated in FIG. 4 are shown as x8 memory blocks for convenience of description.

The sense amplifier 430 amplifies and outputs test data TD11 to TD18 and TD21 to TD28 written in the first and second memory blocks 410 and 420. The comparison unit 440 compares the test data of the first memory block 410 with the test data of the second memory block 420 corresponding to the test data, whether the test data is identical or different. Is generated, and the test data TD11, TD12 to TD17, and TD18 of the first memory block 410 are output.

When the test mode signal TMODE is input to the first NC pin P_NC1 of the memory chip 400 through the first module NC pin M_NC1, more than twice the word lines are activated than in a normal test operation. Test data is simultaneously written to the first and second memory blocks 410 and 420 by 8 bits, respectively.

The first and second memory blocks 410 and 420 apply the test data TD11 to TD18 and TD21 to TD28 to the sense amplifier 430 through corresponding data input / output lines, and the sense amplifier 430 transmits the test data ( TD11 to TD18 and TD21 to TD28 are amplified to a complementary metal-oxide semiconductor (CMOS) level and output.

The memory chip 400 tests N bits of memory cells and outputs test data corresponding to N / 2 bits of memory cells. That is, in FIG. 4, 16 bit memory cells of the first and second memory blocks 410 and 420 are simultaneously tested, but only 8 bit test data of the first memory block 410 is output. This will be described later.

The comparison unit 440 includes first comparison means XOR11 to XOR18 and second comparison means XOR21, XOR22, and XOR23. The first comparison means XOR11 to XOR18 compare the test data of the second memory block 420 corresponding to the test data with any test data of the first memory block 410.

The second comparison means XOR21, XOR22, and XOR23 compare the outputs of the first comparison means XOR11 to XOR18 to generate a test result signal TRST. The first and second comparison means XOR11 to XOR18, XOR21, XOR22, and XOR23 may be exclusive logical OR means.

The test data TD11 to TD18 and TD21 to TD28 written in the first and second memory blocks 410 and 420 are output to the sense amplifier 430. The first comparison means XOR11 to XOR18 of the comparator 440 are exclusive logical OR means. The first comparison means XOR11 to XOR18 compare the test data of the first memory block 410 with the test data of the second memory block 420 corresponding to the test data.

That is, the first exclusive OR means XOR11 compares the first test data TD11 output from the first memory block 410 and the first test data TD21 output from the second memory block 420. If the two first test data TD11 and TD21 are identical to each other, the first exclusive OR means XOR11 outputs “0” and, if different from each other, outputs “1”.

The second exclusive OR means XOR12 compares the second test data TD12 output from the first memory block 410 with the second test data TD22 output from the second memory block 420. If the two second test data TD12 and TD22 are equal to each other, the second exclusive OR means outputs "0" and if it is different from each other, outputs "1".

This operation is performed in all of the first comparison means XOR11 to XOR18. The same test data is written to test the first and second memory blocks 410 and 420 simultaneously. Therefore, when the values output from the first comparison means XOR11 to XOR18 are all “0”, it can be seen that the first and second memory blocks 410 and 420 are normal chips.

If any one of the values output from the first comparison means XOR11 to XOR18 is "1", it can be seen that the memory chip including the first and second memory blocks 410 and 420 is a defective chip.

The second comparison means XOR21, XOR22, and XOR23 compare the outputs of the first comparison means XOR11 to XOR18. The second comparison means XOR21, XOR22, XOR23 have three exclusive ORs. The exclusive OR means XOR21 compares the outputs of the first to fourth exclusive OR means XOR11, XOR12, XOR13, and XOR14 that are the first comparison means XOR11 to XOR18.

The exclusive OR means XOR22 compares the outputs of the fifth to eighth exclusive OR means XOR15, XOR16, XOR17, and XOR18 that are the first comparison means XOR11 to XOR18. The exclusive OR means XOR23 compares the outputs of the exclusive AND means XOR21 and XOR22 and outputs a test result signal TRST.

If the outputs of the first to fourth exclusive OR means XOR11, XOR12, XOR13, and XOR14 are all equal to " 0 ", the output of the exclusive OR means XOR21 is also " 0 ". However, if any one of the outputs of the first to fourth exclusive OR means XOR11, XOR12, XOR13, and XOR14 is "1", then the output of exclusive OR means XOR21 is also "1".

The second comparison means XOR21, XOR22, and XOR23 are means for outputting a test result signal TRST indicating whether the memory chip 400 is a defective chip or a normal chip. That is, if any one of the outputs of the first comparison means XOR11 to XOR18 has "1", the test result signal TRST output from the exclusive OR means XOR23 also becomes "1".

The second comparison means XOR21, XOR22, and XOR23 output the test result signal TRST as "1" when any one of the outputs of the first comparison means XOR11 to XOR18 is present, and the first. If the outputs of the comparison means XOR11 to XOR18 are all "0", the test result signal TRST is output as "0".

If the test result signal TRST is "1", the memory chip 400 generating the test result signal TRST is a defective chip, and if the test result signal TRST is "0", the memory chip 400 generating the test result signal TRST is a normal chip. to be. The test result signal TRST is output to the first module NC pin M_NC1 of the memory module 200 through the first NC pin P_NC1 of the memory chip 400.

The comparator 440 also outputs test data TD11, TD12 ˜ TD17, and TD18 of the first memory block 410. Although the conventional parallel test apparatus 100 may determine whether the memory chip is a defective chip or a normal chip, the memory module 200 may read the test data as it is and analyze it externally.

The comparator 440 may include the first memory block 410 before the test data TD11, TD12 ˜ TD17, and TD18 output from the first memory block 410 are applied to the first comparison means XOR11 ˜ XOR18. The test data of the TD11, TD12 ~ TD17, TD18 is output through an external output pin (not shown).

The test data output outside the memory chip 400 is the test data TD11, TD12 ˜ TD17, and TD18 of the first memory block 410, but inside the memory chip 400, the first and second memory blocks 410, 420 is tested at the same time.

Although only the first and second memory blocks 410 and 420 are shown in the memory chip 400 of FIG. Can be.

Even when N-bit memory cells in the memory chip 400 are tested at a time, N / 2-bit test data is output to the outside. In other words, N-bit memory cells may be tested using a test device (not shown) capable of testing N / 2-bit memory cells at a time.

In more detail, a 512MB memory chip having an internal structure according to an embodiment of the present invention may be tested using a 256MB test apparatus. Thus, test time can be reduced.

5 is a circuit diagram illustrating an internal structure of a memory chip of FIG. 2 according to another exemplary embodiment of the present invention.

A memory module (not shown) on which a memory chip having the internal structure of FIG. 5 is mounted includes a first module NC pin (not shown). The first module NC pin performs the same function as the first module NC pin M_NC1 of the memory module 200 of FIG. 2. That is, the test mode signal TMODE is applied to the memory chips having the structure of FIG. 5.

However, unlike the memory module 200 of FIG. 2, the memory module having the memory chip having the internal structure of FIG. 5 does not include the second module NC pin M_NC2. The second module NC pin M_NC2 of the memory module 200 of FIG. 2 outputs a test result signal TRST. However, the memory module in which the memory chip having the internal structure of FIG. 5 is mounted does not output a test result signal.

The memory chip 500 having the internal structure of FIG. 5 has a difference in circuit configuration and operation of the memory chip 400 and the comparator 540 of FIG. 4. Therefore, the circuit configuration and operation of the comparator 540 will be described.

When the memory chip 500 having the internal structure of FIG. 5 is a normal chip, the memory chip 500 includes test data TD11, TD12 ˜ TD17, and TD18 of the first memory block 510 through output pins (not shown). Outputs When the memory chip 500 is a defect chip, the memory chip 500 outputs a defect signal FS through output pins (not shown).

The fault signal FS has a power supply voltage level or a ground voltage level or has a constant voltage level.

The comparison unit 540 compares the test data of the first memory block 510 with the test data of the second memory block 520 corresponding to the test data, whether the test data is the same or different, and responds to the comparison result. Data is output or a fault signal FS is output.

The comparison unit 540 includes first comparison means XOR11 to XOR18 and output units OUT1 and OUT2 to OUT8. The first comparison means XOR11 to XOR18 compare the test data of the first memory block 510 with the test data of the second memory block 520 corresponding to the test data.

The output parts OUT1 and OUT2 to OUT8 generate a defect signal FS when the output of the first comparison means XOR11 to XOR18 is at the first level, and the output of the first comparison means XOR11 to XOR18 is second. At the level, test data TD11 to TD18 output from the first memory block 410 is generated.

Since the first comparison means XOR11 to XOR18 have the same function as the first comparison means XOR11 to XOR18 of the memory chip 400 of FIG. 4, description thereof is omitted.

If the memory chip 500 is a normal chip, the first comparison means XOR11 to XOR18 output "0", and if the defective chip is a defective chip, the first comparison means XOR11 to XOR18 output "1". The outputs of the first comparison means XOR11 to XOR18 are applied to the corresponding output parts OUT1 and OUT2 to OUT8.

The output parts OUT1 to OUT8 are PMOS transistors PTR for outputting test data in response to the outputs of the corresponding first comparison means XOR11 to XOR18 and the first comparison means XOR11 to XOR18. In response to the NMOS transistors NTR to output the defect signal FS.

Referring to the first output unit OUT1 of the output units OUT1 and OUT2 to OUT8, the first stage of the PMOS transistor PTR is the first memory block 510 among the input stages of the first exclusive OR unit XOR11. The first test data TD11 output from is connected to an input terminal to which the first test data TD11 is applied, and the first test data TD11 of the first memory block 510 is output to the second terminal.

The defect signal FS is applied to the first terminal of the NMOS transistor NTR, and the defect signal FS is output to the second terminal according to the logic level of the gate. The output of the first exclusive OR means XOR11 is applied to the gates of the PMOS transistor PTR and the NMOS transistor NTR.

When the output of the first exclusive-OR means XOR11 is "0", the PMOS transistor PTR is turned on and the first test data TD11 output from the first memory block 510 is output. When the output of the first exclusive-OR means XOR11 is "1", the NMOS transistor NTR is turned on to output the defect signal FS.

The same operation is performed on the remaining output units OUT2 to OUT8. Therefore, when the outputs of the output parts OUT1 and OUT2 to OUT8 are the test data TD11 to TD18 output from the first memory block 510, the memory chip 500 is a normal chip and the defect signal FS is output. The memory chip 500 is a defective chip.

Although the memory chip 500 of FIG. 5 also internally tests N-bit memory cells at a time, the output test data is N / 2 bits.

That is, since a test device (not shown) capable of testing N / 2-bit memory cells can be used to test N-bit memory cells, test time can be reduced and test data written for testing memory cells. Has the advantage of being read out again.

6 is a diagram illustrating a memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 6, a memory device 600 according to another embodiment of the present invention includes a plurality of memory banks BANK1 to BANK8. Each memory bank stores or outputs data using a corresponding column decoder CD, column fuse CF, row decoder RD, and a Lars control unit RC.

In FIG. 6, only eight memory banks BANK1 to BANK8 are illustrated, but are not limited thereto. The column decoder CD, the column fuse CF, the row decoder RD, and the las control unit may be disposed in the memory banks BANK1 to BANK8. The operation of storing data into the memory banks BANK1 to BANK8 by the operation of RC is omitted since it can be understood by those skilled in the art.

The semiconductor memory device 600 according to an exemplary embodiment of the present invention includes at least one first memory block 610, at least one second memory block 620, and a comparator 630. When the semiconductor memory device 600 is in the test mode, the comparator 630 stores the test data TD11 to TD18 stored in the at least one first memory block 610 and the at least one second memory block 620. A test result signal is generated by comparing whether the test data TD21 to TD28 are the same or different.

The comparison unit 630 may store the first data block 610 in the first memory block 610 if the test data TD11 ˜ TD18 and the test data TD21 ˜ TD28 stored in the second memory block 620 are the same. One of the stored test data TD11 to TD18 and the test data TD21 to TD28 stored in the second memory block 620 is output through the output pad DQP.

The test result signal TRST is generated at the first level when the test data TD11 to TD18 stored in the first memory block 610 and the test data TD21 to TD28 stored in the second memory block 620 are not the same. do.

In contrast, the test result signal TRST is generated at the second level when the test data TD11 to TD18 stored in the first memory block 610 and the test data TD21 to TD28 stored in the second memory block 620 are the same. do.

If the test result signal TRST is the first level, the memory device 600 that generates the test result signal TRST is a defective memory chip, and if the test level signal TRST is the second level, the memory device 600 generates the test result signal TRST. It is a normal memory chip.

The first memory block 610 and the second memory block 620 may be disposed in the same memory bank or may be disposed in separate memory banks, respectively. FIG. 6 illustrates that the first memory block 610 and the second memory block 620 are disposed in different memory banks.

The first memory block 610, the second memory block 620, and the comparator 630 illustrated in FIG. 6 may include the first memory block of the memory chip 400 according to the embodiment of the present invention illustrated in FIG. 4. 410, the second memory block 420, and the comparator 440 have the same function.

That is, the same test data is written in the first memory block 610 and the second memory block 620, and the test data TD11 to TD18, which are output from the first memory block 610 and the second memory block 620, If the test data is not the same by comparing the TD21 to TD28, the memory device 600 is recognized as a memory chip in which a defect exists.

In addition, the first memory block 610, the second memory block 620, and the comparator 630 illustrated in FIG. 6 are the first memory of the memory chip 400 according to the exemplary embodiment of the present invention illustrated in FIG. 4. The block 410, the second memory block 420, and the comparator 440 have the same structure.

That is, the comparator 630 of FIG. 6 also includes first comparison means (not shown) and second comparison means (not shown) which are constituted by exclusive OR. Since the operation of the comparison unit 630 of FIG. 6 has been described above, a detailed description thereof will be omitted.

Like the memory chip 400 of FIG. 4, the memory device 600 of FIG. 6 amplifies and applies test data written to at least one of the first and second memory blocks 610 and 620 to the comparator 630. A sense amplifier may be further provided.

The memory chip 400 of FIG. 4 outputs the test result signal TRST to the outside of the memory chip 400, and a user of the memory chip 400 recognizes the test result signal TRST to be output to the outside. ) Is a defective chip or not.

However, the memory device 600 of FIG. 6 does not output the test result signal TRST output from the comparator 630 to the outside of the memory device 600. Instead, when the logic level of the test result signal TRST is generated as the first level, that is, when the memory device 600 is a defective chip, the operation of the semiconductor memory device 600 is turned off.

Herein, the operation of the memory device 600 being turned off means that the memory device 600 does not output data, does not receive input data, does not accept an input command, or the like. it means. When the memory device 600 performs this operation, the user of the memory device 600 may know that there is a defect in the memory device 600.

When the test result signal TRST of the first level is generated, the memory device 600 outputs data of an output driver (not shown) or the memory device 600 in the memory device 600 in response to the test result signal TRST. Semiconductor memory by turning off an operation of one of an output controller (not shown), an input driver (not shown), an input command (not shown), and an input controller (not shown) that controls an address. Causes the entire operation of device 600 to be turned off.

The output driver generally exists inside the memory device 600 and outputs data stored in the memory cell to the outside, and the output controller controls an operation of outputting data stored in the memory cell to the outside in the memory device 600. The part to say is collectively.

When the test result signal TRST is at the first level, the test result signal TRST may be applied to the output driver or the output control unit so that the output driver or the output control unit does not operate.

The input driver generally exists inside the memory device 600 and is a part of data input from the outside, and the input controller is a part for controlling an operation of storing data input from the outside into the memory cell inside the memory device 600. do.

When the test result signal TRST is at the first level, the test result signal TRST may be applied to the input driver or the input control unit so that the input driver or the input control unit does not operate.

According to the logic level of the test result signal TRST, there are various methods of controlling the operations of the output driver, the output control unit, the input driver, and the input control unit.

In addition, the meaning that the operation of the memory device 600 is turned off is not limited to the above-described meanings, and when there is a defect in the memory device 600, the memory device 600 does not operate normally and thus the externally It can include any case that can be recognized.

The structures of the first and second memory blocks 610 and 620 and the comparator 630 of the memory device 600 of FIG. 6 are the first and second memory blocks 510 and 520 and the comparator shown in FIG. 5. It may be the same as the structure of 530. In this case, the defect signal FS generated by the comparator 540 has the same function as the test result signal TRST.

The structures of the first and second memory blocks 610 and 620 and the comparator 630 of the memory device 600 of FIG. 6 are the first and second memory blocks 510 and 520 and the comparator shown in FIG. 5. Even in the case of the structure 530, the operation principle of the memory device 600 of FIG. 6 is the same as described above, and thus a detailed description thereof will be omitted.

FIG. 7 is a diagram for describing a memory module including a plurality of memory devices of FIG. 6.

The memory module 700 of FIG. 7 is similar to the memory module 200 of FIG. 2 but does not include the second module NC pin M_NC2. The second module NC pin M_NC2 is a pin that outputs the test result signal TRST output from the memory chips CP1 to CPn in the memory module 200 to the outside of the module 200.

However, since the memory devices CP1 to CPn mounted in the memory module 700 of FIG. 7 have the same structure as that of the memory device 600 of FIG. 6, the test result signal TRST is not output to the outside. Therefore, a separate pin for outputting the test result signal TRST to the outside of the memory module 700 is not required.

The test modes are determined in response to the test mode signal TMODE input through the first module NC pin M_NC1 of the memory devices CP1 to CPn of the memory module 700. In the test mode, an operation of simultaneously testing the first memory block 610 and the second memory block 620 described above is performed.

The test mode signal TMODE may be generated by a mode register set (MRS) or by a DC voltage having a constant voltage level.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the memory module according to the present invention is suitable for a mounting test by rereading the written test data and has an advantage of reducing test time.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a parallel test apparatus of a conventional semiconductor memory device.

2 is a diagram illustrating a memory module according to an exemplary embodiment of the present invention.

FIG. 3A is a diagram illustrating a case where the memory chip of FIG. 2 has a pin structure.

FIG. 3B is a diagram illustrating a case in which the memory chip of FIG. 2 has a ball structure.

4 is a circuit diagram illustrating an internal structure of a memory chip inside the memory module of FIG. 2 according to an exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an internal structure of a memory chip inside the memory module of FIG. 2 according to another exemplary embodiment.

6 is a diagram illustrating a memory device according to another exemplary embodiment of the present invention.

FIG. 7 is a diagram for describing a memory module including a plurality of memory devices of FIG. 6.

Claims (43)

A plurality of memory chips; A first module NC pin receiving a test mode signal and applying the test mode signal to a first NC pin of each of the memory chips; And A second module NC pin for receiving a test result signal indicating whether the memory chip is a defective chip or a normal chip from a second NC pin of each of the memory chips, Each of the memory chips, Simultaneously test different internal memory blocks and output the test result signal through the second NC pin; And outputting test data of one memory block among the different memory blocks. The memory chip of claim 1, wherein each of the memory chips comprises: And testing the N-bit memory cells and outputting the test data corresponding to the N / 2-bit memory cells. The method of claim 1, wherein the different memory blocks, And a memory module arranged in the same bank. The method of claim 1, wherein the test mode signal, Memory module, characterized in that generated by the Mode Register Set (MRS). The method of claim 1, wherein the test mode signal, And a direct current voltage having a constant voltage level. The memory chip of claim 1, wherein each of the memory chips comprises: At least one first and second memory block; A sense amplifier for amplifying and outputting test data written to the at least one first and second memory blocks; And The test result signal is generated by comparing the test data of the at least one first memory block with the test data of the at least one second memory block corresponding to the test data. And a comparator for outputting test data of one memory block. The method of claim 6, wherein the comparison unit, First comparing means for comparing any test data of the at least one first memory block with test data of the at least one second memory block corresponding to the arbitrary test data; And And second comparing means for comparing the outputs of the first comparing means to generate the test result signal. The method of claim 7, wherein the first and second comparison means, A memory module, characterized in that it is exclusive logical OR means. The method of claim 1, And the memory chip generating the test result signal is a defective chip if the test result signal is a first level, and the memory chip generating the test result signal is a normal chip if the test result signal is a first level. A plurality of memory chips; And A first module NC pin that receives a test mode signal and applies it to a first NC pin of each of the memory chips; Each of the memory chips, Test different memory blocks inside at the same time, And if each of the memory chips is a normal chip, outputs test data of one of the different memory blocks, and outputs a defect signal if the chips are defective. The method of claim 10, wherein each of the memory chips, And testing the N-bit memory cells and outputting the test data corresponding to the N / 2-bit memory cells. The method of claim 10, wherein the different memory blocks, And a memory module arranged in the same bank. The method of claim 10, wherein the test mode signal, Memory module, characterized in that generated by the Mode Register Set (MRS). The method of claim 10, wherein the test mode signal, And a direct current voltage having a constant voltage level. The method of claim 10, wherein each of the memory chips, At least one first and second memory block; A sense amplifier for amplifying and outputting test data written to the at least one first and second memory blocks; And The test data of the at least one first memory block and the test data of the at least one second memory block corresponding to the test data are the same or different and output the test data in response to a comparison result. Or a comparator for outputting the defect signal. The method of claim 15, wherein the comparison unit, First comparing means for comparing any test data of the at least one first memory block with test data of the at least one second memory block corresponding to the arbitrary test data; And And output parts generating the defect signal when the output of the first comparing means is the first level and generating the test data when the output of the first comparing means is the second level. The method of claim 16 wherein the first comparison means, A memory module, characterized in that it is exclusive logical OR means. The method of claim 16, wherein the output unit, respectively, PMOS transistors for outputting said test data in response to outputs of said first comparing means; And And NMOS transistors for outputting the defect signal in response to the output of the first comparing means. The method of claim 18, wherein the defect signal, And a power supply voltage level or a ground voltage level or a constant voltage level. At least one first memory block and at least one second memory block; And In the test mode, a comparison unit for generating a test result signal by comparing whether the test data stored in the at least one first memory block and the test data stored in the at least one second memory block is the same or different, The comparison unit, When the test data stored in the first memory block and the test data stored in the second memory block are the same, one of the test data stored in the first memory block and the test data stored in the second memory block is output. Semiconductor memory device. The method of claim 20, wherein the test result signal, If the test data stored in the first memory block and the test data stored in the second memory block are not the same, the test data is generated at a first level. When the test data stored in the first memory block and the test data stored in the second memory block are the same, the test data is generated at a second level. In the test mode And the test data written in the first memory block and the second memory block is the same. The method of claim 21, wherein the at least one first memory block and the at least one second memory block, A semiconductor memory device, characterized in that arranged in the same memory bank (bank) or each in a separate memory bank. The method of claim 21, wherein when the test result signal is generated at the first level, And the operation of the semiconductor memory device is turned off. The test result signal of claim 21, wherein the test result signal of the first level comprises: Turning off an operation of one of an output driver, an output controller for controlling data output of the memory device, an input driver, an input command, and an address controlling the address so that the entire operation of the semiconductor memory device is turned off. A semiconductor memory device. 21. The semiconductor memory device according to claim 20, further comprising a sense amplifier for amplifying and applying test data written to the at least one first and second memory blocks to the comparison unit. The method of claim 20, wherein the comparison unit, First comparing means for comparing any test data of the at least one first memory block with test data of the at least one second memory block corresponding to the arbitrary test data; And And second comparing means for comparing the outputs of the first comparing means to generate the test result signal. The method of claim 26, wherein the first and second comparison means, A semiconductor memory device, characterized in that it is exclusive logical OR means. The method of claim 20, And if the test result signal is a first level, the memory chip generating the test result signal is a defective chip, and if the test result signal is the second level, the memory chip generating the test result signal is a normal chip. The test mode signal of claim 20, wherein the test mode is determined in response to an input test mode signal. A semiconductor memory device, characterized in that it is generated by a Mode Register Set (MRS) or by a DC voltage having a constant voltage level. The method of claim 20, wherein the comparison unit, First comparing means for comparing any test data of the at least one first memory block with test data of the at least one second memory block corresponding to the arbitrary test data; And And output parts which generate a defect signal when the output of the first comparison means is a first level and generate the test data when the output of the first comparison means is a second level. The method of claim 30, wherein the first comparison means, A semiconductor memory device, characterized in that it is exclusive logical OR means. The method of claim 30, wherein the output unit, respectively, PMOS transistors for outputting said test data in response to outputs of said first comparing means; And And NMOS transistors for outputting the defect signal in response to the output of the first comparison means. The method of claim 30, wherein the defect signal, A semiconductor memory device, characterized in that the power supply voltage level or ground voltage level or a constant voltage level. A plurality of memory chips; And A first module NC pin that receives a test mode signal and applies it to a first NC pin of each of the memory chips; Each of the memory chips, And simultaneously testing different memory blocks therein and outputting test data of one memory block among the different memory blocks if the tested memory chip is a normal chip. The method of claim 34, wherein each of the memory chips, And testing the N-bit memory cells and outputting the test data corresponding to the N / 2-bit memory cells. The method of claim 34, wherein each of the memory chips, At least one first memory block and at least one second memory block; And In the test mode, a comparison unit for generating a test result signal by comparing whether the test data stored in the at least one first memory block and the test data stored in the at least one second memory block is the same or different, The comparison unit, When the test data stored in the first memory block and the test data stored in the second memory block are the same, one of the test data stored in the first memory block and the test data stored in the second memory block is output. Memory modules. The method of claim 36, wherein the test result signal, If the test data stored in the first memory block and the test data stored in the second memory block are not the same, the test data is generated at a first level. When the test data stored in the first memory block and the test data stored in the second memory block are the same, the test data is generated at a second level. In the test mode And the test data written in the first memory block and the second memory block is the same. The method of claim 36, wherein the at least one first memory block and the at least one second memory block, The memory module, characterized in that arranged in the same memory bank (bank) or each separate memory bank. The method of claim 36, wherein when the test result signal is generated at the first level, And the operation of the memory chip is turned off. The test result signal of claim 36, wherein the test result signal of the first level comprises: Turning off the operation of one of an output driver, an output control unit for controlling data output of the memory chip, an input driver, an input command and an address, so that the entire operation of the memory chip is turned off. Memory module. 37. The memory module of claim 36, further comprising a sense amplifier for amplifying and applying test data written to the at least one first and second memory blocks to the comparison unit. The method of claim 36, wherein the comparison unit, First comparing means for comparing any test data of the at least one first memory block with test data of the at least one second memory block corresponding to the arbitrary test data; And And second comparing means for comparing the outputs of the first comparing means to generate the test result signal. The method of claim 42, wherein the first and second comparison means are: A semiconductor memory device, characterized in that it is exclusive logical OR means.