KR20060084630A - Semiconductor memory device having dynamic dq width control for current reduction - Google Patents

Abstract

Disclosed is a semiconductor memory device capable of receiving a DQ number selection signal from an outside of a semiconductor memory device and activating only a corresponding sense amplifier according to the DQ number selection signal to reduce current consumption of data read / write.

DQ can select signal

Description

Semiconductor memory device having dynamic DQ width control for current reduction

1 is a block diagram showing the configuration of a device of a semiconductor memory having a conventional DQ number control method.

2 shows a sub-column address map for each IO width.

3 is a block diagram illustrating an embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

4 is a block diagram illustrating another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

5 is a block diagram illustrating still another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

6 is a block diagram illustrating still another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of turning on / off a plurality of IOs for each DQ during data writing and reading.

Increasing the characteristic efficiency of the operation in semiconductor memory devices and reducing the current consumption is a common trend. In particular, as the importance for low power devices increases, it is also important to reduce the current consumption of data read / write operations in the semiconductor memory device. .

 In order to write / read the memory cell data, a large amount of current is consumed. In particular, a semiconductor memory device having a plurality of IOs generates much more current.

In order to reduce the current consumption, a technique of controlling a plurality of IOs for each DQ to turn on / off a corresponding sense amplifier has been developed.

1 is a block diagram showing a configuration of a device of a semiconductor memory having a conventional DQ number control method and a data path.

Referring to FIG. 1, a semiconductor memory device 100 having a conventional DQ number control scheme includes a memory cell array 101, a column decoder 102 connected to a memory cell 101, a row decoder 103, and a memory cell ( And a sense amplifier circuit 104, an input / output buffer 105, and a data input / output pin 106 for amplifying and driving data input / output at 101. In addition, the semiconductor memory device 100 receives an address input circuit 107 for receiving an address signal, a column address output from the address input circuit 107, and selects a column address for selecting a column address of the memory cell 101. A circuit 108, a row address selection circuit 109 for receiving a row address output from the address input circuit 107 and selecting a row address of the memory cell 101, and a DQ number selection signal generation circuit 110; do.

The DQ number selection signal generation circuit 110 generates a DQ number selection signal for controlling the number of sense amplifiers activated according to the DQ number.

In the memory cell data accessed in FIG. 1, the charge is carried on the IO line or the IO line charge is carried on the bit line. In the former case, the data is read from the memory cell 101. In the latter case, the data is written into the memory cell 101. This operation is a column operation for writing / reading cell data. Before the CSL (column selection line) is enabled, the IO line is precharged to the VCC level. When CSL is enabled, the IO precharge operation is stopped and the write / read operation occurs.

In the read operation, after charge sharing occurs between the bit line and the IO line, the IO sensing enable signal IOSE_EN becomes logic high and the read data is output by the voltage difference.

The DQ number selection signal generation circuit 110 of the conventional semiconductor memory device 100 shown in FIG. 1 is configured with a mode register set (MRS). That is, the DQ number selection signal is generated through the internal control signal and output to the column decoder 102, the row decoder 103, and the sense amplifier circuit unit 104, and a plurality of IO lines may be turned on / off for each DQ. .

However, since the DQ number selection signal of the conventional semiconductor memory device 100 is generated internally through the MRS, it is inconvenient to use for testing in a wafer state. Accordingly, there is a need for a semiconductor memory device capable of externally applying a DQ number selection signal.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device capable of reducing current consumption by activating only a sense amplifier and an IO line required for each DQ when writing and reading data.

Another object of the present invention is to provide a semiconductor memory device capable of directly inputting a DQ number selection signal from the outside.

In order to achieve the object of the present invention as described above, according to a feature of the present invention, a semiconductor memory device is connected to a bit line for receiving and transmitting data from a memory cell is activated by the number according to the DQ number selection signal An address and a DQ number selection signal input unit for receiving a plurality of sense amplifiers, address signals and the DQ number selection signals, and outputting the received DQ number selection signals to the plurality of sense amplifiers, column decoders and row decoders, the memory A column address selection circuit capable of selecting a column address of a cell, and a row address selection circuit capable of selecting a row address of the memory cell, wherein the column address selection circuit and the row address selection circuit comprise the address and the DQ number selection signal. The column in response to an address signal output from an input unit It selects the dress and the row address.

According to another aspect of the present invention, a semiconductor memory device includes a plurality of sense amplifiers connected to a bit line for receiving and transmitting data from a memory cell and activated by the number according to the DQ number selection signal, and the DQ number selection signal. An external PAD that is input and outputs the DQ number selection signal to the plurality of sense amplifiers, row decoders and column decoders, an address input unit for receiving an address, a column address selection circuit for selecting a column address of the memory cell, and the And a row address selection circuit capable of selecting a row address of a memory cell, wherein the column address selection circuit and the row address selection circuit comprise the column address and the row address in response to an address signal output from the address and the DQ number selection signal input unit. Select.

According to still another aspect of the present invention, a semiconductor memory device includes a plurality of sense amplifiers connected to bit lines for receiving and transmitting data from a memory cell and activated as many as the number of DQ number selection signals and the DQ number selection signals. A plurality of DQ number selection signal input / output pins for receiving the input and outputting the DQ number selection signal to the plurality of sense amplifiers, row decoders, and column decoders, an address input unit for receiving an address, and a column address of the memory cell can be selected. A column address selection circuit and a row address selection circuit capable of selecting a row address of the memory cell, wherein the column address selection circuit and the row address selection circuit respond to an address signal output from the address and DQ number selection signal input unit. Select the column address and the row address Choose.

According to still another aspect of the present invention, a semiconductor memory device includes a plurality of sense amplifiers and DQ number selection control signals connected to bit lines for receiving and transmitting data from memory cells and activated as many as DQ number selection signals. Generating the DQ number selection signal in response to the received DQ number selection control signal input / output pin and the DQ number selection control signal and outputting the generated DQ number selection signal to the plurality of sense amplifiers, row decoders and column decoders A DQ number selection signal generation unit, an address input unit for receiving an address, a column address selection circuit for selecting a column address of the memory cell, and a row address selection circuit for selecting a row address of the memory cell, A column address selection circuit and a row address selection circuit are used for the address and DQ repair. In response to the address signal output from the signal input unit selects the column address and row address.

In order to fully understand the present invention, the advantages of the operability of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 shows a sub-column address map for each IO width.

That is, FIG. 2 shows a sub column address map when the IO width is X1, X2, X4, X8, and X16. Referring to FIG. 2, in case of X16, all 16 DQs should be enabled. However, in case of X8, only 1/2 of the DQs are sufficient, and in case of X4, only 1/4 of the DQs are enabled. In the case of, only 1/8 DQ is enabled, and in case of X1, only one DQ is enabled.

In other words, in case of X8, data is output by integrating 2DQ into one DQ, and in case of X4, data is output by integrating 4DQ into one DQ, and in case of X2, 8DQ is integrated into one DQ. In this case, data can be output by combining 16DQ into one DQ. Using this control scheme, arithmetic can result in a reduction of current and power from 1/16 to 1/2.

3 is a block diagram illustrating an embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

Referring to FIG. 3, a semiconductor memory device 300 according to an embodiment of the present invention may receive and transmit data from a memory cell array 301, a column decoder 302, a row decoder 303, and a memory cell. And a sense amplifier circuit section 304, an input / output buffer 305, and a data input / output pin 306, each comprising a plurality of sense amplifiers connected to a bit line for activation according to the number of DQ number selection signals. And an address and a DQ number selection signal input circuit 307 for receiving a DQ number selection signal and outputting the received DQ number selection signal to the column decoder 302, the row decoder 303, and the sense amplifier circuit unit 304. ), A column address selection circuit 308 capable of selecting the column address of the memory cell 01, and a row address selection circuit 309 capable of selecting the row address of the memory cell 301.

The column address selection circuit 308 and the row address selection circuit 309 select the column address and the row address in response to the address signal output from the address and DQ number selection signal input circuit 307.

The semiconductor memory device 300 of FIG. 3 is configured to externally apply the DQ number selection signal to the address input circuit 307 so that the DQ number selection signal is externally connected to the address without using the DQ number selection signal generation circuit. You get an effect that you can process together. In addition, compared to the semiconductor memory device 100 shown in FIG. 1, the scheme of the circuit can be configured more simply.

Referring to FIG. 3, a detailed operation method will be described. If an external DQ number selection signal is input to select a DQ number corresponding to 1/2 from the outside, the DQ number selection signal and the address input circuit 307 select the DQ number. The signal is output to the sense amplifier circuit section 304 so that only the sense amplifier corresponding to the number of DQs is activated. That is, only one half of the sense amplifiers of the selected column blocks (or low blocks) are activated to prevent current consumption of the remaining sense amplifiers.

In addition, when the DQ number selection signal corresponding to 1/4 is input, only one quarter of the sense amplifiers of the selected column blocks are activated. When the DQ number selection signal corresponding to 1/8 is input, the selected column block is input. Only one eighth of all sense amplifiers are active.

4 is a block diagram illustrating another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

Compared to the semiconductor memory device 300 of FIG. 3, the semiconductor memory device 400 according to another exemplary embodiment illustrated in FIG. 4 may have an external PAD (not an address input circuit 407). Integrated input via 410. That is, the semiconductor memory device 400 illustrated in FIG. 4 directly inputs the DQ number selection signal to the row decoder 403, the column decoder 402, and the sense amplifier circuit unit 404 through the external PAD 410. .

The semiconductor memory device 400 illustrated in FIG. 4 may directly apply a DQ number selection signal from the outside, and thus may be usefully used for testing in a wafer state.

5 is a block diagram illustrating still another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

The semiconductor memory device 500 according to an exemplary embodiment of the present invention illustrated in FIG. 5 receives a DQ number selection signal through the DQ number selection signal input / output pin 510 instead of the external PAD 410 of FIG. 4. . That is, a plurality of DQ number selection signal input / output pins 510 are provided to directly receive the DQ number selection signal, and the DQ number selection signal is applied to the row decoder 503, the column decoder 502, and the sense amplifier circuit unit 504. do.

6 is a block diagram illustrating still another embodiment of a semiconductor memory device having a DQ number control scheme according to the present invention.

The semiconductor memory device 600 of FIG. 6 further includes a DQ number selection signal generation circuit 611 in the semiconductor memory device 500 of FIG. 5 to control the DQ width.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the semiconductor memory device according to the present invention, the current consumption can be reduced by activating only the sense amplifier and the IO line required for each DQ when writing / reading data, and the DQ number selection signal can also be directly input from the outside.

Claims (8)

A plurality of sense amplifiers connected to bit lines for receiving and transmitting data from the memory cells and activated as many as the number according to the DQ number selection signal; An address and DQ number selection signal input unit for receiving an address signal and the DQ number selection signal and outputting the received DQ number selection signal to the plurality of sense amplifiers, column decoders, and row decoders; A column address selection circuit capable of selecting a column address of the memory cell; And A row address selection circuit capable of selecting a row address of the memory cell, And the column address selection circuit and the row address selection circuit select the column address and the row address in response to an address signal output from the address and the DQ number selection signal input unit. The method of claim 1, And a plurality of sense amplifiers, in response to the DQ number selection signal, input / output lines are turned on / off so that only a corresponding sense amplifier is activated and corresponding to the activated DQ, and input / output data. A plurality of sense amplifiers connected to bit lines for receiving and transmitting data from the memory cells and activated as many as the number according to the DQ number selection signal; An external PAD receiving the DQ number selection signal and outputting the DQ number selection signal to the plurality of sense amplifiers, row decoders and column decoders; An address input unit for receiving an address; A column address selection circuit capable of selecting a column address of the memory cell; And A row address selection circuit capable of selecting a row address of the memory cell, And the column address selection circuit and the row address selection circuit select the column address and the row address in response to an address signal output from the address and the DQ number selection signal input unit. The method of claim 3, wherein And a plurality of sense amplifiers, in response to the DQ number selection signal, input / output lines are turned on / off so that only a corresponding sense amplifier is activated and corresponding to the activated DQ, and input / output data. A plurality of sense amplifiers connected to bit lines for receiving and transmitting data from the memory cells and activated as many as the number according to the DQ number selection signal; A plurality of DQ number selection signal input / output pins for receiving the DQ number selection signal and outputting the DQ number selection signal to the plurality of sense amplifiers, row decoders, and column decoders; An address input unit for receiving an address; A column address selection circuit capable of selecting a column address of the memory cell; And A row address selection circuit capable of selecting a row address of the memory cell, And the column address selection circuit and the row address selection circuit select the column address and the row address in response to an address signal output from the address and the DQ number selection signal input unit. The method of claim 5, wherein And a plurality of sense amplifiers, in response to the DQ number selection signal, input / output lines are turned on / off so that only a corresponding sense amplifier is activated and corresponding to the activated DQ, and input / output data. A plurality of sense amplifiers connected to bit lines for receiving and transmitting data from the memory cells and activated as many as the number according to the DQ number selection signal; A DQ number selection signal input / output pin for receiving a DQ number selection control signal; A DQ number selection signal generator configured to generate the DQ number selection signal in response to the DQ number selection control signal and to output the generated DQ number selection signal to the plurality of sense amplifiers, row decoders, and column decoders; An address input unit for receiving an address; A column address selection circuit capable of selecting a column address of the memory cell; And A row address selection circuit capable of selecting a row address of the memory cell, And the column address selection circuit and the row address selection circuit select the column address and the row address in response to an address signal output from the address and the DQ number selection signal input unit. The method of claim 7, wherein And a plurality of sense amplifiers, in response to the DQ number selection signal, input / output lines are turned on / off so that only a corresponding sense amplifier is activated and corresponding to the activated DQ, and input / output data.

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