KR20050053505A - Semiconductor device and the method of testing the same - Google Patents

Abstract

One problem to be solved by one of the inventions included in the present application is that a plurality of output pins can be collected and the simultaneous test of the plurality of output pins can be performed with the number of channels of the semiconductor test apparatus smaller than the number of output pins of the semiconductor device. A semiconductor device and a test method thereof are provided. One of the typical inventions includes an Ex-OR circuit 6 for inverting the polarity of the constant voltage and the negative voltage for driving a gate line in an LCD driver which is a semiconductor device having a function of driving a gate line of a liquid crystal panel. In order to control the state of the tri-state type inverter circuit 9 and the Ex-OR circuit 6 and the tri-state type inverter circuit 9 which can control the output circuit for driving a line in a high impedance state, at least one The test control terminal TEST is provided, and at the time of testing, only one terminal of the gate output is configured to perform a simultaneous test of a plurality of gate outputs as a constant voltage VGH or a negative voltage VGL output and other high impedance states.

Description

Semiconductor device and test method therefor {SEMICONDUCTOR DEVICE AND THE METHOD OF TESTING THE SAME}

<Related application>

This application claims the priority of Japanese Patent Application No. 2003-404691 for which it applied on December 3, 2003, The content is taken in here.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a test method thereof, and more particularly to a semiconductor device such as an LCD driver having a function of driving a gate line of a liquid crystal panel, and a technology effective for applying the test method thereof.

EMBODIMENT OF THE INVENTION The technique which this inventor examined as a premise of this invention is demonstrated using FIGS. 16-19. Fig. 16 shows the connection relationship between the liquid crystal panel and the LCD driver, Fig. 17 shows the connection relationship between the LCD driver and the semiconductor test apparatus, Fig. 18 shows the configuration of the inverter circuit 30 of Fig. 17, and Fig. 19 shows the operation of the gate output of the LCD driver. It is a figure which shows each.

As shown in FIG. 16, the liquid crystal panel 500 and the LCD driver required for driving this liquid crystal panel are connected. The transistor 511 and the capacitor 512 are arranged in each pixel 510 of the liquid crystal panel 500, and the source terminals of the transistors in the vertical direction shown in common are common. Similarly, the gate terminal of each transistor of the horizontal direction shown is also common.

In general, in order to drive the liquid crystal panel 500, a source driver 501 having a function of connecting to a source common terminal and applying a gradation voltage serving as color display information, and a horizontal to be connected to the gate common terminal shown in FIG. A gate driver 502 having a function of controlling display of pixels in the direction and a power supply circuit 503 having a function of generating a voltage necessary for operating the source driver 501 and the gate driver 502 are required. These are generally called LCD drivers, and the source driver 501, the gate driver 502, and the power supply circuit 503 may be integrated individually, or may be integrated on a single chip by integrating several functions. .

As shown in Fig. 17, when conducting an electrical operation test, an LCD driver (gate driver with built-in power circuit) 1f and a semiconductor test apparatus 100 having a function necessary for driving a gate common terminal of a liquid crystal panel are The electrical operation test is conducted in this connected state. As shown in FIG. 18, the inverter circuit (output circuit) 30 at the output terminal of the LCD driver 1f includes the level shift circuit 40, the p-channel transistor 50, and the n-channel transistor 51. It is configured to output the constant voltage VGH or the negative voltage VGL from the gate output terminal Gx in accordance with the input level H / L.

In Fig. 17, the gate output terminals G1 to Gn of the LCD driver 1f control display / non-display for each line of the liquid crystal panel (pixels in one column in the horizontal direction shown in Fig. 16). For this purpose, as shown in FIG. 19, even if the counter value (setting state) of the LCD driver 1f changes, one terminal among the plurality of gate outputs G1 to Gn must be a constant voltage VGH (display voltage) output, and otherwise. The voltage is output exclusively so as to be the negative voltage VGL (non-display voltage) output.

In the test of the LCD driver 1f, as shown in Fig. 17, the gate output terminals G1 to Gn are connected to the comparators 103 of the semiconductor test apparatus 100, respectively, and the respective gate output terminals G1 to Gn are connected. The semiconductor test apparatus 100 determines whether the voltage value is the constant voltage VGH or the negative voltage VGL. And if the voltage value shown in the LCD driver 1f is output from each gate output terminal G1-Gn in all the counter value (setting state) shown in FIG. 19, the gate output of this LCD driver 1f It is determined that there is no defect in the function of, and the test on the gate output is terminated.

On the other hand, the high precision of liquid crystal panels advances, and there exists a tendency for the output pin count of an LCD driver to increase. In the conventional LCD driver test method, as described above, each gate output terminal is connected to a comparator of a semiconductor test apparatus for testing. In addition, since the same applies to the input pins for operating the LCD driver from the semiconductor test apparatus, it is necessary to assign the number of channels of the semiconductor test apparatus to the number of input pins. For this reason, a semiconductor test apparatus having a channel equal to or greater than the input / output pin number of the LCD driver is required. For example, in a semiconductor test apparatus equipped with 256 channels, an LCD driver with 350 pins of gate output cannot be tested. There was a problem that the semiconductor test apparatus could not be tested.

In addition, in the LCD driver which drives the liquid crystal panel mounted in small devices, such as a mobile telephone, all functions (source, gate, a power supply circuit, etc.) which are required to drive a liquid crystal panel for the purpose of miniaturization of a device are carried out on one chip. There is a tendency to integrate, and the total number of pins of an LCD driver is increasing. For this reason, it is necessary to increase the number of channels of a semiconductor test apparatus by newly purchasing an expensive semiconductor test apparatus equipped with a large number of channels or by purchasing an optional product sold by a semiconductor test apparatus manufacturer. There is a problem that the manufacturing cost of the product cannot be reduced.

As a method of solving this problem, for example, Patent Literature 1 discloses a technique for providing a switching switch between an element under test and a semiconductor test apparatus. Specifically, it is disclosed that the changeover switch performs a test while sequentially switching each connection between the comparator in the semiconductor test device and the output pin of the semiconductor device based on the switch signal from the CPU in the semiconductor test device. For this reason, even if the number of output pins of a semiconductor device exceeds the channel number of a semiconductor test apparatus, a test can be performed.

[Patent Document 1] Japanese Patent Application Laid-Open No. 10-26655

However, when testing a semiconductor device with an output pin number that exceeds the channel of the semiconductor test apparatus using the technique described in Patent Document 1, since the test is performed while switching sequentially with the switch, the test time is conventionally increased. This results in an increase in the test cost. For example, in the gate output test of an LCD driver having a gate output of 350 pins, when testing using 10 channels of a semiconductor test apparatus using the technique of Patent Literature 1, a test time of 35 times as conventional is required. Done. For this reason, there arises a problem that the manufacturing cost of the semiconductor device cannot be reduced.

Therefore, in view of the above problem, the present invention provides a semiconductor device capable of simultaneously testing a plurality of output pins by aggregating a plurality of output pins and using a channel number of a semiconductor test device smaller than the number of output pins of the semiconductor device; And the test method thereof. In particular, it aims at providing the semiconductor device suitable for the LCD driver which has a function which drives the gate line of a liquid crystal panel, and its test method.

Among the inventions disclosed herein, an outline of representative ones will be briefly described as follows.

That is, the present invention is applied to a semiconductor device having a function of driving a gate line of a liquid crystal panel, the polarity inversion circuit for inverting the polarity of the positive voltage and the negative voltage for driving the gate line, and the output circuit for driving the gate line. At least one control terminal is provided for controlling the state of the state setting circuit which can be controlled to a high impedance state, and the states of the polarity inversion circuit and the state setting circuit.

Moreover, this invention is applied to the semiconductor device which has a function which drives the gate line of a liquid crystal panel, The polarity inversion circuit which inverts the polarity of the positive voltage and negative voltage which drive a gate line, and the output circuit for driving a gate line. At least one control terminal for controlling the state of the transistor capable of controlling the transistor to a high impedance state, the polarity inversion circuit and the state of the transistor.

Further, the present invention is applied to a test method of a semiconductor device having a function of driving a gate line of a liquid crystal panel, and the output of the plurality of output terminals for driving the gate line is a constant voltage output and a high impedance state, or a negative voltage output and A plurality of output terminals of a semiconductor device are tested by controlling a high impedance state and using a resistance network provided inside or outside the semiconductor device with the number of channels of the semiconductor test device smaller than the number of output terminals of the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in the whole figure for demonstrating an Example, the same code | symbol is attached | subjected to the member which has the same function in principle, and the description of the repetition is abbreviate | omitted.

<Example 1>

An LCD driver as Embodiment 1 of a semiconductor device according to the present invention will be described with reference to Figs. 1 is a configuration of an LCD driver, FIG. 2 is an equivalent circuit at the time of a test, FIG. 3 is an equivalent circuit when a failure is assumed, FIG. 4 is a setting state of a control signal, FIG. 5 is an example of a truth table of a test control circuit, Fig. 6 shows the operation of the test, Fig. 7 shows the configuration of the LCD driver of the example in which the circuit scale is reduced, and Fig. 8 shows the circuit configuration of the inverter circuit of Fig. 7, respectively.

The LCD driver according to the first embodiment is connected to a gate common terminal among a source driver, a gate driver, and a power supply circuit required to drive a liquid crystal panel as shown in FIG. 16 described above, and performs display control of pixels in the horizontal direction. The difference from the LCD driver shown in FIG. 17 described above, which is applied to a gate driver having a function of performing the same, is a tri-state inverter capable of switching the output of the inverter circuit at the output stage to a high impedance state as shown in FIG. A test control circuit for changing to a circuit (state setting circuit) 9 and providing an Ex-OR circuit (polar inversion circuit) 6 between the decode circuit 5 and the latch circuit 7 and controlling them. (Control circuit) 2 and test control terminal (control terminal) TEST are provided.

Therefore, in the LCD driver of the present embodiment, details will be described later. However, in the test by the semiconductor test apparatus, only one terminal in the gate output is a constant voltage VGH or negative voltage VGL output, and otherwise, a plurality of gate outputs. By integrating these through the resistance network, it is possible to perform simultaneous test of a plurality of gate outputs with the number of channels of the semiconductor test apparatus smaller than the number of gate outputs.

That is, the LCD driver 1 of the first embodiment includes a test control circuit 2 connected to the test control terminal TEST, and an interface circuit / register connected to the test control circuit 2 and to which an input signal is input ( 3), a counter 4 connected to this interface circuit / register 3, a plurality of decoder circuits (DEC) 5 connected in parallel to this counter 4, and each decoder circuit 5, respectively. A plurality of Ex-OR circuits 6 that are connected and to which a signal M from the test control circuit 2 is input, and a plurality of latch circuits 7 that are connected to the respective Ex-OR circuits 6 and are synchronized with the clock CLK 7. ), A plurality of tri-state inverter circuits 9 connected to each latch circuit 7 and controlled by a setting signal EnH / EnL from the test control circuit 2, and a power supply terminal Vcc, And a power supply circuit 11 for generating VGH and negative voltage VGL.

In this LCD driver 1, the input signal is a signal containing information for shifting to the pixel display of the next line of the liquid crystal panel, in which each function of driving the liquid crystal panel is integrated on the same chip, or a separate chip. Depending on whether or not is integrated into the circuit, the input may be input from an internal circuit or may be input from an external source. This input signal is input to the counter 4 via the interface circuit / register 3, and the value of the counter 4 is incremented according to the change of the input signal, and is output to the decoder circuit 5. In the decode circuit 5, according to the value of the counter 4, in the normal operation (FIG. 4) through the Ex-OR circuit 6, the latch circuit 7, and the tri-state inverter circuit 9. The gate output terminals G1 to Gn are output so as to be output voltages of VGH / VGL (input level L / H). In this normal operation, the signal M from the test control circuit 2 is "H" (High level), EnH is "L" (Low level), and EnL is "H". The operation in the test mode will be described later.

The Ex-OR circuit 6 is a polarity inversion circuit for inverting the polarities of the constant voltage and the negative voltage for driving the gate line of the liquid crystal panel, and the tri-state inverter circuit 9 has an output circuit for driving the gate line. A state setting circuit that can be controlled in an impedance state. The latch circuit (D-flip-flop circuit) 7 is provided for the purpose of maintaining the output value of the decode circuit 5 during the display period of the pixel for each line of the liquid crystal panel.

The tri-state type inverter circuit 9 is a structure of a so-called clocked inverter circuit, and as shown in FIG. 2, the level shift circuit 40 and the high withstand voltage p-channel transistor 50 constituting the normal inverter circuit. And the p-channel transistor 60, the n-channel transistor 51 and the n-channel transistor 61 of high breakdown voltage. In this tri-state type inverter circuit 9, a signal of H / L is inputted to the gate terminal EnH / EnL of the transistor 60 and the transistor 61, so that the input level H / L is shown in FIG. This makes it possible to control the high impedance state.

The purpose of using the level shift circuit 40 and the high breakdown voltage transistor is as follows. That is, since the gate output voltage VGH / VGL is a voltage several times higher than the power supply voltage Vcc for operating the LCD driver 1 of + 16.5 / -16.5V, for example, the p-channel transistor 50 and the p-channel The transistor 60, the n-channel transistor 51, and the n-channel transistor 61 are transistors of high voltage resistance that are guaranteed to operate even when a voltage of VGL from VGH, that is, a voltage of 33 V (normally higher voltage) is applied. I use it.

The transistors 50 and 60 and the transistors 51 and 61 enclosed by the circles shown in FIG. 2 show that the transistors having high breakdown voltage are used. The high breakdown voltage transistor is larger than the normal transistor size that is guaranteed for operation by the normal power supply voltage. For this reason, as shown in FIG. 2, the level shift circuit 40 is provided, and the circuit before the level shift circuit 40 is a normal transistor, and the circuit after the level shift circuit 40 is a high withstand voltage transistor. By using, the chip area of the LCD driver 1 is reduced.

In the case of performing the test, as in the test mode 1 shown in FIG. 4, the setting signal EnH = EnL = L to the tri-state inverter circuit 9 is set. At this time, if the input signal M = L of the Ex-OR circuit 6 is set, the output level of the decode circuit 5 does not change, and is input to the tri-state inverter circuit 9 through the latch circuit 7. do. Therefore, in this setting state, as shown in Fig. 6A, the portion of the negative voltage output VGL in the normal operation can be changed to the high impedance state. In addition, the detail of the setting method of the setting signal EnH / EnL to the tri-state type inverter circuit 9 and the signal M of the Ex-OR circuit 6 is mentioned later.

The LCD driver is set in the state of such a test mode, and as shown in Fig. 1, the first resistors R1 and 12 are respectively connected to the gate output terminals G1 to Gn, and the first resistors 12 are connected to each other. One end is connected in common, and the resistance network which terminates with the 2nd resistor R2 (13) at the common connection point A is provided. And connection point A is connected to the comparator 103 of the semiconductor test apparatus 100, and a test is performed. If the LCD driver 1 is not defective, as shown in Fig. 6A, only one terminal of the gate output becomes the VGH output and the other high impedance state regardless of the value of the counter 4; The circuit shown in FIG. 2 is equivalent. That is, the input voltage of the comparator 103 is a ratio of the resistance value R1 of the resistor 12 and the resistance value R2 of the resistor 13, that is,

VA = {R2 / (R1 + R2)} × VGH [V]

When the resistance values of the first resistor 12 and the second resistor 13 are the same value (R1 = R2 = R), VA = (1/2) VGH [V].

When the constant voltage VGH is output to two or more gate outputs or the voltage is not output to all gate outputs, unlike the output voltage state shown in Fig. 6A due to a failure of the decode circuit 5 or the like. A voltage value different from the voltage is input to the comparator 103 by the resistance network shown in FIG. For example, when the constant voltage VGH is output to two terminals of the gate output due to a failure, the circuit shown in Fig. 3 is equivalent. At this time, when the voltage at the connection point A input to the comparator 103 is applied to Millman's theorem,

VA = (2VGH / R1) / {(1 / Rl) + (1 / Rl) + (1 / R2)} [V]

It becomes When the resistance values of the first resistor 12 and the second resistor 13 are set to the same value (R1 = R2 = R), VA = (2/3) VGH [V], and the voltage value at the connection point A It is possible to determine whether or not a failure occurs.

In the test described above, originally, when the negative voltage VGL is outputted, the setting signal to the tri-state inverter circuit 9 is set to EnH = EnL = L to change to high impedance. In such a test, the n-channel transistor 50 shown in FIG. 2 does not always operate. For this reason, in order to perform the operation test of the n-channel transistor 50, the H / L input to the tri-state inverter circuit 9 by setting the M signal input to the Ex-OR circuit 6 to H level, Inverts the level. As shown in the test mode 2 of FIG. 4, when the setting signal to the tri-state type inverter circuit 9 is EnH = EnL = H, as shown in FIG. Only the terminal is a VGL output. Since the voltage of the connection point A input to the comparator 103 becomes the value which changed the VGH of (Equation 1) and (Equation 2) demonstrated above to VGL, it can be determined similarly whether there exists a fault.

Thus, the polarity inversion signal M to the Ex-OR circuit 6 and the setting signals EnH and EnL of the tri-state inverter circuit 9 are compared with the test mode 1 and the test mode 2 shown in FIG. By setting in this way, it is possible to simultaneously test a plurality of gate outputs in one channel of the semiconductor test apparatus.

Next, the setting of the M signal to the Ex-OR circuit 6 and the EnH and EnL signals to the tri-state inverter circuit 9 will be described. 1 shows a circuit configuration in which the test control circuit 2 generates signals of M, EnH, and EnL. Specifically, a test register (not shown) and a test control terminal TEST are prepared in the interface circuit / register 3. Writing to the test register is performed using an input signal line. The test control terminal TEST is used as a control terminal for selecting the normal operation / test mode. For example, as shown in FIG. 5, the test control circuit 2 may include a circuit that outputs M, EnH, and EnL signals in accordance with the setting values of the test control terminal and the test register.

Incidentally, the correspondence between the setting values of the test control terminal TEST and the test register of FIG. 5 and the M, EnH, and EnL signals is an example, and is not limited thereto. In addition, although the test control circuit 2 is shown independently, it may be a structure contained in the interface circuit / register 3, for example. The second resistor 13 is terminated by GND (ground), but may be terminated by any arbitrary voltage.

In this embodiment, an example in which the test control circuit 2 generates the signals M, EnH, EnL for switching the test mode in accordance with the test control terminal TEST and the setting value of the test register is shown and described. However, an object of the present invention is to perform the test by setting the output state (test modes (1) and (2)) of FIG. 6 at the time of conducting the test. It is not limited and may be changed in various ways. For example, control terminals of M, EnH, and EnL may be provided to control switching of H / L levels from the outside.

As apparent from the above description, the Ex-OR circuit 6 is a circuit capable of inverting the input / output level by the M signal for the purpose of inverting the input level to the tri-state type inverter circuit 9. If it is a structure, it does not matter even if it is not the Ex-OR circuit 6. Although shown to include a power supply circuit 11 for generating a gate output voltage VGH / VGL from the power supply voltage Vcc, the configuration includes a power supply circuit depending on the type of LCD driver, or inputs the gate output voltage VGH / VGL from an external source. It may be a constitution.

1 illustrates an example of the configuration of the LCD driver related to the gate output, and is not limited to the configuration shown. In addition, a circuit having a function not shown may be integrated on the same chip. In addition, although shown in FIG. 2 so that the level shift circuit may be built in the tri-state type inverter circuit 9, it is not necessarily provided in the same circuit.

In the present embodiment, although the entire gate output of the LCD driver is shown and described to simultaneously test in one channel of the semiconductor test apparatus, the present invention is not limited to this, but a plurality of gate outputs are aggregated into one through a resistor network, It is possible to perform a test using the number of channels of a semiconductor test apparatus smaller than the number of gate outputs. In consideration of the relationship between the number of input / output pins of the LCD driver and the total number of channels of the semiconductor test apparatus to be used, the arrangement of the gate output pins on the chip, and the like, the number of gate output aggregation and the number of channels of the semiconductor test apparatus may be determined.

In the other embodiments described below, this point will not be specifically described, but it is obvious that the same is true in the embodiments according to the present invention.

Finally, in this embodiment, a method of reducing the chip occupation area of the additional circuit will be described. The structure of the tri-state inverter circuit 9 shown in FIG. 1 can be realized by the combination of the transistors shown in FIG. 2, but as described above, the transistors used in this circuit need to use a high breakdown voltage. . For this reason, compared with the LCD driver which is the premise of the present invention, p-channel and n-channel high-voltage transistors need to be added as many as the number of gate output terminals, so that the chip area is increased and the price of the LCD driver is difficult to be reduced. do.

Therefore, as shown in Figs. 7 and 8, the LCD driver 1a in the example of reducing the circuit scale controls the transistor 65 and the transistor 66 for controlling the high impedance to the tri-state inverter circuit 10. ), And the VGH2 and VGL2 of the transistor 65 and the transistor 66 are distributed to the tri-state inverter circuits 10 so that the same operation as that shown in FIGS. 1 and 2 can be performed. . By changing to the configuration shown in Figs. 7 and 8, the number of additional high breakdown voltage transistors to be added is smaller than that shown in Figs. 1 and 2, and the effect of the increase in the chip area of the LCD driver by the application of the present invention is achieved. Can be reduced.

In FIG. 7, the transistor 65 and the transistor 66 for high impedance control are shown to be disposed independently of other circuits, but may be included in the test control circuit 2 or the power supply circuit 11. none. Although the transistors 65 and 66 are shown as one transistor each, an optimum setting system is constructed by providing a plurality of transistors in parallel in consideration of the current limitations of the transistors, resistance values, and the like. You may do it, and you may change it variously.

In the embodiments to be described later, the tri-state inverter circuit shown in Figs. 1 and 2 is shown and described, but the circuit configuration as shown in Figs. 7 and 8 may be changed.

<Example 2>

An LCD driver which is a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. Fig. 9 shows the configuration of the LCD driver, Fig. 10 shows the equivalent circuit during the test, Fig. 11 shows the configuration of the LCD driver in the example in which it is not necessary to reset the comparison voltage, and Fig. 12 shows the test pattern.

As shown in FIG. 9, the LCD driver 1b of the second embodiment is an example in which a resistance network provided between the LCD driver and the semiconductor test apparatus in the first embodiment is integrated in the LCD driver. When not implemented, a switch (switch means) 17 connected in series with the first resistor 12 is provided so that the resistance network can be separated. Since the setting of each gate output voltage and the signals of M, EnH, and EnL during the test execution (test mode) are the same as those described in the first embodiment, description thereof is omitted. The difference from the first embodiment is that the resistance network is integrated into the LCD driver 1b so that all the output voltages at the time of testing are inputted to the comparator of the semiconductor test apparatus 100 via the gate output terminal G1 to determine that Output voltage value.

Specifically, when the LCD driver 1b has no failure, the equivalent circuit when the counter value shown in Fig. 6 is 1 is as shown in Fig. 10A, and the counter value is other than 1. Is equivalent circuit of FIG. In the first embodiment, in the case of normal operation, regardless of the counter value, it is always constant at the voltage determined by the resistance ratio of the first resistor 12 and the second resistor 13, but in the present embodiment, the equivalent circuit of FIG. As can be seen, the output voltage becomes VGH or VGL only when the counter value is one. Determination of the voltage value is performed in the semiconductor test apparatus 100, but the comparison voltage value of the comparator 103 of the semiconductor test apparatus 100 is changed in the state of the counter value 1 of the LCD driver 1b and in other states. It is possible to perform a test correctly by doing this. In addition, the comparison voltage setting of the comparator 103 can be arbitrarily performed by the program for controlling the semiconductor test apparatus 100 called a test program.

In addition, the switch 17 shown in the present Example generally comprises one or a plurality of transistors. Although the first resistor 12 and the second resistor 13 are shown as being integrated in the LCD driver 1, the second resistor 13 may be changed so as to be externally connected at the time of testing without being integrated. none.

As described above, in this embodiment, when the counter value is 1 and when the counter value is other than that, the voltage input to the comparator 103 of the semiconductor test apparatus 100 is different from each other. As in the first embodiment, irrespective of the setting state of the LCD driver 1, when the input voltage of the comparator 103 is constant, it is not necessary to change the comparison voltage of the comparator during the test, but in the case of the present embodiment In the test, it is necessary to change the comparator voltage once. For this reason, compared with Example 1, a test time increases only by the comparative voltage setting of a comparator. 11 shows an example in which the test is performed without resetting the comparison voltage of the comparator 103 in the LCD driver 1b shown in the present embodiment.

In the LCD driver 1c of FIG. 11, two comparators Cp1 and Cp2 103 of the semiconductor test apparatus 100 are used to connect to the gate output terminals G1 and G2 to perform the test. When the LCD driver 1c is set in the test mode 1, when the counter value is 1, the voltage of VGH / 2 is input to the comparator Cp1 connected to G1 and the comparator Cp2 connected to G2. When the counter value is 2, the voltage of VGH is input to the comparator Cp1 connected to G1, and to the comparator Cp2 connected to G2.

Up to the above, the details of the determination by the comparator 103 of the semiconductor test apparatus 100 have not been described in detail, but the expected value H / L of the comparator output called a test pattern as shown in FIG. 12 is described. The LCD driver's acceptance judgment is made as to whether or not it matches one pattern. Here, X described in the test pattern indicates that the expected value is not determined regardless of the output value H / L of the comparator. That is, in the embodiment shown in Fig. 11, the comparison voltages of the two comparators Cp1 and Cp2 connected to the gate output are set to a constant value in order to expect VGH / 2, and only when the counter value is 1 by the test pattern. It is used to determine by the comparator connected to G2, and to determine by the comparator connected to G1 when the counter value is other counter value. For this reason, since it is not necessary to reset the comparison voltage of a comparator, test time becomes shorter than the case shown in FIG.

In addition, although the comparator 103 was connected to G1 and G2 in FIG. 11, it does not limit a connection terminal, What is necessary is just to test using two comparators. In addition, the test pattern of FIG. 12 has described the example and is not limited to this.

In Embodiments 1 and 2 described above, it is possible to confirm the exclusive operation that only one pin is outputting a voltage among the plurality of gate outputs, but it is necessary to specify which gate output pin is outputting a voltage. It is difficult. Therefore, when aiming at the high reliability of a test further, Example 3 or Example 4 mentioned next may be used.

<Example 3>

An LCD driver according to a third embodiment of the semiconductor device according to the present invention will be described with reference to FIGS. 13 and 14. Fig. 13 shows the configuration of the LCD driver, and Fig. 14 shows equivalent circuits at the time of testing.

In the LCD driver 1d of the third embodiment, a portion different from that of the first embodiment is a resistor network provided between the gate output terminals G1 to Gn and the semiconductor test apparatus 100, as shown in FIG. Configuration. Specifically, the first resistor 12 is connected between each gate output terminal, and one side (connection point A) of the first resistor 12 connected only to the gate output terminal is terminated by the second resistor 13. . The test is performed by connecting the resistance network different from the above-described first embodiment, setting it to the test mode (1) described in the first embodiment.

In the present embodiment, the voltage at the connection point A is divided by the first resistor R1 and the second resistor R2 when, for example, VGH is set when the counter value 1 in FIG. 6 (a) is set. When the voltage to be set is set to the counter value 3, the voltage divided by 2R1 and the second resistor R2, which is twice the first resistance, is. As such, the first resistor R1 is weighted. An equivalent circuit in such a case is shown in FIG. 14, and the voltage at the connection point A is

VA = {R2 / (xR1 + R2)} VGH [V]

(Where x: counter value -1)

By the voltage value at the connection point A, specific determination of the pin of the gate output voltage can also be performed simultaneously.

In addition, also in the present Example, it sets to the test mode 2 shown in FIG. 4 similarly to the said Example 1, and performs a test similarly. In addition, when the test is not brought to the voltage output state shown in Fig. 6 due to a failure, considering the equivalent circuit as described in the first embodiment, the voltage value at the connection point A is different from the value expected, and there is no failure. It is clear that can be determined.

Voltage measurement at the connection point A is measured by the voltage measuring unit 150 of the semiconductor test apparatus 100 as shown in FIG. 13. As in the first embodiment, it is also possible to make a judgment in the comparator of the semiconductor test apparatus 100, but in general, the semiconductor test apparatus 100 takes about several tens of ms to set the comparison voltage of the comparator. Since the voltage measuring unit 150 of the semiconductor test apparatus 100 measures the voltage and determines it by the determination value previously described in the test program, the speed depends on the CPU of the semiconductor test apparatus 100 or the like, so that it is determined at high speed. Can be. As in the present embodiment, when the voltage changes every time the measurement is made, the decision made by the voltage measuring unit 150 is shorter in the test time as shown in FIG. 13, and the manufacturing cost of the LCD driver 1d is reduced. Can be reduced.

However, the present embodiment is not limited to the voltage measuring unit 150 of the semiconductor test apparatus 100, and the test may be performed by a method that is optimal for conducting the test.

<Example 4>

An LCD driver as a fourth embodiment of the semiconductor device according to the present invention will be described with reference to FIG. 15 is a diagram illustrating a configuration of the LCD driver.

As shown in Fig. 15, the LCD driver 1e according to the fourth embodiment is an example in which the resistance network of the third embodiment is integrated in the LCD driver 1, except that the test network setting at the time of the test is conducted. The switch 17 connected in series with the first resistor 12 is provided so as to separate the. Since specific operation | movement, a test method, etc. are the same as that of the said Example 3, description is abbreviate | omitted. Also in this embodiment, the same effect can be obtained.

Note that the switch 17 shown in this embodiment is constituted of one or a plurality of transistors as in the second embodiment. Although the first resistor 12 and the second resistor 13 are shown as being integrated in the LCD driver 1, the second resistor 13 may be changed so as to be externally connected at the time of testing without being integrated. none.

Example 5

An LCD driver of Embodiment 5 according to the present invention will be described with reference to Figs. FIG. 1 shows the configuration of the LCD driver, and FIG. 20 shows the circuit configuration of the inverter circuit 9 of FIG.

The LCD driver 1 of the fifth embodiment changes the configuration (FIG. 2) of the inverter circuit 9 shown in the first embodiment to the circuit configuration 10 shown in FIG.

Specifically, similarly to the first embodiment, when the test mode is set as shown in FIG. 4, the gates of the p-channel transistor 50 and the n-channel transistor 51 in accordance with the level input to the inverter circuit 9. By controlling the level H / L to be input to the OR circuit 90 and the AND circuit 91, high impedance control can be performed in accordance with the input level as in the first embodiment. Hereinafter, since it is the same as that of Example 1 about a specific test method, description is abbreviate | omitted.

According to the present embodiment, since the OR circuit 90 and the AND circuit 91 for controlling with high impedance are disposed in front of the input terminal of the level shift circuit 40, like the high impedance control transistor of the first embodiment. There is no need to use a transistor with high breakdown voltage. In the circuit configuration shown in Fig. 2 of the first embodiment, the resistance (output impedance) when turned on from the gate terminal is the sum of the p-channel transistor 50 and the p-channel transistor 60, or the n-channel transistor 51. ) And the n-channel transistor 61, but in the present embodiment, as in the conventional LCD driver, the p-channel transistor 50, or the n-channel transistor 51, becomes the p-channel transistor 50, When the n-channel transistor 51 uses the same characteristics as those in the first embodiment, the on resistance of the gate terminal can be further reduced.

As mentioned above, although the inverter circuit of Example 5 was demonstrated on the premise of applying to Example 1 (FIG. 1), it is similarly applicable to Examples 2-4 (FIGS. 9, 11, 13, and 15). This can be seen clearly from the description of the above Examples 2 to 4. Also in this embodiment, the same effect can be obtained.

In the present embodiment, the level input to the gates of the p-channel transistor 50 and the n-channel transistor 51 is controlled and described using the OR circuit 90 and the AND circuit 91 as a means for making the high impedance. Note that the present invention is not limited to this circuit configuration, and similarly, any configuration can control the gate levels of the p-channel transistor 50 and the n-channel transistor 51.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Of course, it can be variously changed in the range which does not deviate from the summary.

The effects obtained by the representative ones of the inventions disclosed herein will be briefly described as follows.

(1) Simultaneous testing of a plurality of output pins can be performed with the number of channels of the semiconductor test apparatus smaller than the number of the plurality of output pins of the semiconductor device.

(2) A semiconductor test apparatus having a channel number smaller than the total number of pins of the semiconductor device can be effectively utilized.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the structure of the LCD driver in Example 1. FIG.

FIG. 2 is a diagram showing an equivalent circuit during testing in Example 1. FIG.

FIG. 3 is a diagram showing an equivalent circuit when a failure is assumed in Example 1. FIG.

4 is a diagram showing a setting state of a control signal in Example 1. FIG.

FIG. 5 is a diagram showing a truth table of a test control circuit in Example 1. FIG.

6 (a) and 6 (b) are diagrams showing the operation during the test in Example 1, FIG. 6 (a) is in the test mode 1, and FIG. 6 (b) is the test mode. Figures corresponding to (2), respectively.

FIG. 7 is a diagram showing a configuration of an LCD driver of an example in which the circuit scale is reduced in Example 1. FIG.

FIG. 8 is a diagram showing a circuit configuration of the inverter circuit of FIG. 7 according to the first embodiment. FIG.

9 is a diagram showing the configuration of an LCD driver in Example 2. FIG.

10A and 10B show an equivalent circuit during testing in Example 2, and FIG. 10A shows an equivalent circuit when the counter value is 1, and FIG. Are diagrams showing equivalent circuits when the counter value is other than 1, respectively.

FIG. 11 is a diagram showing a configuration of an example LCD driver in which the comparison voltage does not need to be reset in Example 2. FIG.

12 is a view showing a test pattern in Example 2. FIG.

FIG. 13 is a diagram showing the configuration of an LCD driver in Example 3. FIG.

FIG. 15 is a diagram showing a configuration of an LCD driver in Example 4. FIG.

Fig. 16 is a diagram showing a connection relationship between a liquid crystal panel and an LCD driver in the technology examined as a premise of the present invention.

Fig. 17 is a diagram showing a connection relationship between an LCD driver and a semiconductor test apparatus in the technology examined as a premise of the present invention.

FIG. 18 is a diagram showing the configuration of the inverter circuit of FIG. 17 in the technique examined as a premise of the present invention. FIG.

Fig. 19 is a view showing the operation of the gate output of the LCD driver in the technique examined as a premise of the present invention.

2O is a configuration diagram of an inverter circuit in Embodiment 5. FIG.

<Explanation of symbols for the main parts of the drawings>

1: LCD Driver

2: test control circuit

3: interface circuit / register

4: counter

5: decoder circuit

6: Ex-OR circuit

7: latch circuit

9: tri-state inverter circuit

11: power circuit

12: first resistance

13: second resistance

100: semiconductor test apparatus

103: comparator

Claims (10)

A semiconductor device having a function of driving a gate line of a liquid crystal panel, A polarity inversion circuit for inverting the polarity of the constant voltage and the negative voltage driving the gate line; A state setting circuit capable of controlling the output circuit for driving the gate line in a high impedance state; At least one control terminal for controlling the states of the polarity inversion circuit and the state setting circuit A semiconductor device comprising a. The method of claim 1, And a control circuit connected to said at least one control terminal for controlling the states of said polarity inversion circuit and said state setting circuit. A semiconductor device having a function of driving a gate line of a liquid crystal panel, A polarity inversion circuit for inverting the polarity of the constant voltage and the negative voltage driving the gate line; A transistor capable of controlling an output circuit for driving the gate line in a high impedance state; At least one control terminal for controlling the states of the polarity inversion circuit and the transistor A semiconductor device comprising a. The method of claim 3, And a control circuit connected to said at least one control terminal for controlling the states of said polarity inversion circuit and said transistor. The method according to any one of claims 1 to 4, The output of the plurality of output terminals for driving the gate line is controlled to a constant voltage output and a high impedance state, or a negative voltage output and a high impedance state, and the resistance network or a part of the resistance network or inside the semiconductor device, and the resistance A semiconductor device characterized by comprising a switch means capable of separating a network or a part of the resistive network during normal operation. The method of claim 5, The resistor network connects one end of the first resistor to an output terminal of each output circuit for driving the gate line of the liquid crystal panel, and commonly connects another end of the first resistor to connect the common connection point. And terminating at the second resistor. The method of claim 5, The resistor network connects a first resistor between each output terminal of an output terminal of each output circuit for driving a gate line of the liquid crystal panel, and one end of the first resistor connected between each output terminal is A semiconductor device, wherein one of the first resistors connected only to the output terminal is terminated by the second resistor. A test method of a semiconductor device having a function of driving a gate line of a liquid crystal panel, The semiconductor device is controlled by outputting a plurality of output terminals for driving the gate line to a constant voltage output and a high impedance state, or a negative voltage output and a high impedance state, and through a resistor network installed inside or outside the semiconductor device. The test method of the semiconductor device characterized by testing the several output terminal of the said semiconductor device by the number of channels of the semiconductor test apparatus smaller than the number of the output terminals of the said semiconductor device. The method of claim 8, A resistor network provided inside or outside the semiconductor device connects one end of a first resistor to an output terminal of each output circuit for driving a gate line of the liquid crystal panel, and the other end of the first resistor. Is connected in common, and the common connection point is terminated by a second resistor, and the quality determination of the semiconductor device is performed using the voltage value of the common connection point. The method of claim 8, A resistance network provided inside or outside the semiconductor device connects a first resistor between each output terminal of an output terminal of each output circuit for driving a gate line of the liquid crystal panel, and is connected between the respective output terminals. One end of one of the first resistors, in which one end of the first resistor is connected only to the output terminal, is terminated by a second resistor, and both parts of the semiconductor device are connected at a voltage value of a common connection point of the first and second resistors. A test method of a semiconductor device, characterized in that the determination is performed.