CN1624489A - Semiconductor device and the method of testing the same - Google Patents
Semiconductor device and the method of testing the same Download PDFInfo
- Publication number
- CN1624489A CN1624489A CNA2004100983146A CN200410098314A CN1624489A CN 1624489 A CN1624489 A CN 1624489A CN A2004100983146 A CNA2004100983146 A CN A2004100983146A CN 200410098314 A CN200410098314 A CN 200410098314A CN 1624489 A CN1624489 A CN 1624489A
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistance
- output
- semiconductor devices
- gate line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
Representative one of the inventions has such a configuration that an LCD driver, which is the semiconductor device having a function of driving a gate line of a liquid crystal display panel, comprises: an exclusive-OR circuit for inverting polarities of positive and negative voltages for driving the gate line; a tri-state type inverter circuit capable of controlling, to a high-impedance state, an output circuit for driving the gate line; and at least one of test control terminals TEST for controlling the exclusive-OR circuit and the tri-state type inverter circuit. When a test is conducted, only one terminal of the gate output outputs a positive voltage VGH or negative voltage VGL and the other terminal is set to a high-impedance state, whereby the plurality of gate outputs are simultaneously tested.
Description
The application with on Dec 3rd, 2003 Japanese patent application No.JP2003-404691 be priority application.
Technical field
The present invention relates to semiconductor devices and method of testing thereof, particularly to the such semiconductor devices and the method for testing otherwise effective technique thereof of lcd driver of function with the gate line that drives liquid crystal panel.
Background technology
The present inventor illustrates the technology of studying as prerequisite of the present invention with reference to Figure 16～Figure 19.Figure 16 is the figure of the annexation of expression liquid crystal panel and lcd driver, Figure 17 is the figure of the annexation of expression lcd driver and semiconductor test apparatus, Figure 18 is the figure of structure of the phase inverter 30 of expression Figure 17, and Figure 19 is the figure of the grid output action of expression lcd driver.
As shown in figure 16, liquid crystal panel 500 links together with the necessary lcd driver of this liquid crystal panel of driving.With illustrated form configuration transistor 511 and capacitor 512, the transistorized source terminal of each of illustrated vertical direction is shared on each pixel 510 of liquid crystal panel 500.Equally, each transistorized gate terminal of illustrated horizontal direction is also shared.
Generally in order to drive liquid crystal panel 500, be connected source electrode share on the terminal and have the function that adds the grayscale voltage that becomes the color display message source electrode driver 501, be connected grid share on the terminal and have the pixel that carries out illustrated horizontal direction show the function of control gate drivers 502, have to generate and make source electrode driver 501 and gate drivers 502 work and the power circuit 503 of the function of necessary voltage necessitates.These generally are called lcd driver, exist to compile the integrated individually respectively situations of source electrode driver 501, gate drivers 502, power circuit 503 with several functions and be integrated into a situation on the chip.
As shown in figure 17, when the electronic work of enforcement is tested, lcd driver (being built-in with the gate drivers of the power circuit) 1f that will have the shared necessary function of terminal of grid that drives liquid crystal panel is connected with semiconductor test apparatus 100, under this connection status, implements electronic the test.The phase inverter of the output stage of lcd driver 1f (output circuit) 30 as shown in figure 18, constitute by level shift circuit 40, p channel transistor 50, n channel transistor 51, become according to incoming level H/L, from the structure of grid lead-out terminal Gx output positive voltage VGH or negative voltage VGL.
In Figure 17, grid lead-out terminal G1～Gn of lcd driver 1f carries out the control of demonstration/do not show of per 1 row (1 row pixel of horizontal direction shown in Figure 16) of liquid crystal panel.Therefore, as shown in figure 19, even the count value of lcd driver 1f (set condition) changes, also necessarily having a terminal among a plurality of grid output G1～Gn becomes positive voltage VGH (display voltage) output, other become negative voltage VGL (not display voltage) output, exclusively output voltage.
The test of such lcd driver 1f as shown in figure 17, each grid lead-out terminal G1～Gn is connected on the comparer 103 of semiconductor test apparatus 100, judges that by semiconductor test apparatus 100 magnitude of voltage of each grid lead-out terminal G1～Gn is positive voltage VGH or negative voltage VGL.And if lcd driver 1f is under whole count values (set condition) state shown in Figure 19, export illustrated magnitude of voltage from each grid lead-out terminal G1-Gn, it is bad just to judge that the function of exporting about the grid of this lcd driver 1f does not have, and finishes the test about grid output.
On the other hand, exist the tendency of liquid crystal panel to the output pin number increase of height meticulous aspect development, lcd driver.The method of testing of lcd driver in the past is connected each grid lead-out terminal as mentioned above with the comparer of semiconductor test apparatus, test.In addition, equally also to being used to the input pin of lcd driver work be applied, so also need the port number of semiconductor test apparatus is distributed to the input pin number from semiconductor test apparatus.Therefore, need have the semiconductor test apparatus of passage more than the input and output pin of lcd driver, for example in the semiconductor test apparatus that 256 passages are housed, can't test grid output number is the lcd driver of 350 pins, the problem that existence can't be tested with this semiconductor test apparatus.
In driving the lcd driver that carries the liquid crystal panel in mini-plants such as mobile phone, miniaturization for equipment, exist to be integrated into a tendency on the chip driving the necessary repertoire of liquid crystal panel (source electrode, grid, power circuit), the number of pins of lcd driver more and more increases.Therefore, be necessary to carry the high price semiconductor test apparatus of a lot of passages, buy the option product that semiconductor test apparatus producer sells, the port number of semiconductor test apparatus is increased, therefore can't reduce the manufacturing cost of lcd driver by new purchase.
As the method that addresses this problem, in patent documentation 1 (spy opens flat 10-26655 communique), propose between tested element and semiconductor test apparatus, to be provided with the technology of change-over switch.Particularly, this change-over switch is according to the switching signal from the CPU in the semiconductor test apparatus, switches respectively being connected of output pin of comparer in the semiconductor test apparatus and semiconductor devices on one side successively, Yi Bian test.Therefore, even the output pin number of semiconductor devices surpasses the port number of semiconductor test apparatus, also can test.
, when the described patent documentation 1 described technology of use, when the output pin number is tested above the semiconductor devices of the passage of semiconductor test apparatus, switch successively with switch on one side, Yi Bian test, so compared with the past, cause the increase of test duration, cause testing cost to rise.For example in the grid output test of the lcd driver of grid output, use the technology of patent documentation 1, when using 10 passages of semiconductor test apparatus to test, need 35 times test duration in the past with 350 pins.Therefore, generation can't reduce the problem of the manufacturing cost of semiconductor devices.
Summary of the invention
In view of described problem, the objective of the invention is to: provide and compile a plurality of output pins, the port number of the semiconductor test apparatus that can lack with the output pin than semiconductor devices can carry out the semiconductor devices and the method for testing thereof of the test of a plurality of output pins simultaneously.Particularly its purpose is: semiconductor devices and method of testing thereof that the lcd driver of the function that is suitable for having the gate line that drives liquid crystal panel is provided.
The summary of representative invention is as follows among the present invention.
Be the semiconductor devices that the present invention is applied to have the function of the gate line that drives liquid crystal panel, have: the polarity reversal circuit that makes the polarity reversal of the positive voltage of driving grid line and negative voltage; The output circuit that is used for the driving grid line can be controlled to be the setting state circuit of high impedance status; Be used to control at least one control terminal of the state of polarity reversal circuit and setting state circuit.
In addition, the present invention is applied to have the semiconductor devices of the function of the gate line that drives liquid crystal panel, has: the polarity reversal circuit that makes the polarity reversal of the positive voltage of driving grid line and negative voltage; The output circuit that is used for the driving grid line can be controlled to be the transistor of high impedance status; Be used to control at least one control terminal of polarity reversal circuit and transistorized state.
In addition, the present invention is applied to have the method for testing of semiconductor devices of the function of the gate line that drives liquid crystal panel, the output of a plurality of lead-out terminals of driving grid line is controlled to be positive voltage output and high impedance status or negative voltage output and high impedance status, by being arranged on semiconductor device inside or outside resistance circuit network, use the port number of the semiconductor test apparatus that the output terminal subnumber than semiconductor devices also lacks to carry out the test of a plurality of lead-out terminals of semiconductor devices.
If the effect that simple declaration is obtained by representational invention in the invention of describing among the application is then as described below.
Test when (1) port number of the semiconductor test apparatus that can also lack with a plurality of output pin numbers than semiconductor devices carries out a plurality of output pin.
(2) semiconductor test apparatus that can effectively utilize port number also to lack than the number of pins summation of semiconductor devices.
Description of drawings
Following brief description accompanying drawing.
Fig. 1 is the figure of the lcd driver structure of expression embodiment 1;
The figure of equivalent electrical circuit when Fig. 2 is the test of expression embodiment 1;
Fig. 3 is among the expression embodiment 1, the figure of the equivalent electrical circuit when supposing fault;
Fig. 4 is the figure of the set condition of the control signal among the expression embodiment 1;
Fig. 5 is the figure of the truth table of the test control circuit among the expression embodiment 1;
Fig. 6 A and Fig. 6 B are among the expression embodiment 1, the figure of the action during test, and Fig. 6 A is corresponding to test pattern (1), and Fig. 6 B is corresponding to test pattern (2);
Fig. 7 is among the expression embodiment 1, reduces the figure of structure of lcd driver of the example of circuit scale;
Fig. 8 is among the expression embodiment 1, the figure of the circuit structure of the phase inverter of Fig. 7;
Fig. 9 is the figure of structure of the lcd driver of expression embodiment 2;
Figure 10 A and Figure 10 B are the figure of the equivalent electrical circuit in when test among the expression embodiment 2, and Figure 10 A represents that count value is 1 o'clock a equivalent electrical circuit, and Figure 10 B represents that count value is the equivalent electrical circuit beyond 1 time;
Figure 11 is illustrated among the embodiment 2, need not set the figure of lcd driver structure of the example of comparative voltage again;
Figure 12 is the figure of the test pattern of expression embodiment 2;
Figure 13 is the figure of the lcd driver structure of expression embodiment 3;
The figure of equivalent electrical circuit when Figure 14 is the test of expression embodiment 3;
Figure 15 is the figure of the lcd driver structure of expression embodiment 4;
Figure 16 is illustrated in the technology of studying as prerequisite of the present invention the figure of the annexation of liquid crystal panel and lcd driver;
Figure 17 is illustrated in the technology of studying as prerequisite of the present invention the figure of the annexation of lcd driver and semiconductor test apparatus;
Figure 18 is illustrated in the technology of studying as prerequisite of the present invention the figure of the phase inverter structure of Figure 17;
Figure 19 is illustrated in the technology of studying as prerequisite of the present invention the figure of the grid output action of lcd driver;
Figure 20 is the structural drawing of the phase inverter of embodiment 5.
Embodiment
Describe the embodiment of the invention with reference to the accompanying drawings in detail.It should be noted that,,, use identical symbol in principle, and the repetitive description thereof will be omitted for member with same function at the whole accompanying drawings that are used for illustrating embodiment.
(embodiment 1)
The lcd driver of the embodiment 1 of semiconductor devices of the present invention is described with reference to Fig. 1～Fig. 8.Fig. 1 is the figure of expression lcd driver structure, the figure of the equivalent electrical circuit when Fig. 2 is the expression test, Fig. 3 is the figure that the equivalent electrical circuit when fault is arranged is supposed in expression, Fig. 4 is the figure of the set condition of expression control signal, Fig. 5 is the figure of an example of the truth table of expression test control circuit, Fig. 6 is the figure of the action in when test expression, and Fig. 7 is the figure of lcd driver structure that reduces the example of circuit scale, and Fig. 8 is the figure of circuit structure of the phase inverter of presentation graphs 7.
The lcd driver of present embodiment 1 is to be applied to the foregoing necessary source electrode driver of driving liquid crystal panel shown in Figure 16, gate drivers, being connected grid in the power circuit shares on the terminal, the gate drivers of function with demonstration control of the pixel that carries out horizontal direction, be with the difference of foregoing lcd driver shown in Figure 17: as shown in Figure 1, the output of the phase inverter of output stage is changed to the ternary phase inverter (setting state circuit) 9 that can switch to high impedance status, Ex-OR circuit (polarity reversal circuit) 6 is set between decoding scheme 5 and latch cicuit 7, and is provided with test control circuit (control circuit) 2 and test control end (control terminal) TEST that is used to control them.
Therefore, in the lcd driver of present embodiment, details as described later, when testing with semiconductor test apparatus, having only 1 terminal in the grid output is positive voltage VGH or negative voltage VGL output, other are high impedance status, by resistance circuit network a plurality of grid outputs are compiled, and use the port number of the semiconductor test apparatus that also lacks than grid output number just can test simultaneously a plurality of grid outputs.
The lcd driver 1 that is present embodiment 1 is by constituting with the lower part: be connected the test control circuit 2 on the sub-TEST of test control end; Be connected on this test control circuit 2, the interface circuit/register 3 of input signal input; Be connected the counter 4 on this interface circuit/register 3; The a plurality of decoding schemes (DEC) 5 in parallel with this counter 4; Be connected on each decoding scheme 5, input is from a plurality of Ex-OR circuit 6 of the signal M of test control circuit 2; Be connected on each Ex-OR circuit 6 a plurality of latch cicuits 7 synchronous with clock CLK; Be connected on each latch cicuit 7, a plurality of ternary phase inverter 9 of the setting signal EnH/EnL of origin self-test control circuit 2 control; Be connected the power circuit 11 that power supply terminal Vcc goes up, produces positive voltage VGH and negative voltage VGL.
In this lcd driver 1, input signal is the signal that comprises the information that the pixel of the next line that is used to transfer to liquid crystal panel shows, according to being integrated on the same chip or being integrated on the different chips, there are the situation of circuit input internally and the situation of importing from the outside to each function that drives liquid crystal panel.This input signal is input to counter 4 by interface circuit/register 3, and according to the variation of input signal, the value of counter 4 increases, and outputs to decoding scheme 5.Then, in decoding scheme 5, according to the value of counter 4, by Ex-OR circuit 6, latch cicuit 7, ternary phase inverter 9, when routine action (Fig. 4), export, make each grid lead-out terminal G1～Gn become the output voltage of VGH/VGL (incoming level L/H).When this conventional action, are " H " (high level) from the signal M of test control circuit 2, EnH is that " L " (low level), EnL are " H ".The action of test pattern will be described in the back.
The structure of ternary phase inverter 9 is so-called clock control formula phase inverters, as shown in Figure 2, is made of level shift circuit 40, the high pressure p channel transistor 50 and 60 that constitutes common phase inverter, high pressure n channel transistor 51 and 61.In this three-state phase inverter 9,, as shown in Figure 4, can be controlled to be high impedance status according to incoming level H/L by the gate terminal (EnH/EnL) of transistor 60 and 61 being imported the signal of H/L.
It should be noted that, use the purpose of level shift circuit 40 and high voltage transistor as described below.Be that grid output voltage V GH/VGL for example is+16.5/-16.5V, be voltage than the high several times of power source voltage Vcc that are used to make lcd driver 1 work, so p channel transistor 50,60 and n channel transistor 51, even 61 use and to add VGH when the voltage of VGL is 33V voltage (being generally the voltage greater than it), high voltage transistor that also can safety action.
When testing, test pattern as shown in Figure 4 (1) is such, establishes the setting signal EnH=EnL=L to ternary phase inverter 9.If the input signal M=L of Ex-OR circuit 6 at this moment, the output level of decoding scheme 5 does not just change, by latch cicuit 7 to ternary phase inverter 9 inputs.Therefore under this set condition, shown in Fig. 6 (a), can change to high impedance status to the part that becomes negative voltage output VGL with the routine action.The back is described the establishing method to the signal M of the setting signal EnH/EnL of ternary phase inverter 9 and Ex-OR circuit 6 in detail.
Lcd driver is set for the state of this test pattern, as shown in Figure 1, be provided with resistance circuit network, this resistance circuit network connects first resistance (R1) 12 respectively on each grid lead-out terminal G1～Gn, the other end of this first resistance 12 links together jointly, at this points of common connection A with second resistance (R2) 13 as terminal.And, tie point A is connected on the comparer 103 of semiconductor test apparatus 100, test.When not having in the lcd driver 1 when defective, shown in Fig. 6 (a), no matter the value of counter 4 how, has only a terminal of grid output to become VGH output, other become high impedance status, so its equivalent electrical circuit as shown in Figure 2.Be the ratio that the input voltage of comparer 103 becomes the resistance value R2 of the resistance value R1 of resistance 12 and resistance R 13, that is,
VA={R2/ (R1+R2) } * VGH[V] (formula 1),
During the resistance value of first resistance 12 and second resistance 13 identical (R1=R2=R),
VA＝(1/2)VGH[V]。
Because the fault of decoding scheme 5 grades and he different with the output voltage state shown in Fig. 6 (a), in the output of the grid more than 2 or 2 during output positive voltage VGH, or all in the grids output not during output voltage, by resistance circuit network shown in Figure 1, the input magnitude of voltage different in comparer 103 with described voltage.For example, when because fault, during output positive voltage VGH, its equivalent electrical circuit as shown in Figure 3 on 2 terminals in grid output.At this moment, if use Mil Man Dingli, the voltage that then is input to the tie point A in the comparer 103 becomes:
VA=(2VGH/R1)/{ (1/R1)+(1/R1)+(1/R2) } [V] (formula 2)
When the resistance value identical (R1=R2=R) of first resistance 12 and second resistance 13, VA=(2/3) VGH[V],, can judge having or not of fault according to magnitude of voltage at tie point A.
In the test of above explanation, when output negative voltage VGL,, change to high impedance by the setting signal to ternary phase inverter 9 is set at EnH=EnL=L.When carrying out such test, n channel transistor 50 shown in Figure 2 is not worked usually.Therefore, in order to carry out the motion test of n channel transistor 50, be the M signal sets that is input in the Ex-OR circuit 6 high level, the H/L level that is input to ternary phase inverter 9 is put upside down.Then, if shown in the test pattern (2) of Fig. 4, the setting signal to ternary phase inverter 9 is set at EnH=EnL=H, then shown in Fig. 6 (b), have only a terminal of grid output to become VGL output.The voltage that is input to the tie point A of comparer 103 changes to the value that obtains behind the VGL for the VGH with described (formula 1) and (formula 2), so can judge having or not of fault equally.
Like this, by setting like that the polarity reversal signal M of Ex-OR circuit 6 and the setting signal EnH and the EnL of ternary phase inverter 9, can test a plurality of grid outputs simultaneously with a passage of semiconductor test apparatus by test pattern shown in Figure 4 (1) and test pattern (2).
Below, illustrate to the signal M of Ex-OR circuit 6 and to the setting of the EnH and the EnL signal of ternary phase inverter 9.Fig. 1 shows the circuit structure that generates M, EnH and EnL signal with test control circuit 2.Particularly, setup test register (not shown) and the sub-TEST of test control end in interface circuit/register 3.Utilize input signal cable to carry out to test writing with register.The sub-TEST of test control end uses as being used to select the control terminal of normal mode/test pattern.Test control circuit 2 (for example, as shown in Figure 5) can constitute the circuit of exporting M, EnH and EnL signal according to test control end and test with the setting value of register.
It should be noted that what Fig. 5 represented is sub-TEST of test control end and the test setting value of register and the corresponding example of M, EnH and EnL signal, but is not limited thereto.In addition, though illustrate test control circuit 2 separately, also can be the structure that for example is included in interface circuit/register 3 at this.Be connected as terminal on the GND (ground connection) at this second resistance 13, but also can be used as terminal is connected on the free voltage.
In the present embodiment, diagram has also illustrated the setting value of using register according to sub-TEST of test control end and test, generate the example of signal (M, EnH and EnL) of the switching usefulness of test patterns with test control circuit 2, but the objective of the invention is to when testing, the output state (test pattern (1), (2)) that is set at Fig. 6 is tested afterwards, be not to limit the generative circuit structure of the switching of these test patterns, can carry out various changes with signal.The control terminal of M, EnH and EnL for example also can be set, from outside switching controls H/L level.
From before this explanation as can be known, the purpose of Ex-OR circuit 6 is to be used to make the incoming level to ternary phase inverter 9 to put upside down, but so long as the circuit structure that can put upside down the input and output level according to the M signal just, can not be an Ex-OR circuit 6.Comprising the power circuit 11 that generates grid output voltage V GH/VGL from power source voltage Vcc though be illustrated as, according to the kind of lcd driver, can be the structure that comprises power circuit, also can be the structure from outside input grid output voltage V GH/VGL.
In addition, Fig. 1 has enumerated the example about the lcd driver structure of grid output, is not limited to illustrated structure.In addition, the circuit with not shown function can be integrated on the same chip.In addition, in Fig. 2, be illustrated as and in ternary phase inverter 9, organize level shift circuit, but might not be arranged in the same circuit.
In the present embodiment, diagram has also illustrated whole grid outputs of testing lcd driver with 1 passage of semiconductor test apparatus simultaneously, but the present invention is not limited thereto, can compile a plurality of grid outputs by resistance circuit network is one, uses the port number of the semiconductor test apparatus that also lacks than grid output number to test.Can consider after the relation and the configuration of grid output pin on chip of whole port numbers of semiconductor test apparatus of the input and output number of pins of lcd driver and use the use port number that compiles number and semiconductor test apparatus of decision grid output.
In other embodiment of following explanation, do not write down these points especially, but in an embodiment of the present invention, these all are the same.
At last, in the present embodiment, the method that reduces the chip occupied area that appends circuit is described.The structure of ternary phase inverter 9 shown in Figure 1 can realize with transistorized combination shown in Figure 2, but as mentioned above, the transistor that uses in this circuit is necessary to use high voltage transistor.Therefore, compare, be necessary to append according to grid output terminal subnumber respectively the high voltage transistor of p raceway groove, n raceway groove, so chip area increases, be difficult to reduce the price of lcd driver with the lcd driver of prerequisite of the present invention.
Therefore, as shown in Figure 7 and Figure 8, as the lcd driver 1a of the example that reduces circuit scale outside ternary phase inverter 10, be provided for being controlled to be the transistor 65 and 66 of high impedance in addition, by the VGH2 of transistor 65 and 66 and VGL2 are distributed to each ternary phase inverter 10, it is carried out and Fig. 1 and the same action of circuit shown in Figure 2.By changing to Fig. 7 and structure shown in Figure 8, can reduce the high voltage transistor number that appends than Fig. 1 and situation shown in Figure 2, can reduce influence in response to the chip area increase of the lcd driver that causes with the present invention.
In Fig. 7, be illustrated as and be independent of the transistor 65 and 66 that other circuit arrangement are used for high impedance control, but also can be included in the structure in test control circuit 2 or the power circuit 11.In addition, transistor 65 and 66 with a transistor diagram, is still considered transistorized electric current restriction or resistance value etc. respectively, can be arranged in parallel a plurality of transistors, constitutes best initialization system, carries out various changes.
In the embodiment of following explanation, illustrate and illustrate with Fig. 1 and ternary phase inverter shown in Figure 2, but certainly change to Fig. 7 and circuit structure shown in Figure 8.
(embodiment 2)
The lcd driver of the embodiment 2 of semiconductor devices of the present invention is described with reference to Fig. 9～Figure 12.Fig. 9 is the figure of structure of expression lcd driver, the figure of the equivalent electrical circuit when Figure 10 is the expression test, and Figure 11 is the figure of structure of lcd driver that need not set the example of comparative voltage again, Figure 12 is the figure of expression test pattern.
The lcd driver 1b of present embodiment 2 as shown in Figure 9, be that the resistance circuit network that is arranged among the embodiment 1 between lcd driver and the semiconductor test apparatus is integrated in the interior example of lcd driver, be provided with the switch (switch block) 17 of connecting with first resistance 12, thereby when not testing, can cut off resistance circuit network.Explanation is the same among each signal sets of each grid output voltage when testing (test pattern) and M, EnH, EnL and the embodiment 1, so the omission explanation.Be with the difference of described embodiment 1: its output voltage values is owing to be integrated in resistance circuit network in the lcd driver 1b, and the output voltage during test all is input in the comparer of semiconductor test apparatus 100 via grid lead-out terminal G1 to be judged.
Specifically, when lcd driver 1b did not have fault, described count value shown in Figure 6 was that 1 o'clock equivalent electrical circuit becomes Figure 10 (a), and count value is beyond 1 the time, and equivalent electrical circuit becomes Figure 10 (b).In described embodiment 1, when regular event, output voltage and count value are irrelevant, are the voltage by the resistance ratio decision of first resistance 12 and second resistance 13, are certain.But in the present embodiment, from the equivalent electrical circuit of Figure 10 as can be known, have only when count value is 1, output voltage becomes VGH or VGL.Carry out the whether qualified judgement of magnitude of voltage by semiconductor test apparatus 100.Magnitude of voltage when the comparing voltage value of the comparer 103 by making semiconductor test apparatus 100 is different from other state when the count value of lcd driver 1b is 1 state can be tested exactly.It should be noted that, can be according to the program that is used to control semiconductor test apparatus 100 that is called test procedure, the comparative voltage that compares device 103 is arbitrarily set.
In addition, illustrated switch 17 generally is made of one or more transistors in the present embodiment.And be illustrated as first resistance 12 and second resistance 13 all is integrated in the lcd driver 1, but can change to not integrated second resistance 13, and the form that when test, connects from the outside.
As mentioned above, in the present embodiment, be 1 o'clock and in addition the time in count value, be input to the voltage difference of the comparer 103 of semiconductor test apparatus 100.Embodiment 1 is such as described, regardless of the set condition of lcd driver, the input voltage of comparer 103 is a timing all, and the comparative voltage of comparer is changed, but in the present embodiment, when test, be necessary the comparative voltage of comparer is changed 1 time.Therefore, compare, can increase the test duration of the comparative voltage setting section of comparer with described embodiment 1.Therefore, Figure 11 is illustrated among the lcd driver 1b shown in the present embodiment, does not need to set the comparative voltage of comparer 103, the example of testing again.
In the lcd driver 1c of Figure 11, use 2 comparers (Cp1, Cp2) 103 of semiconductor test apparatus 100, be connected on grid lead-out terminal G1 and the G2, test.When lcd driver 1c was set at test pattern (1), count value was 1 o'clock, to be connected comparator C p1 input VGH on the G1, to being connected the voltage of the comparator C p2 input VGH/2 on the G2.In addition, when count value is 2, to be connected comparator C p1 input VGH/2 on the G1, to being connected the voltage of the comparator C p2 input VGH on the G2.
The details of carrying out whether qualified judgement of the comparer 103 of based semiconductor proving installation 100 more than has been described, but in fact, with the whether consistent whether qualified judgement of carrying out lcd driver of the expectation value H/L of the comparer output that is called test pattern shown in Figure 12 with described pattern.Here, no matter the output valve H/L that the X that records and narrates in the test pattern represents comparer how, do not carry out expectation value and judge.Promptly in the embodiment shown in fig. 11, the comparative voltage that is connected 2 comparator C p1, Cp2 in the grid output is set at certain value in order to expect VGH/2, according to test pattern, have only when count value is 1, judge with the comparer that is connected on the G2, when other count values, with judging with the comparer that is connected on the G1.Therefore, need not set the comparative voltage of comparer again, so compare during with Fig. 7, the test duration shortens.
It should be noted that, in Figure 11, on G1 and G2, be connected comparer 103, but do not limit splicing ear, can use 2 comparers to test.In addition, the test pattern of Figure 12 explanation one example is not limited thereto.
In the embodiment 1 and embodiment 2 of above explanation, can confirm in a plurality of grid outputs, to have only the exclusive action of 1 pin output voltage, but be difficult to determine which grid output pin output voltage.Therefore, in order further to improve the high reliability of test, can use the embodiment 3 or the embodiment 4 of following explanation.
(embodiment 3)
The lcd driver of the embodiment 3 of semiconductor devices of the present invention is described with reference to Figure 13, Figure 14.Figure 13 is the figure of the structure of expression lcd driver, the figure of the equivalent electrical circuit when Figure 14 is the expression test.
In the lcd driver 1d of present embodiment 3, the parts different with described embodiment 1 are arranged on the structure of the resistance circuit network between grid lead-out terminal G1～Gn and the semiconductor test apparatus 100 as shown in figure 13.Particularly, first resistance 12 is connected between each grid lead-out terminal, and an end (tie point A) that only is connected first resistance 12 on the grid lead-out terminal stops with second resistance 13.After having connected the different resistance circuit network of this and described embodiment 1, be set at described embodiment 1 in the test pattern (1) of explanation, test.
In the present embodiment, the voltage of tie point A for example is to 1 weighting of first resistance R, promptly when the count value of Fig. 6 (a) is set at 1, be VGH, when count value is set at 2, for voltage, when count value is set at 3, for 2 times the 2R1 of first resistance and the voltage of second resistance R, 2 dividing potential drops with first resistance R 1 and second resistance R, 2 dividing potential drops.Figure 14 represents equivalent electrical circuit at this moment, and the voltage of tie point A becomes:
VA={R2/ (xR1+R2) } VGH[V] (formula 3)
(wherein, x: count value-1)
According to the magnitude of voltage of tie point A, also can carry out the definite judgement of pin of grid output voltage simultaneously.
In addition, in the present embodiment, be set at test pattern shown in Figure 4 (2) equally, test equally with described embodiment 1.It should be noted that when because fault, when not becoming voltage output state shown in Figure 6 in test, consider that equivalent electrical circuit will be very clear as long as resemble embodiment 1 described, the magnitude of voltage of tie point A is different with the value of expectation, can judge having or not of fault.
The voltage determination of tie point A is measured with the voltage measuring unit for measuring 150 of semiconductor test apparatus 100 as shown in figure 13.Implement 1 like that as described, though also can judge with the comparer of semiconductor test apparatus 100, the comparative voltage that general semiconductor test apparatus 100 compares device needs the time about tens of ms when setting.The voltage measuring unit for measuring 150 of semiconductor test apparatus 100 is measured voltage, judges with the decision content that is documented in advance in the test procedure, so speed exists with ... the CPU of semiconductor test apparatus 100 etc., so can judge at a high speed.As present embodiment, when measuring voltage at every turn and all changing, as shown in figure 13, the test duration when judging with voltage measuring unit for measuring 150 shortens, and can reduce the manufacturing cost of lcd driver 1d.
, present embodiment is not limited to the voltage measuring unit for measuring 150 of semiconductor test apparatus 100, can test with the most suitable method of testing.
(embodiment 4)
The lcd driver of the embodiment 4 of semiconductor devices of the present invention is described with reference to Figure 15.Figure 15 is the figure of the structure of expression lcd driver.
The lcd driver 1e of present embodiment 4 as shown in figure 15, be that the resistance circuit network of described embodiment 3 is integrated in a example in the lcd driver 1, the switch 17 connect with first resistance 12 is set, thereby beyond can the test pattern when setting enforcement and test, cuts off resistance circuit network.Concrete action and method of testing and described embodiment 3 are same, so omit explanation.In addition, in the present embodiment, can obtain same effect.
It should be noted that illustrated in the present embodiment switch 17 and described embodiment 2 are same, are made of one or more transistors.In addition, be illustrated as first resistance 12 and second resistance 13 all are integrated in the lcd driver 1, but can change to not integrated second resistance 13, and the form that when test, connects from the outside.
(embodiment 5)
The lcd driver of the embodiment 5 of semiconductor devices of the present invention is described with reference to Fig. 1, Figure 20.Fig. 1 is the figure of structure of expression lcd driver, and Figure 20 is the figure of circuit structure of the phase inverter 9 of presentation graphs 1.
The lcd driver 1 of present embodiment 5 changes to circuit structure shown in Figure 20 10 to the structure (Fig. 2) of the phase inverter 9 shown in the embodiment 1.
Particularly, similarly to Example 1, if be set at test pattern as shown in Figure 4, just according to the level that is input to phase inverter 9, be input to the level (H/L) of the grid of p channel transistor 50 and n channel transistor 51 by OR circuit 90 and 91 controls of AND circuit, similarly to Example 1, can carry out high impedance control according to incoming level.Remaining concrete method of testing similarly to Example 1, so omit explanation.
According to present embodiment, be used to be controlled to be the OR circuit 90 of high impedance and AND circuit 91 and be configured in level and move 40 the full level of input terminal, with transistor, do not need high voltage transistor so do not resemble the high impedance control of embodiment 1.In addition, in the circuit structure shown in Figure 2 of embodiment 1, resistance (output impedance) during from conducting that gate terminal is observed be p channel transistor 50 and 60 with, or n channel transistor 51 and 61 and, but in the present embodiment, same with lcd driver in the past, become p channel transistor 50 or n channel transistor 51, so when using the p channel transistor 50 of characteristic similarly to Example 1 and n channel transistor 51, can further reduce the conducting resistance of gate terminal.
More than be prerequisite so that the phase inverter of present embodiment 5 is applied to embodiment 1 (Fig. 1), be illustrated, but from the explanation of the foregoing description 2 to 4 as can be known, can be used for embodiment 2 to 4 (Fig. 9, Figure 11, Figure 13, Figure 15) equally.In addition, in the present embodiment, also can obtain same effect.
In the present embodiment, be input to the level of the grid of p channel transistor 50, n channel transistor 51 as control, become the method for high impedance, utilize OR circuit 90 and AND circuit 91 to be illustrated, but the present invention is not limited thereto, so long as can control the structure of level of the grid of p channel transistor 50, n channel transistor 51 equally, just can.
Above according to the clear specifically invention of being undertaken by the present inventor of embodiment, but the present invention is not limited to described embodiment, can carry out various changes certainly in the scope that does not break away from its aim.
Claims (10)
1. a semiconductor devices has the function of the gate line that drives liquid crystal panel, it is characterized in that having:
Make the polarity reversal circuit of the polarity reversal of the positive voltage that drives described gate line and negative voltage;
The output circuit that is used to drive described gate line can be controlled to be the setting state circuit of high impedance status;
Be used to control at least one control terminal of the state of described polarity reversal circuit and setting state circuit.
2. semiconductor devices according to claim 1 is characterized in that having:
Be connected on described at least one control terminal, be used to control the control circuit of the state of described polarity reversal circuit and setting state circuit.
3. a semiconductor devices has the function of the gate line that drives liquid crystal panel, it is characterized in that having:
Make the polarity reversal circuit of the polarity reversal of the positive voltage that drives described gate line and negative voltage;
The output circuit that is used to drive described gate line can be controlled to be the transistor of high impedance status;
Be used to control at least one control terminal of described polarity reversal circuit and described transistorized state.
4. semiconductor devices according to claim 3 is characterized in that having:
Be connected on described at least one control terminal, be used to control the control circuit of described polarity reversal circuit and described transistorized state.
5. according to any described semiconductor devices in the claim 1～4, it is characterized in that the inside of described semiconductor devices or outside have:
Resistance circuit network is used for the output of a plurality of lead-out terminals that drive described gate line being controlled to be positive voltage output and high impedance status or being controlled to be negative voltage output and high impedance status, and
The switch block that when routine is moved, can cut off the part of described resistance circuit network and described resistance circuit network or described resistance circuit network.
6. semiconductor devices according to claim 5 is characterized in that:
Described resistance circuit network connects an end of first resistance on the lead-out terminal of each output circuit of the gate line that drives described liquid crystal panel, the public connection of the other end of described first resistance is carried out terminal at described points of common connection with second resistance and connected.
7. semiconductor devices according to claim 5 is characterized in that:
Described resistance circuit network comprises a plurality of first resistance and one second resistance, wherein said first resistance is connected respectively to adjacent pair of output of lead-out terminal of each output circuit of the gate line that drives described liquid crystal panel, described second resistance is connected on of described a plurality of lead-out terminals, and its other end to be terminal connect.
8. the method for testing of a semiconductor devices, the function with the gate line that drives liquid crystal panel of this semiconductor devices, it is characterized in that: the output of a plurality of lead-out terminals of driving grid line is controlled to be positive voltage output and high impedance status or negative voltage output and high impedance status, by being arranged on described semiconductor device inside or outside resistance circuit network, carry out the test of a plurality of lead-out terminals of described semiconductor devices than the semiconductor test apparatus that the output terminal subnumber of described semiconductor devices also lacks with port number.
9. the method for testing of semiconductor devices according to claim 8 is characterized in that:
Be arranged on described semiconductor device inside or outside resistance circuit network connect first resistance on the lead-out terminal of each output circuit of the gate line that drives described liquid crystal panel a end, the public connection of the other end of described first resistance, carry out terminal at described points of common connection with second resistance and connect, judge with the magnitude of voltage of described points of common connection whether described semiconductor devices is qualified.
10. the method for testing of semiconductor devices according to claim 8 is characterized in that:
Be arranged on described semiconductor device inside or outside resistance circuit network connection first resistance between each lead-out terminal of the lead-out terminal of each output circuit of the gate line that drives described liquid crystal panel, any one that is connected in first resistance that only is connected in first resistance between described each lead-out terminal on the described lead-out terminal carried out the terminal connection with second resistance, judges with the magnitude of voltage of the points of common connection of described first and second resistance whether described semiconductor devices is qualified.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003404691 | 2003-12-03 | ||
| JP404691/2003 | 2003-12-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1624489A true CN1624489A (en) | 2005-06-08 |
| CN100419446C CN100419446C (en) | 2008-09-17 |
Family
ID=34779854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100983146A Expired - Fee Related CN100419446C (en) | 2003-12-03 | 2004-12-03 | Semiconductor device and the method of testing the same |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR100702564B1 (en) |
| CN (1) | CN100419446C (en) |
| TW (1) | TWI254799B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123069B (en) * | 2006-08-09 | 2011-06-08 | 三星移动显示器株式会社 | Organic light emitting display and driving method of inspection circuit of organic light emitting display |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4391512B2 (en) | 2006-10-20 | 2009-12-24 | シャープ株式会社 | Electrostatic withstand voltage evaluation apparatus and electrostatic withstand voltage evaluation method |
| JP4650553B2 (en) * | 2008-10-20 | 2011-03-16 | ソニー株式会社 | LCD panel |
| KR101297657B1 (en) * | 2013-05-02 | 2013-08-21 | (주) 에이블리 | A switch circuit for testing a semiconductor element |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3142435B2 (en) * | 1994-02-15 | 2001-03-07 | 株式会社東芝 | Semiconductor integrated circuit device |
| JPH1026655A (en) * | 1996-07-11 | 1998-01-27 | Yamaha Corp | Testing apparatus for lsi |
| US6292182B1 (en) * | 1997-06-25 | 2001-09-18 | Hyundai Electronics Industries Co., Ltd. | Liquid crystal display module driving circuit |
| JP5051942B2 (en) * | 2000-02-01 | 2012-10-17 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP2003107128A (en) * | 2001-09-27 | 2003-04-09 | Ando Electric Co Ltd | Semiconductor testing device and test method |
-
2004
- 2004-11-11 TW TW093134494A patent/TWI254799B/en not_active IP Right Cessation
- 2004-12-02 KR KR1020040100274A patent/KR100702564B1/en not_active IP Right Cessation
- 2004-12-03 CN CNB2004100983146A patent/CN100419446C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101123069B (en) * | 2006-08-09 | 2011-06-08 | 三星移动显示器株式会社 | Organic light emitting display and driving method of inspection circuit of organic light emitting display |
| US8054257B2 (en) | 2006-08-09 | 2011-11-08 | Samsung Mobile Display Co., Ltd. | Organic light emitting display and driving method of inspection circuit of organic light emitting display |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100702564B1 (en) | 2007-04-04 |
| TW200519394A (en) | 2005-06-16 |
| KR20050053505A (en) | 2005-06-08 |
| TWI254799B (en) | 2006-05-11 |
| CN100419446C (en) | 2008-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100345179C (en) | Driving circuit for displaying apparatus | |
| CN1201160C (en) | Testing method and device of semiconductor integrated circuit | |
| EP3285250B1 (en) | Drive chip, drive board and test method therefor, and display device | |
| CN1357871A (en) | Electrooptical device and its testing method, testing circuit and electronic equipment | |
| JPH11167129A (en) | Liquid crystal display device having electrostatic protective circuit and display inspection method utilize this circuit | |
| CN1734322A (en) | Array base palte and have the main substrate and the liquid crystal indicator of described array base palte | |
| CN110192240B (en) | Signal protection circuit, driving method and device thereof | |
| CN102629457B (en) | Driving module of liquid crystal display | |
| CN1365092A (en) | Driver circuit for display device | |
| CN1744187A (en) | Driver element and display device with this driver element | |
| JP2010262302A (en) | Inspection method of semiconductor device | |
| CN1540398A (en) | Display device | |
| US7443373B2 (en) | Semiconductor device and the method of testing the same | |
| CN1624489A (en) | Semiconductor device and the method of testing the same | |
| CN1534360A (en) | Semiconductor device and its testing method | |
| CN1667745A (en) | Small size circuit for detecting a status of an electrical fuse with low read current | |
| CN1619328A (en) | Semiconductor device and testing method thereof | |
| CN1145213C (en) | Semiconductor integrated circuit and checking method, crystal device and electronic device | |
| CN106782240B (en) | Test circuit based on CMOS GOA | |
| CN1855311A (en) | Shift register, display device, and electronic device | |
| US20090058889A1 (en) | Display panel driver | |
| CN1581360A (en) | Logic circuit and semiconductor integrated circuit | |
| CN1855191A (en) | Scan drive circuit for plasma display panel, driving circuit for plasma display panel and plasma display apparatus using same | |
| CN108230984B (en) | Low-level voltage signal generator, gate drive circuit and display panel | |
| JPH07140439A (en) | Display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: NEC CORP. Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP. Effective date: 20100716 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: RENESAS ELECTRONICS CO., LTD. Free format text: FORMER NAME: NEC CORP. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA, JAPAN COUNTY |
|
| CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corp. Address before: Kanagawa, Japan Patentee before: NEC ELECTRONICS Corp. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20100716 Address after: Kanagawa, Japan Patentee after: NEC ELECTRONICS Corp. Address before: Tokyo, Japan Patentee before: Renesas Technology Corp. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080917 Termination date: 20131203 |